UM10208_2
© NXP B.V. 2007. All rights reserved.
User manual
Rev. 02 — 1 June 2007
53 of 362
NXP Semiconductors
UM10208
Chapter 7: LPC2800 CGU
module clock. More typically, a selection stage and base clock serve multiple spreading
stages and module clocks, which can also use the output(s) of one or more fractional
dividers.
Fractional dividers multiply their base clock input by an integer “n” and divide it by another
integer “m”. Since n must be less than m, a fractional divider’s output always has a slower
frequency than its base frequency.
Each spreading stage is connected to a particular base clock, and can enable or disable
its output clock under control of a register bit. Some spreading stages include an enable
input that allows clock pulses only when it is active: on the LPC288x this is used for
peripheral registers that do not have dynamic roles such as interrupting or change
detection, such that these registers can be clocked only when the processor is accessing
that module. A spreading stage that is connected to a fractional divider can produce
clocks under the control of the fractional divider. This can take the form of outputting a
high pulse of the base clock once per the divider’s multiply/divide period, or this pulse can
be “stretched” to provide an approximate 50-50 duty cycle of the multiply/divide period.
Finally, an output of the Event Router block is used as a “wakeup” signal that globally
enables the clocks for those spreading stages that are programmatically selected for such
wakeup.
The clocks produced by the spreading stages are used to provide clock-synchronized
reset signals for the various LPC288x modules and for sub-modules within them. Each
reset signal is asserted due to a low on the RESET pin, a watchdog timer reset, or
because software writes to a software reset register for that module or sub-module.
3.
Register descriptions
3.1 CGU configuration registers
The registers that control central aspects of the CGU are listed in
and
described individually thereafter.
Table 32.
CGU configuration registers
Name
Description
Access Reset
value
Address
PMODE
Power Mode Register.
This 2-bit register
controls whether modules selected for “wakeup”
operation receive clocking.
R/W
01
0x8000 4C00
WDBARK
Watchdog Bark Register.
Software can read
this register to determine whether a reset is due
to the Watchdog Timer.
RO
0 (RESET)
1 (WDT)
0x8000 4C04
OSC32EN
32 kHz Oscillator Control Register.
This 1-bit
register enables or disables the 32kHz oscillator.
R/W
1
0x8000 4C08
OSCEN
12 MHz Oscillator Control Register.
This 1-bit
register enables or disables the fast oscillator.
R/W
1
0x8000 4C10
