NXP Semiconductors LPC2880, User Manual

Page: 294 / 362

UM10208_2 © NXP B.V. 2007. All rights reserved.
User manual Rev. 02 — 1 June 2007 294 of 362
NXP Semiconductors
UM10208
Chapter 23: LPC2800 SD/MMC
4.3.14 Transmit FIFO
The processor or a GPDMA channel writes to the transmit FIFO once the MCI is enabled
for transmission. Data is written into the FIFO location specified by the current value of the
data pointer. The pointer is incremented after every FIFO write.
The transmit FIFO contains a data output register. This holds the data word pointed to by
the read pointer. When the data path subunit has loaded its shift register, it asserts a
signal that increments the read pointer.
If the transmit FIFO is disabled, all status flags are de-asserted, and the read and write
pointers are reset. The data path subunit asserts TxActive when it transmits data.
Table 23–329 lists the transmit FIFO status flags.
4.3.15 Receive FIFO
When the data path subunit receives a word of data, it presents it to the Receive FIFO and
asserts a strobe signal. The write pointer is incremented after the write is completed, and
the receive FIFO control logic asserts an acknowledge signal.
On the read side, the content of the FIFO word pointed to by the current value of the read
pointer is driven to the APB. The read pointer is incremented when the APB interface
asserts an acknowledge signal.
If the receive FIFO is disabled, all status flags are de-asserted, and the read and write
pointers are reset. The data path subunit asserts RxActive when it receives data.
Table 23–330 lists the receive FIFO status flags.
Table 329. Transmit FIFO status flags
Flag Description
TxFifoFull Set when all 16 transmit FIFO words contain valid data.
TxFifoEmpty Set when the transmit FIFO does not contain valid data.
TxHalfEmpty Set when 8 or more transmit FIFO words are empty. This flag can be
used as a DMA request.
TxDataAvlbl Set when the transmit FIFO contains valid data. This flag is the inverse
of the TxFifoEmpty flag.
TxUnderrun Set when an underrun error occurs. This flag is cleared by writing to the
MCIClear register.
Table 330. Receive FIFO status flags
Symbol Description
RxFifoFull Set when all 16 receive FIFO words contain valid data.
RxFifoEmpty Set when the receive FIFO does not contain valid data.
RxHalfFull Set when 8 or more receive FIFO words contain valid data. This flag can
be used as a DMA request.
RxDataAvlbl Set when the receive FIFO is not empty. This flag is the inverse of the
RxFifoEmpty flag.
RxOverrun Set when an overrun error occurs. This flag is cleared by writing to the
MCIClear register.