UM10208_2
© NXP B.V. 2007. All rights reserved.
User manual
Rev. 02 — 1 June 2007
171 of 362
NXP Semiconductors
UM10208
Chapter 14: LPC2800 UART
3.19 NHP Mode Register (MODE - 0x8010 1034)
The NHP Mode Register controls how data is removed from the receive FIFO, and how
UART interrupts are enabled and requested. NHP stands for Nexperia Home Platform.
3.20 NHP Pop Register (POP - 0x8010 1030)
3.21 Interrupt Status Register (INTS - 0x8010 1FE0)
When bit 0 of the NHP Mode register is 1, the UART interrupt request is derived from this
read-only register and the Interrupt Enable Register, which is described in a subsequent
section.
Table 186. NHP Mode Register (MODE - 0x8010 1034)
Bit
Name
Description
Reset
value
0
NHP
When this bit is 0, as it is after a reset, the UART is compatible with
other UARTs derived from the National 16x50 family, in that reading
the RBR removes the byte read from the RBR (and receive FIFO),
and the UART requests interrupts under control of the IER. When this
bit is 1, bytes must be explicitly removed from the receive FIFO by
writing to the NHP Pop Register, and the UART interrupt request is
derived from the INTS and INTE registers, which are described in
subsequent sections.
0
31:1
Reserved. Software should not write ones to reserved bits. The value
of reserved bits when read is not defined.
1
Table 187. NHP Pop Register (POP - 0x8010 1030)
Bit
Name
Description
Reset
value
When bit 0 of the NHP Mode Register is 1, writing to this write-only
register removes the byte from the RBR (and Rx FIFO). In NHP
mode, this register should be written after reading a byte from the
RBR, because doing so does not remove the byte from the RBR.
Table 188. Interrupt Status Register (INTS - 0x8010 1FE0)
Bit
Name
Description
Reset
value
0
DCTSInt
This bit is set when the CTS pin changes state, and is cleared by
writing a 1 to bit 0 of the INTCS register.
0
3:1
-
Reserved. The value of reserved bits when read is not defined.
-
4
THREInt
This bit is set when the Transmit Holding Register becomes empty (in
FIFO modes, when the Transmit FIFO becomes empty). It can be set
by writing to the THR or by writing a 1 to bit 4 of the INTCS register.
0
5
RxTOInt
This bit is set when there is at least one character in the Rx FIFO, and
no characters have been received nor read from the Rx FIFO for 4
character times. It is cleared by any of: receiving a new character,
popping the RBR, or writing a 1 to bit 5 of the INTCS register.
0
6
RxDAInt
This bit is set when the reception of a character brings the number of
received characters available to the threshold level. (In ‘450 mode the
threshold is 1 character, in FIFO modes it is controlled by bits 7:6 of
the FCR.) This bit is cleared by popping the RBR below the threshold.
0
