NXP Semiconductors LPC1102, User Manual

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User manual Rev. 1 — 20 October 2010 235 of 258
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Chapter 19: Appendix LPC1102 ARM Cortex-M0 reference
[1] This is the same value as IPSR bits[5:0], see Table 19–195 .
[2]
The NMI is not implemented on the LPC1102.
When you write to the ICSR, the effect is Unpredictable if you:
•
write 1 to the PENDSVSET bit and write 1 to the PENDSVCLR bit
•
write 1 to the PENDSTSET bit and write 1 to the PENDSTCLR bit.
19.5.3.4 Application Interrupt and Reset Control Register
The AIRCR provides endian status for data accesses and reset control of the system. See
the register summary in
Table 19–221 and Table 19–224 for its attributes.
To write to this register, you must write
0x05FA
to the VECTKEY field, otherwise the
processor ignores the write.
The bit assignments are:
[25] PENDSTCLR WO SysTick exception clear-pending bit.
Write:
0 = no effect
1 = removes the pending state from the SysTick
exception.
This bit is WO. On a register read its value is Unknown.
[24:23] - - Reserved.
[22] ISRPENDING RO Interrupt pending flag, excluding NMI and Faults:
0 = interrupt not pending
1 = interrupt pending.
[21:18] - - Reserved.
[17:12] VECTPENDING RO Indicates the exception number of the highest priority
pending enabled exception:
0 = no pending exceptions
Nonzero = the exception number of the highest priority
pending enabled exception.
[11:6] - - Reserved.
[5:0] VECTACTIVE
[1]
RO Contains the active exception number:
0 = Thread mode
Nonzero = The exception number
[1]
of the currently
active exception.
Remark: Subtract 16 from this value to obtain the
CMSIS IRQ number that identifies the corresponding bit
in the Interrupt Clear-Enable, Set-Enable,
Clear-Pending, Set-pending, and Priority Register, see
Table 19–195 .
Table 223. ICSR bit assignments
Bits Name Type Function