UM10429
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User manual
Rev. 1 — 20 October 2010
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NXP Semiconductors
UM10429
Chapter 19: Appendix LPC1102 ARM Cortex-M0 reference
19.5.3.5 System Control Register
The SCR controls features of entry to and exit from low power state. See the register
summary in
for its attributes. The bit assignments are:
Table 224. AIRCR bit assignments
Bits
Name
Type
Function
[31:16]
Read: Reserved
Write: VECTKEY
RW
Register key:
Reads as Unknown
On writes, write
0x05FA
to VECTKEY, otherwise the
write is ignored.
[15]
ENDIANESS
RO
Data endianness implemented:
0 = Little-endian
1 = Big-endian.
[14:3]
-
-
Reserved
[2]
SYSRESETREQ
WO
System reset request:
0 = no effect
1 = requests a system level reset.
This bit reads as 0.
[1]
VECTCLRACTIVE
WO
Reserved for debug use. This bit reads as 0. When
writing to the register you must write 0 to this bit,
otherwise behavior is Unpredictable.
[0]
-
-
Reserved.
Table 225. SCR bit assignments
Bits
Name
Function
[31:5]
-
Reserved.
[4]
SEVONPEND
Send Event on Pending bit:
0 = only enabled interrupts or events can wake-up the processor,
disabled interrupts are excluded
1 = enabled events and all interrupts, including disabled interrupts,
can wake-up the processor.
When an event or interrupt enters pending state, the event signal
wakes up the processor from WFE. If the processor is not waiting for
an event, the event is registered and affects the next WFE.
The processor also wakes up on execution of an
SEV
instruction.
[3]
-
Reserved.
[2]
SLEEPDEEP
Controls whether the processor uses sleep or deep sleep as its low
power mode:
0 = sleep
1 = deep sleep.
[1]
SLEEPONEXIT
Indicates sleep-on-exit when returning from Handler mode to Thread
mode:
0 = do not sleep when returning to Thread mode.
1 = enter sleep, or deep sleep, on return from an ISR to Thread
mode.
Setting this bit to 1 enables an interrupt driven application to avoid
returning to an empty main application.
[0]
-
Reserved.
