NXP Semiconductors KIT-TPLSNIFEVB, User Manual

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NXP Semiconductors
UM11650
KIT-TPLSNIFEVB tool
Contents
1 Introduction ......................................................... 3
2 Finding kit resources and information on
the NXP web site ................................................ 4
3 Getting ready .......................................................4
3.1 Kit contents ........................................................4
3.2 Additional hardware and software ..................... 5
4 Getting to know the hardware ........................... 5
4.1 KIT-TPLSNIFEVB features ................................ 5
4.2 Block diagram ....................................................6
4.3 Schematics ........................................................ 6
5 Configuring the hardware .................................. 6
5.1 Connecting to the TPL bus ................................6
5.1.1 Optional TPL bus loading ..................................7
5.2 Power and data connections ............................. 7
5.2.1 Connecting to the logic analyzer ....................... 8
5.2.1.1 Interfacing with the Saleae Logic Analyzer ........ 9
5.2.2 Powering the TPL sniffer ................................. 10
5.2.2.1 Power bank keep-alive function .......................10
6 Hardware specifications ...................................10
7 References .........................................................11
8 Legal information ..............................................12
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section 'Legal information'.
© NXP B.V. 2021. All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 4 August 2021
Document identifier: UM11650