NXP Semiconductors KIT-TPLSNIFEVB, User Manual

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NXP Semiconductors
UM11650
KIT-TPLSNIFEVB tool
4.2 Block diagram
aaa-042712
TPL
MC33664
The TPL sniffer interfaces the TPL bus
with transformer isolation
TPL frames are received and sent in SPI
format by the MC33664 and buffered by the
cable driver
Internal power supplies generate the required 3.3 V and 5 V
and implement a pulsed load to provide the power bank
keep-alive function
TPL_IN
TPL_OUT
CABLE
DRIVER
CHARGE
PUMP
LDO
Galvanic isolation
M
IC
R
O
-U
S
B
C
O
N
N
4x
2
PULSED
LOAD
5 V
3.3 V
C
O
N
N
2
x1
C
O
N
N
2
x1
Figure 4. TPL sniffer block diagram
4.3 Schematics
The schematics for the KIT-TPLSNIFEVB tool are available at http://www.nxp.com/KIT-
TPLSNIFEVB .
5 Configuring the hardware
The TPL sniffer exposes a set of connectors on two sides. One side is dedicated to
the TPL bus connection and on the other side all other connectors are present. The
two sides are galvanically isolated from each other, that is, the TPL bus connectors are
isolated from all other accessible points on the housing.
5.1 Connecting to the TPL bus
As shown in Figure 4 , the TPL connectors are located on one side of the housing and are
marked
TPL_IN
and
TPL_OUT
with a polarity indication
+
and
-
. The correct polarity of
the connection is mandatory for the proper functioning of the sniffer and, in most cases,
also for the system to be sniffed.
Conversely, the terms
IN
and
OUT
are conventional and the two connectors are
electrically in parallel inside the TPL sniffer. They are physically duplicated to make it
easier to connect the wires in certain use cases. For example, in the case of a daisy
chain, the original TPL bus is cut and the two ends must be plugged onto the receptacles
of the TPL sniffer shown in Figure 5 . In other cases, for example, when the TPL bus has
UM11650 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved.
User manual Rev. 1 — 4 August 2021
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