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6.4.3 Control/Status Register (MMDVSQ_CSR)

This register defines the operating configuration of divide operations and provides status
information. The upper 3 bits provide busy status indicators, while the low-order byte
defines the configuration for divide operations. The read-only status bits in CSR[31:29]
are valid for both divide and square root operations; the configuration and status bit in
CSR[5:0] are only valid for divides. A memory write access of the CSR register while the
module is busy during a calculation causes the access to be stalled (using wait states)
until the calculation completes.

Address: F000_4000h base + 8h offset = F000_4008h

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

R

W

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

R

0

W

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

* Notes:

x = Undefined at reset.

•

MMDVSQ_CSR field descriptions

Field

Description

31

BUSY

BUSY

This read-only bit is asserted when the MMDVSQ is performing a divide or square root. When an
operation is initiated, the hardware sets this flag. It remains asserted until the operation completes and the

Table continues on the next page...

Memory map and register definition

Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018

86

NXP Semiconductors

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Summary of Contents for Kinetis KE1xZ256

Page 1: ...KE1xZ256 Sub Family Reference Manual Supports MKE15Z256VLL7 MKE15Z256VLH7 MKE15Z128VLL7 MKE15Z128VLH7 MKE14Z256VLL7 MKE14Z256VLH7 MKE14Z128VLL7 MKE14Z128VLH7 Document Number KE1xZP100M72SF0RM Rev 3 0...

Page 2: ...Kinetis KE1xZ256 Sub Family Reference Manual Rev 3 07 2018 2 NXP Semiconductors...

Page 3: ...Conventions 47 1 5 1 Numbering systems 47 1 5 2 Typographic notation 47 1 5 3 Special terms 48 Chapter 2 Introduction 2 1 Overview 49 2 2 Block Diagram 49 2 3 Module Functional Categories 50 Chapter...

Page 4: ...71 5 2 6 Flash Configuration Register 1 SIM_FCFG1 72 5 2 7 Flash Configuration Register 2 SIM_FCFG2 74 5 2 8 Unique Identification Register High SIM_UIDH 75 5 2 9 Unique Identification Register Mid H...

Page 5: ...2 1 Features 98 7 3 Memory map register descriptions 98 7 3 1 Crossbar Switch AXBS Slave Configuration MCM_PLASC 99 7 3 2 Crossbar Switch AXBS Master Configuration MCM_PLAMC 99 7 3 3 Platform Control...

Page 6: ...itialization application information 129 Chapter 10 Peripheral Bridge AIPS Lite 10 1 Chip specific information for this module 131 10 1 1 Instantiation Information 131 10 2 Introduction 132 10 2 1 Fea...

Page 7: ...es 181 12 2 Introduction 181 12 2 1 Overview 181 12 2 2 Features 182 12 2 3 Modes of operation 182 12 3 External signal description 183 12 4 Memory map register definition 183 12 4 1 Channel Configura...

Page 8: ...3 3 11 Clear Enable Request Register DMA_CERQ 214 13 3 12 Set Enable Request Register DMA_SERQ 215 13 3 13 Clear DONE Status Bit Register DMA_CDNE 216 13 3 14 Set START Bit Register DMA_SSRT 217 13 3...

Page 9: ...DMA_TCDn_CITER_ELINKNO 235 13 3 33 TCD Last Destination Address Adjustment Scatter Gather Address DMA_TCDn_DLASTSGA 236 13 3 34 TCD Control and Status DMA_TCDn_CSR 236 13 3 35 TCD Beginning Minor Loo...

Page 10: ...0 14 4 1 Aliased bit band regions 272 14 4 2 Bit Manipulation Engine 273 14 5 Peripheral memory map 273 14 5 1 Peripheral Bridge AIPS Lite Memory Map 274 14 6 Private Peripheral Bus PPB memory map 277...

Page 11: ...ister descriptions 293 16 5 Functional Description 309 16 5 1 Flash Protection 309 16 5 2 Flash Access Protection 311 16 5 3 FlexNVM Description 312 16 5 4 Interrupts 316 16 5 5 Flash Operation in Low...

Page 12: ...Clocking Information 364 17 6 7 LPTMR prescaler glitch filter clocking options 365 17 6 8 RTC Clocking Information 365 17 6 9 TSI Clocking Information 366 17 6 10 Module Clocking Information for LPUA...

Page 13: ...Fast IRC Configuration Register SCG_FIRCCFG 393 18 3 16 Fast IRC Trim Configuration Register SCG_FIRCTCFG 394 18 3 17 Fast IRC Status Register SCG_FIRCSTAT 395 18 3 18 Low Power FLL Control Status Reg...

Page 14: ...2 Introduction 411 20 2 1 Features 411 20 3 Functional description 412 20 4 Memory map and register definition 413 20 4 1 PCC Register Descriptions 413 Chapter 21 Reset and Boot 21 1 Introduction 459...

Page 15: ...sh Driver Entry Point 500 22 4 2 Flash driver API Tree 501 22 4 3 Quick demo using Kinetis Flash Driver API 502 22 4 4 Flash driver data structures 503 22 4 5 Flash driver API 504 22 5 Peripherals Sup...

Page 16: ...apter 24 Power Management 24 1 Introduction 547 24 2 Power Modes Description 548 24 2 1 Run mode 549 24 2 2 Wait mode 550 24 2 3 Stop mode 551 24 2 4 Power domains 553 24 2 5 Entering and exiting powe...

Page 17: ...hapter 26 Power Management Controller PMC 26 1 Chip specific Information for this Module 581 26 2 Introduction 581 26 3 Features 581 26 4 Modes of Operation 581 26 4 1 Full Performance Mode FPM 581 26...

Page 18: ...Watchdog Monitor EWM 28 1 Introduction 593 28 1 1 Features 593 28 1 2 Modes of Operation 594 28 1 3 Block Diagram 595 28 2 EWM Signal Descriptions 596 28 3 Memory Map Register Definition 596 28 3 1 C...

Page 19: ...Features 606 29 2 2 Block diagram 607 29 3 Memory map and register definition 607 29 3 1 Watchdog Control and Status Register WDOG_CS 608 29 3 2 Watchdog Counter Register WDOG_CNT 611 29 3 3 Watchdog...

Page 20: ...ynomial register CRC_GPOLY 626 30 2 3 CRC Control register CRC_CTRL 626 30 3 Functional description 627 30 3 1 CRC initialization reinitialization 627 30 3 2 CRC calculations 628 30 3 3 Transpose feat...

Page 21: ...3 1 MTB_RAM Memory Map 646 32 3 2 MTB_DWT Memory Map 658 32 3 3 System ROM Memory Map 668 32 4 Usage Guide 672 32 4 1 ARM reference 672 Chapter 33 Signal Multiplexing and Pin Assignment 33 1 Introduc...

Page 22: ...5 Detailed signal description 695 34 6 Memory map and register definition 695 34 6 1 Pin Control Register n PORTx_PCRn 702 34 6 2 Global Pin Control Low Register PORTx_GPCLR 705 34 6 3 Global Pin Cont...

Page 23: ...9 35 3 5 Port Data Input Register GPIOx_PDIR 719 35 3 6 Port Data Direction Register GPIOx_PDDR 720 35 4 FGPIO memory map and register definition 720 35 4 1 Port Data Output Register FGPIOx_PDOR 722 3...

Page 24: ...uration Register 2 ADCx_CFG2 746 36 4 4 ADC Data Result Registers ADCx_Rn 747 36 4 5 Compare Value Registers ADCx_CVn 748 36 4 6 Status and Control Register 2 ADCx_SC2 749 36 4 7 Status and Control Re...

Page 25: ...4 26 ADC Plus Side General Calibration Offset Value Register 0 ADCx_CLP0_OFS 761 36 4 27 ADC Plus Side General Calibration Offset Value Register X ADCx_CLPX_OFS 762 36 4 28 ADC Plus Side General Calib...

Page 26: ...785 37 3 3 ANMUX key features 785 37 4 CMP DAC and ANMUX diagram 786 37 5 CMP block diagram 787 37 6 CMP pin descriptions 788 37 6 1 External pins 788 37 7 CMP functional modes 789 37 7 1 Disabled mo...

Page 27: ...ge Guide 816 37 14 1 Zero Crossing Detection 816 37 14 2 Window Mode 817 37 14 3 Round Robin Mode 817 Chapter 38 Programmable Delay Block PDB 38 1 Chip specific Information for this Module 821 38 1 1...

Page 28: ...Y 837 38 5 Functional description 837 38 5 1 PDB pre trigger and trigger outputs 837 38 5 2 PDB trigger input source selection 839 38 5 3 Pulse Out s 840 38 5 4 Updating the delay registers 841 38 5 5...

Page 29: ...S 870 39 4 10 Features Mode Selection FTMx_MODE 872 39 4 11 Synchronization FTMx_SYNC 874 39 4 12 Initial State For Channels Output FTMx_OUTINIT 876 39 4 13 Output Mask FTMx_OUTMASK 878 39 4 14 Functi...

Page 30: ...3 Counter 911 39 5 4 Channel Modes 917 39 5 5 Input Capture mode 919 39 5 6 Output Compare mode 922 39 5 7 Edge Aligned PWM EPWM mode 924 39 5 8 Center Aligned PWM CPWM mode 925 39 5 9 Combine mode 92...

Page 31: ...terrupts 1003 39 7 1 Timer Overflow Interrupt 1003 39 7 2 Reload Point Interrupt 1003 39 7 3 Channel n Interrupt 1003 39 7 4 Fault Interrupt 1003 39 8 Initialization Procedure 1004 39 9 Usage Guide 10...

Page 32: ...6 Set Timer Enable Register LPITx_SETTEN 1018 40 4 7 Clear Timer Enable Register LPITx_CLRTEN 1019 40 4 8 Timer Value Register LPITx_TVALn 1020 40 4 9 Current Timer Value LPITx_CVALn 1021 40 4 10 Tim...

Page 33: ...PWT_PPH 1039 41 4 4 Pulse Width Timer Positive Pulse Width Register Loq PWT_PPL 1039 41 4 5 Pulse Width Timer Negative Pulse Width Register High PWT_NPH 1040 41 4 6 Pulse Width Timer Negative Pulse W...

Page 34: ...r definition 1056 42 4 1 Low Power Timer Control Status Register LPTMRx_CSR 1057 42 4 2 Low Power Timer Prescale Register LPTMRx_PSR 1058 42 4 3 Low Power Timer Compare Register LPTMRx_CMR 1060 42 4 4...

Page 35: ...Alarm Register RTC_TAR 1072 43 3 4 RTC Time Compensation Register RTC_TCR 1072 43 3 5 RTC Control Register RTC_CR 1074 43 3 6 RTC Status Register RTC_SR 1076 43 3 7 RTC Lock Register RTC_LR 1077 43 3...

Page 36: ...f operation 1092 44 2 5 Signal Descriptions 1093 44 3 Memory Map and Registers 1094 44 3 1 Version ID Register LPSPIx_VERID 1095 44 3 2 Parameter Register LPSPIx_PARAM 1096 44 3 3 Control Register LPS...

Page 37: ...pecific information for this module 1123 45 1 1 Instantiation Information 1123 45 1 2 Module Clocking Information for LPUART LPSPI LPI2C FlexIO and LPIT 1123 45 1 3 Inter connectivity Information 1124...

Page 38: ...a Register LPI2Cx_MRDR 1147 45 3 18 Slave Control Register LPI2Cx_SCR 1148 45 3 19 Slave Status Register LPI2Cx_SSR 1149 45 3 20 Slave Interrupt Enable Register LPI2Cx_SIER 1152 45 3 21 Slave DMA Enab...

Page 39: ...6 3 Register definition 1181 46 3 1 LPUART Register Descriptions 1181 46 4 Functional description 1205 46 4 1 Baud rate generation 1205 46 4 2 Transmitter functional description 1206 46 4 3 Receiver f...

Page 40: ...rrupt Enable Register FLEXIO_TIMIEN 1234 47 3 11 Shifter Status DMA Enable FLEXIO_SHIFTSDEN 1235 47 3 12 Shifter Control N Register FLEXIO_SHIFTCTLn 1235 47 3 13 Shifter Configuration N Register FLEXI...

Page 41: ...nnectivity Information 1270 48 2 Introduction 1271 48 2 1 Features 1272 48 2 2 Modes of operation 1272 48 2 3 Block diagram 1272 48 3 External signal description 1273 48 3 1 TSI 24 0 1274 48 4 Registe...

Page 42: ...ing mode 1301 48 5 5 Enable TSI module 1303 48 5 6 Software and hardware trigger 1303 48 5 7 Scan times 1303 48 5 8 Clock setting 1304 48 5 9 Reference voltage 1305 48 5 10 End of scan 1305 48 5 11 Ou...

Page 43: ...ip 2 Chapters in the second set are organized into functional groupings that detail particular areas of functionality Examples of these groupings are clocking timers and communication interfaces Each...

Page 44: ...nces Thetabledoesnot list feature detailsthat theinstancesshare Table 49 1 eSCI instance feature differences Instance DMA support eSCI_A and eSCI_B Yes eSCI_C eSCI_D eSCI_E and eSCI_F No descriptions...

Page 45: ...R SWT_TO SWT_WN and SWT_SK registersareread only TheSWT memory map isshown in thefollowing table SWT memory map Address offset hex Register name Width in bits Access Reset value Section page 0 SWT Con...

Page 46: ...xus_3_0 arbitrates with Core0 data for XBAR port 1 Core1 instruction 2 1 Core1 data 3 1 Nexus_3_1 9 Nexus_3_1 arbitrates with Core1 data for XBAR port 3 Table continues on the next page Sample Referen...

Page 47: ...numbers are followed by this suffix only when the possibility of confusion exists In general decimal numbers are shown without a suffix h Hexadecimal number For example the hexadecimal equivalent of t...

Page 48: ...l meanings Term Meaning asserted Refers to the state of a signal as follows An active high signal is asserted when high 1 An active low signal is asserted when low 0 deasserted Refers to the state of...

Page 49: ...s of ARM Cortex M0 MCUs and product family It also presents high level descriptions of the modules available on the device covered by this document 2 2 Block Diagram The following figure shows a top l...

Page 50: ...gh drive Digital filters I O 8 pins LPO TSI 36ch TRGMUX Boot ROM FIRC SIRC LPFLL OSC32 FAC EWM optional upto 58 port E output capable Kinetis KE1xZ Sub Family x2 LPI C 2 FlexTimer 8ch x1 4ch x2 PWT Fl...

Page 51: ...clock FIRC Slow internal reference clock SIRC System oscillator OSC Low Power Oscillator LPO Peripheral Clock Control PCC Security and integrity modules Cyclic Redundancy Check CRC module for error d...

Page 52: ...ory Description High drive I O pins see Pin properties Digital filters see Ports summary table in Port control and interrupt module features Module Functional Categories Kinetis KE1xZ256 Sub Family Re...

Page 53: ...tex M profile processors It is based on the 16 bit Thumb instruction set and includes Thumb 2 technology including all but three 16 bit Thumb opcodes plus seven 32 bit instructions The Cortex M0 instr...

Page 54: ...mented on the Cortex M0 processor of this device A single AHB Lite bus A single cycle IO port PPB bus NVIC interface MTB interface Debug port interface Optional Debug Cortex M0 components Cortex M0 pr...

Page 55: ...WD YES MPU Not present 3 4 SysTick Clock Configuration The System Tick Timer s clock source is always the core clock CORE_CLK on this device This results in the following The CLKSOURCE bit in SysTick...

Page 56: ...SysTick Clock Configuration Kinetis KE1xZ256 Sub Family Reference Manual Rev 3 07 2018 56 NXP Semiconductors...

Page 57: ...kable Interrupt NMI The NVIC registers are located within the processor s internal System Control Space SCS with base address of 0xE000E000 Most of the NVIC registers are accessible only in privileged...

Page 58: ...quest 4 3 Interrupt channel assignments The interrupt source assignments are defined in the following table Vector number the value stored on the stack when an interrupt is serviced IRQ number non cor...

Page 59: ...0x0000_0060 24 8 2 LPI2C0 Single interrupt vector for all sources 0x0000_0064 25 9 2 LPI2C1 0x0000_0068 26 10 2 LPSPI0 Single interrupt vector for all sources 0x0000_006C 27 11 2 LPSPI1 Single interru...

Page 60: ...hannel assignments value number as example only Table 4 3 LPTMR interrupt vector assignment example only Address Vector IRQ1 NVIC non IPR register number2 NVIC IPR register number3 Source module Sourc...

Page 61: ...nge is 20 21 Therefore the following bitfield locations are used to configure the LPTMR interrupts NVIC_ISER1 26 NVIC_ICER1 26 NVIC_ISPR1 26 NVIC_ICPR1 26 NVIC_IABR1 26 NVIC_IPR14 21 20 Chapter 4 Inte...

Page 62: ...Interrupt channel assignments Kinetis KE1xZ256 Sub Family Reference Manual Rev 3 07 2018 62 NXP Semiconductors...

Page 63: ...configuration FlexTimer clock and channel selection and configuration ADC trigger selection Flash configuration System device unique identification UID LPUART pseudo open drain control 5 2 Memory map...

Page 64: ...d Low SIM_UIDML 32 R See section 5 2 10 76 4004_8060 Unique Identification Register Low SIM_UIDL 32 R See section 5 2 11 76 4004_806C Miscellaneous Control register SIM_MISCTRL 32 R W 0000_0000h 5 2 1...

Page 65: ...COCO 1 0 1 PDB0 Channel 0 back to back operation with COCO 0 of ADC0 and COCO 1 of ADC1 PDB0 Channel 1 back to back operation with COCO 0 of ADC1 and COCO 1 of ADC0 12 11 Reserved This field is reserv...

Page 66: ...must also be configured for the FTM external clock function through the appropriate Pin Control Register in the Port Control module 00 FTM2 external clock driven by TCLK0 pin 01 FTM2 external clock dr...

Page 67: ...appropriate pin control register in the port control module when it comes from external fault pin TRGMUX_FTM0 SELx is corresponding to FTM0 Fault x input Bit value 0 FTM0_FLTx pin Bit value 1 TRGMUX_F...

Page 68: ...igger source select Selects trigger source for ADC1 NOTE Each PDB supports two ADC channels and each channel is with 2 pre triggers 0 PDB output 1 TRGMUX output 7 6 Reserved This field is reserved Thi...

Page 69: ...T1 field descriptions Field Description 31 24 Reserved This field is reserved This read only field is reserved and always has the value 0 23 16 FTM0_OUTSEL FTM0 channel modulation select with FTM1_CH1...

Page 70: ...sert the TRIG1 input to FTM2 Software must clear this bit to allow other trigger sources to assert 1 FTM1SYNCBIT FTM1 Sync Bit Software control for FTM1 hardware trigger synchronization 0 No effect 1...

Page 71: ...d features 27 24 SUBFAMID Kinetis E series Sub Family ID Specifies the Kinetis E series sub family of the device 23 20 SERIESID Kinetis Series ID Specifies the Kinetis series of the device 0010 Kineti...

Page 72: ...on user programming in user IFR via the PGMPART flash command Address 4004_8000h base 4Ch offset 4004_804Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R NVMSIZE PFSIZE 0 EEERAMSIZE W Reset x...

Page 73: ...d This field is reserved This read only field is reserved and always has the value 0 1 FLASHDOZE Flash Doze When set Flash memory is disabled for the duration of Doze mode An attempt by the DMA or oth...

Page 74: ...ys has the value 0 30 24 MAXADDR0 Max address block 0 This field concatenated with 13 trailing zeros indicates the first invalid address of program flash block 0 For example if MAXADDR0 0x10 the first...

Page 75: ...Unique identification for the device 5 2 9 Unique Identification Register Mid High SIM_UIDMH Address 4004_8000h base 58h offset 4004_8058h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13...

Page 76: ...fication Unique identification for the device 5 2 11 Unique Identification Register Low SIM_UIDL Address 4004_8000h base 60h offset 4004_8060h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14...

Page 77: ...Open drain is enabled on UART1 16 UART0ODE UART0 Open Drain Enable 0 Open drain is disabled on UART0 1 Open drain is enabled on UART0 15 8 Reserved This field is reserved This read only field is reser...

Page 78: ...ion 3 1 Reserved This field is reserved This read only field is reserved and always has the value 0 0 SW_TRG Software Trigger bit to TRGMUX Memory map and register definition Kinetis KE1xZ256 Sub Fami...

Page 79: ...rtant to maximize system performance and minimize device power dissipation Accordingly the MMDVSQ module is included in select microcontrollers to serve as a memory mapped co processor located in a sp...

Page 80: ...register write overhead Supports two methods to determine when result is valid including software polling Configurable divide by zero response Pipelined design processes 2 bits per cycle with early t...

Page 81: ...lt Master Lite m0 s1 s2 s0 m3 m2 NVIC Fetch Rn MUL MTB Port MTB MCM MMDVSQ Figure 6 1 Generic Cortex M0 Core Platform Block Diagram Next a block diagram of the internal structure of the MMDVSQ module...

Page 82: ...dresses to its programming model All functionality associated with the MMDVSQ module resides in the core platform s clock domain this includes its connections with the crossbar slave port To minimize...

Page 83: ...MMDVSQ can perform either a divide or square root calculation The basic integer operations supported by the MMDVSQ are For divide MMDVSQ_RES quotient MMDVSQ_DEND MMDVSQ_DSOR MMDVSQ_RES remainder MMDV...

Page 84: ...lculation causes the access to be stalled using wait states until the calculation completes Address F000_4000h base 0h offset F000_4000h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12...

Page 85: ...29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R DIVISOR W Reset x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Notes x Undefined at reset MMDVSQ_DSO...

Page 86: ...g wait states until the calculation completes Address F000_4000h base 8h offset F000_4008h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R BUSY DIV SQRT 0 W Reset 0 x x 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 87: ...the value 0 5 DFS Disable Fast Start The MMDVSQ supports 2 mechanisms for initiating a divide operation The default mechanism is a fast start where a write to the DSOR register begins the divide Alter...

Page 88: ...11 perform an unsigned divide returning the remainder 0 Return the quotient in the RES for the divide calculation 1 Return the remainder in the RES for the divide calculation 1 USGN Unsigned calculati...

Page 89: ...reset MMDVSQ_RES field descriptions Field Description RESULT Result This is the output result for a divide or square root calculation 6 4 5 Radicand Register MMDVSQ_RCND The write only radicand regis...

Page 90: ...inder is the same as the sign of the dividend The quotient is negated if the signs of the dividend and divisor are different The hardware implementation processes two bits per machine cycle and includ...

Page 91: ...e radicand per cycle the result register finishes with the integer portion of the square root calculation The module includes early termination logic so that the execution time is data dependent based...

Page 92: ...the programmer The Q notation is written as Qm n where Q designates that the number is in the Q format notation the Texas Instruments representation for signed fixed point numbers the Q being reminis...

Page 93: ...uQ16 00 1 0 43 581 0x0003_243F uQ16 16 0x0000_01C5 uQ08 08 1 76953125 0 165 0x0324_3F6A uQ08 24 0x0000_1C5B uQ04 12 1 772216769 0 013 0x3243_F6A8 uQ04 28 0x0000_716F uQ02 14 1 7723999023 0 003 0xC90F_...

Page 94: ...000__0000_0000_0000_00 01 1x 2 0000_0000_0000_0000__0000_0000_0000_0000 1 Table 6 5 Square Root Execution Times RCND 31 0 Execution Time with CSR BUSY 1 cycles 01 1x xx_xxxx_xxxx_xxxx__xxxx_xxxx_xxxx_...

Page 95: ...e a stalled bus cycle cannot be interrupted so if system interrupt latency is a concern the processor should execute a simple wait loop for example polling CSR BUSY before reading the RES register Thi...

Page 96: ...example the following sequence can be used for the context reload 1 Write 0x0000_0020 to the CSR to disable the fast start mechanism 2 Reload DEND DSOR CSR and RES registers from the saved state Since...

Page 97: ...e The MCM module s location is highlighted AXBS CM0 Core Platform FAU FMC LD ST Dbg Cortex M0 Core AHB Bus AGU RAM Array 32 Dec SHFT ALU DMA_4ch NVM Array PRAM 32 GPIO PBRIDGE BME 32 IO Port Slave Per...

Page 98: ...re describe the registers using byte addresses The registers can be written only when in supervisor mode MCM memory map Absolute address hex Register name Width in bits Access Reset value Section page...

Page 99: ...BS input port n is absent 1 A bus slave connection to AXBS input port n is present 7 3 2 Crossbar Switch AXBS Master Configuration MCM_PLAMC PLAMC is a 16 bit read only register identifying the presen...

Page 100: ...states for the speculation buffer DFCS EFDS Description 0 0 Speculation buffer is on for instruction and off for data 0 1 Speculation buffer is on for instruction and on for data 1 X Speculation buffe...

Page 101: ...l mechanism allows software to execute code from the same block on which flash operations are being performed However software must ensure the sector the flash operations are being performed on is not...

Page 102: ...g 11 DFCDA Disable Flash Controller Data Caching Disables flash controller data caching 0 Enable flash controller data caching 1 Disable flash controller data caching 10 CFCC Clear Flash Controller Ca...

Page 103: ...y field is reserved and always has the value 0 2 CPOWOI Compute Operation Wake up on Interrupt 0 No effect 1 When set the CPOREQ is cleared on any interrupt or exception vector fetch 1 CPOACK Compute...

Page 104: ...ield descriptions continued Field Description 0 Request is cleared 1 Request Compute Operation Memory map register descriptions Kinetis KE1xZ256 Sub Family Reference Manual Rev 3 07 2018 104 NXP Semic...

Page 105: ...c load and store instructions of the Arm Cortex M instruction set architecture v6M v7M with the concept of decorated storage provided by the BME the resulting implementation provides a robust and effi...

Page 106: ...ore NVIC Fetch Rn MUL MTB Port Figure 8 1 Cortex M0 core platform block diagram As shown in the block diagram the BME module interfaces to a switch AHB slave port as its primary input and sources an A...

Page 107: ...eld inserts logical AND OR and XOR operations Support for byte halfword and word sized decorated operations Supports minimum signal toggling on AHB output bus to reduce power dissipation 8 2 3 Modes o...

Page 108: ...lds in peripheral registers and is consistent with I O hardware addressing in the Embedded C standard For most BME commands a single core read or write bus cycle is converted into an atomic read modif...

Page 109: ...ranslated into a read operation on the output bus using the actual memory address with the decoration removed and then captured in a register 2 Cycle x 1 2nd AHB address phase Write access with the re...

Page 110: ...n and mem_addr 19 0 specifies the address offset into the space based at 0x4000_0000 for peripherals The indicates an address bit don t care The decorated AND write operation is defined in the followi...

Page 111: ...The core performs the required write data lane replication on byte and halfword transfers ioorb 0 0 0 1 mem_addr ioorh 0 0 0 1 mem_addr ioorw 0 0 0 1 mem_addr 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16...

Page 112: ...ration and can be byte 8 bit halfword 16 bit or word 32 bit The core performs the required write data lane replication on byte and halfword transfers ioxorb 0 0 1 mem_addr ioxorh 0 0 1 mem_addr ioxorw...

Page 113: ...h is 16 bits The core performs the required write data lane replication on byte and halfword transfers The BFI operation can be used to insert a single bit into a peripheral For this case the w field...

Page 114: ...ister 7 0 xy_z then destination is abxy_zfgh if b 4 and the decorated store strb Rt register 7 0 xyz_ then destination is axyz_efgh if b 5 and the decorated store strb Rt register 7 0 xyz _ then desti...

Page 115: ...he second AHB data phase as the original read data is returned to the processor core For an unsigned bit field extract the decorated load transaction is stalled for one cycle in the BME as the data fi...

Page 116: ...us is translated into a read operation on the output bus with the actual memory address with the decoration removed and then captured in a register 2 Cycle x 1 second AHB address phase Write access wi...

Page 117: ...xt rdata Figure 8 8 Decorated load unsigned bit field insert timing diagram The decorated unsigned bit field extract follows the same execution template shown in the above figure a 2 cycle read operat...

Page 118: ...operand returned to the core The data size is specified by the read operation and can be byte 8 bit halfword 16 bit or word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9...

Page 119: ...filled in the operand returned to the core The data size is specified by the read operation and can be byte 8 bit halfword 16 bit or word 32 bit iolaslb 0 0 1 mem_addr iolaslh 0 0 1 mem_addr iolaslw 0...

Page 120: ...justified and zero filled in the operand returned to the core Recall this is the only decorated operation that does not perform a memory write that is UBFX only performs a read The data size is specif...

Page 121: ...Decode decoration Capture address attributes Idle AHB address phase next BME AHB_dp previous Perform memory read Form bit mask Form rdata mask and capture destination data in register Logically right...

Page 122: ...ences to peripherals and GPIO based at either 0x4000_F000 or 0x400F_F000 0x5000_0000 0x5FFF_FFFF Decorated BFI UBFX references to peripherals and GPIO only based at 0x4000_F000 8 5 Application informa...

Page 123: ...r2 r3 addr r ADDR wdata r WDATA r2 r3 define IOXORW ADDR WDATA __asm ldr r3 3 26 orr r3 addr mov r2 wdata str r2 r3 addr r ADDR wdata r WDATA r2 r3 define IOXORH ADDR WDATA __asm ldr r3 3 26 orr r3 a...

Page 124: ...Application information Kinetis KE1xZ256 Sub Family Reference Manual Rev 3 07 2018 124 NXP Semiconductors...

Page 125: ...ighted AXBS CM0 Core Platform FAU FMC LD ST Dbg Cortex M0 Core AHB Bus AGU RAM Array 32 Dec SHFT ALU DMA_4ch NVM Array PRAM 32 GPIO PBRIDGE BME 32 IO Port Slave Peripherals Alt Master Lite m0 s1 s2 s0...

Page 126: ...ation can be read from MCM registers 9 2 Introduction The information found here provides information on the layout configuration and programming of the crossbar switch The crossbar switch connects bu...

Page 127: ...t The latency in servicing the request depends on each master s priority level and the responding slave s access time Because the crossbar switch appears to be just another slave to the master device...

Page 128: ...numbered master having the highest priority for example in a system with 5 masters master 1 has lower priority than master 3 If two masters request access to the same slave port the master with the hi...

Page 129: ...ng master is to the ID of the last master After granted access to a slave port a master may perform as many transfers as desired to that port until another master makes a request to the same slave por...

Page 130: ...Initialization application information Kinetis KE1xZ256 Sub Family Reference Manual Rev 3 07 2018 130 NXP Semiconductors...

Page 131: ...ormation This device contains one peripheral bridge A generic block diagram of the processor core and platform for this class of microcontrollers is shown in the following figure The AIPS PBRIDGE modu...

Page 132: ...dge AIPS Lite Memory Map for the memory slot assignment 10 2 Introduction The peripheral bridge converts the crossbar switch interface to an interface that can access most of the slave peripherals on...

Page 133: ...on this device do es not contain any user programmable registers 10 4 Functional description The peripheral bridge functions as a bus protocol translator between the crossbar switch and the slave peri...

Page 134: ...s than or equal to the designated peripheral slot size If an access is attempted that is larger than the targeted port an error response is generated Functional description Kinetis KE1xZ256 Sub Family...

Page 135: ...TRGMUX0 supports up to 32 input sources and its output will be the target modules With the TRGMUX each peripheral which accepts external triggers will usually have one specific 32 bit trigger control...

Page 136: ...nal output etc which needs more than 4 trigger inputs multiple control registers are created to support that The trigger input and peripheral trigger control are assigned as the following figure indic...

Page 137: ...ete trigger for data result A ADCx_COCOB ADCx conversion complete trigger for data result B PDBx_Pulse0 PDBx pulse0 trigger PDBx_Pulse1 PDBx pulse1 trigger RTC_second RTC second trigger RTC_alarm RTC...

Page 138: ...G TRGMUX_FTM2 out49 FTM2_FAULT0 out50 FTM2_FAULT1 out51 out52 Reserved out53 out54 out55 TRGMUX_PDB0 out56 out57 X out58 X out59 X Reserved out60 out61 X out62 X out63 X PDB0_EXTRG TRGMUX0 OR ADC1_ADH...

Page 139: ...PI2C0 TRGMUX_LPI2C1 TRGMUX_LPSPI0 TRGMUX_LPSPI1 TRGMUX_LPTMR0 TRGMUX_TSI TRGMUX_PWT OUT out64 out65 X out66 X out67 X out68 FlexIO_TRG_TIM0 out69 FlexIO_TRG_TIM1 out70 FlexIO_TRG_TIM2 out71 FlexIO_TRG...

Page 140: ...allows software to configure the trigger inputs for various peripherals Each peripheral has its own unique TRGMUX register that is used to select the trigger source for peripheral See each peripheral...

Page 141: ...TOP is selected 001100 0x0c LPSPI0 Frame is selected 001101 0x0d LPSPI0 RX data is selected 001110 0x0e LPUART1 RX Data is selected 001111 0x0f LPUART1 TX Data is selected 010000 0x10 LPUART1 RX Idle...

Page 142: ...110011 0x33 Unused 110100 0x34 Unused 110101 0x35 Unused 110110 0x36 Unused 110111 0x37 Unused 111000 0x38 Unused 111001 0x39 Unused 111010 0x3a Unused 111011 0x3b Unused 111100 0x3c Unused 111101 0x...

Page 143: ...next system Reset 30 This read only bit field is reserved and always has the value 0 29 24 SEL3 Trigger MUX Input 3 Source Select This read write bit field is used to configure the MUX select for peri...

Page 144: ...0 Refer to the Select Bit Fields table in the Features section for bit field information 11 4 1 3 TRGMUX_CTRL1 TRGMUX_CTRL1 11 4 1 3 1 Address Register Offset TRGMUX_CTRL1 40063004h TRGMUX Register 11...

Page 145: ...re the MUX select for peripheral trigger input 1 Refer to the Select Bit Fields table in the Features section for bit field information 7 6 This read only bit field is reserved and always has the valu...

Page 146: ...010110 0x16 FLEXIO Trigger 2 is selected 010111 0x17 FLEXIO Trigger 3 is selected 011000 0x18 TRGMUX1 Output 0 selected 011001 0x19 TRGMUX1 Output 1 is selected 011010 0x1a TRGMUX1 Output 2 is select...

Page 147: ...TRGMUX_EXTOUT1 32 RW 00000000h 4006200Ch TRGMUX ADC0 TRGMUX_ADC0 32 RW 00000000h 40062010h TRGMUX ADC1 TRGMUX_ADC1 32 RW 00000000h 4006201Ch TRGMUX CMP0 TRGMUX_CMP0 32 RW 00000000h 40062020h TRGMUX CM...

Page 148: ...WT 32 RW 00000000h 11 4 2 2 TRGMUX DMAMUX0 TRGMUX_DMAMUX0 11 4 2 2 1 Address Register Offset TRGMUX_DMAMUX0 40062000h 11 4 2 2 2 Function TRGMUX Register 11 4 2 2 3 Diagram Bits 31 30 29 28 27 26 25 2...

Page 149: ...Fields table in the Features section for bit field information 15 14 This read only bit field is reserved and always has the value 0 13 8 SEL1 Trigger MUX Input 1 Source Select This read write bit fie...

Page 150: ...d is reserved and always has the value 0 21 16 SEL2 Trigger MUX Input 2 Source Select This read write bit field is used to configure the MUX select for peripheral trigger input 2 Refer to the Select B...

Page 151: ...eld is reserved and always has the value 0 29 24 SEL3 Trigger MUX Input 3 Source Select This read write bit field is used to configure the MUX select for peripheral trigger input 3 Refer to the Select...

Page 152: ...ures section for bit field information 11 4 2 5 TRGMUX ADC0 TRGMUX_ADC0 11 4 2 5 1 Address Register Offset TRGMUX_ADC0 4006200Ch TRGMUX Register 11 4 2 5 2 Diagram Bits 31 30 29 28 27 26 25 24 23 22 2...

Page 153: ...it field is used to configure the MUX select for peripheral trigger input 1 Refer to the Select Bit Fields table in the Features section for bit field information 7 6 This read only bit field is reser...

Page 154: ...field is reserved and always has the value 0 21 16 This read only bit field is reserved and always has the value 0 15 14 This read only bit field is reserved and always has the value 0 13 8 SEL1 Trigg...

Page 155: ...written or not 0 Register can be written 1 Register cannot be written until the next system Reset 30 This read only bit field is reserved and always has the value 0 29 24 This read only bit field is r...

Page 156: ...9 28 27 26 25 24 23 22 21 20 19 18 17 16 R LK Rese rved Reserved Reserved Reserved W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R Reserved Reserved Reserved SEL0...

Page 157: ...lect This read write bit field is used to configure the MUX select for peripheral trigger input 0 Refer to the Select Bit Fields table in the Features section for bit field information 11 4 2 9 TRGMUX...

Page 158: ...to the Select Bit Fields table in the Features section for bit field information 15 14 This read only bit field is reserved and always has the value 0 13 8 SEL1 Trigger MUX Input 1 Source Select This...

Page 159: ...ce Select This read write bit field is used to configure the MUX select for peripheral trigger input 2 Refer to the Select Bit Fields table in the Features section for bit field information 15 14 This...

Page 160: ...egister cannot be written until the next system Reset 30 This read only bit field is reserved and always has the value 0 29 24 This read only bit field is reserved and always has the value 0 23 22 Thi...

Page 161: ...ection for bit field information 11 4 2 12 TRGMUX PDB0 TRGMUX_PDB0 11 4 2 12 1 Address Register Offset TRGMUX_PDB0 40062038h TRGMUX Register 11 4 2 12 2 Diagram Bits 31 30 29 28 27 26 25 24 23 22 21 2...

Page 162: ...s the value 0 13 8 This read only bit field is reserved and always has the value 0 7 6 This read only bit field is reserved and always has the value 0 5 0 SEL0 Trigger MUX Input 0 Source Select This r...

Page 163: ...is reserved and always has the value 0 21 16 SEL2 Trigger MUX Input 2 Source Select This read write bit field is used to configure the MUX select for peripheral trigger input 2 Refer to the Select Bi...

Page 164: ...eld is reserved and always has the value 0 29 24 SEL3 Trigger MUX Input 3 Source Select This read write bit field is used to configure the MUX select for peripheral trigger input 3 Refer to the Select...

Page 165: ...on for bit field information 11 4 2 15 TRGMUX LPUART0 TRGMUX_LPUART0 11 4 2 15 1 Address Register Offset TRGMUX_LPUART0 4006204Ch TRGMUX Register 11 4 2 15 2 Diagram Bits 31 30 29 28 27 26 25 24 23 22...

Page 166: ...the value 0 13 8 This read only bit field is reserved and always has the value 0 7 6 This read only bit field is reserved and always has the value 0 5 0 SEL0 Trigger MUX Input 0 Source Select This re...

Page 167: ...eserved and always has the value 0 23 22 This read only bit field is reserved and always has the value 0 21 16 This read only bit field is reserved and always has the value 0 15 14 This read only bit...

Page 168: ...ster cannot be written until the next system Reset 30 This read only bit field is reserved and always has the value 0 29 24 This read only bit field is reserved and always has the value 0 23 22 This r...

Page 169: ...served Reserved W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R Reserved Reserved Reserved SEL0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11 4 2 18 3 Fields Field Fu...

Page 170: ...nfigure the MUX select for peripheral trigger input 0 Refer to the Select Bit Fields table in the Features section for bit field information 11 4 2 19 TRGMUX LPSPI0 TRGMUX_LPSPI0 11 4 2 19 1 Address R...

Page 171: ...15 14 This read only bit field is reserved and always has the value 0 13 8 This read only bit field is reserved and always has the value 0 7 6 This read only bit field is reserved and always has the...

Page 172: ...reserved and always has the value 0 23 22 This read only bit field is reserved and always has the value 0 21 16 This read only bit field is reserved and always has the value 0 15 14 This read only bit...

Page 173: ...ter cannot be written until the next system Reset 30 This read only bit field is reserved and always has the value 0 29 24 This read only bit field is reserved and always has the value 0 23 22 This re...

Page 174: ...ved Reserved W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R Reserved Reserved Reserved SEL0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11 4 2 22 3 Fields Field Funct...

Page 175: ...configure the MUX select for peripheral trigger input 0 Refer to the Select Bit Fields table in the Features section for bit field information 11 4 2 23 TRGMUX PWT TRGMUX_PWT 11 4 2 23 1 Address Regi...

Page 176: ...is reserved and always has the value 0 5 0 SEL0 Trigger MUX Input 0 Source Select This read write bit field is used to configure the MUX select for peripheral trigger input 0 Refer to the Select Bit...

Page 177: ...nput of PDB PDB then be used to trigger other modules like ADC For details please refer to ADC Trigger Concept Use Case section 11 5 2 CMP Window Sample Input PDB and LPIT could be used to generate pu...

Page 178: ...Usage Guide Kinetis KE1xZ256 Sub Family Reference Manual Rev 3 07 2018 178 NXP Semiconductors...

Page 179: ...chronous DMA operation as indicated by the last column in the following DMA source assignment table Asynchronous DMA requests can be used to activate a DMA channel in WAIT or STOP mode Table 12 1 DMA...

Page 180: ...26 FTM0 Channel 6 27 FTM0 Channel 7 28 FTM1 Channel 0 29 FTM1 Channel 1 30 FTM2 Channel 0 31 FTM2 Channel 1 32 LPI2C1 LPI2C1 Receive Yes for LPI2C1 33 LPI2C1 LPI2C1 Transmit Yes for LPI2C1 34 Reserve...

Page 181: ...reserved sources disables that DMA channel 12 1 2 DMA trigger sources The DMAMUX on this device also supports a periodic trigger mode The trigger sources are from TRGMUX output showed in following tab...

Page 182: ...gure 12 1 DMAMUX block diagram 12 2 2 Features The DMAMUX module provides these features Up to 59 peripheral slots and up to four always on slots can be routed to 8 channels 8 independently selectable...

Page 183: ...s empty or a receive buffer becomes full periodically Configuration of the period is done in the registers of the periodic interrupt timer LPIT This mode is available only for channels 0 3 12 3 Extern...

Page 184: ...hannel must be disabled via CHCFGn ENBL Address 4002_1000h base 0h offset 1d i where i 0d to 7d Bit 7 6 5 4 3 2 1 0 Read ENBL TRIG SOURCE Write Reset 0 0 0 0 0 0 0 0 DMAMUX_CHCFGn field descriptions F...

Page 185: ...bility Channels that implement only the normal routing functionality 12 5 1 DMA channels with periodic triggering capability Besides the normal routing functionality the first 4 channels of the DMAMUX...

Page 186: ...een seen This is illustrated in the following figure DMA request Peripheral request Trigger Figure 12 3 DMAMUX channel triggering normal operation After the DMA request has been serviced the periphera...

Page 187: ...to periodically read data from external devices and transfer the results into memory without processor intervention Using the GPIO ports to drive or sample waveforms By configuring the DMA to transfe...

Page 188: ...software should initiate the start of a DMA transfer an always enabled DMA source can be used to provide maximum flexibility When activating a DMA channel via software subsequent executions of the min...

Page 189: ...before use 12 6 2 Enabling and configuring sources To enable a source with periodic triggering 1 Determine with which DMA channel the source will be associated Note that only the first 4 DMA channels...

Page 190: ...nnel 3 Write 0x85 to CHCFG1 The following code example illustrates steps 1 and 3 above In File registers h define DMAMUX_BASE_ADDR 0x40021000 Example only Following example assumes char is 8 bits vola...

Page 191: ...2 and 3 above In File registers h define DMAMUX_BASE_ADDR 0x40021000 Example only Following example assumes char is 8 bits volatile unsigned char CHCFG0 volatile unsigned char DMAMUX_BASE_ADDR 0x0000...

Page 192: ...In File main c include registers h CHCFG8 0x00 CHCFG8 0x87 Initialization application information Kinetis KE1xZ256 Sub Family Reference Manual Rev 3 07 2018 192 NXP Semiconductors...

Page 193: ...sor The hardware microarchitecture includes A DMA engine that performs Source address and destination address calculations Data movement operations Local memory containing transfer control descriptors...

Page 194: ...hannels provide the same functionality This structure allows data transfers associated with one channel to be preempted after the completion of a read write sequence if a higher priority channel activ...

Page 195: ...al the eDMA engine performs a series of source read destination write operations until the number of bytes specified in the minor loop byte count has moved For descriptors where the sizes are not equa...

Page 196: ...nnel arbitration Channel completion reported via programmable interrupt requests One interrupt per channel which can be asserted at completion of major iteration count Programmable error terminations...

Page 197: ...attempts to complete its current transfer After the transfer completes the device enters Wait mode 13 3 Memory map register definition The eDMA s programming model is partitioned into two regions The...

Page 198: ...value of zero Writes to reserved bits in a register are ignored Reading or writing a reserved memory location generates a bus error DMA memory map Absolute address hex Register name Width in bits Acc...

Page 199: ...MA_DCHPRI1 8 R W See section 13 3 21 226 4000_8103 Channel n Priority Register DMA_DCHPRI0 8 R W See section 13 3 21 226 4000_8104 Channel n Priority Register DMA_DCHPRI7 8 R W See section 13 3 21 226...

Page 200: ...Loop Mapping Enabled and Offset Disabled DMA_TCD1_NBYTES_MLOFFNO 32 R W Undefined 13 3 26 229 4000_9028 TCD Signed Minor Loop Offset Minor Loop Mapping and Offset Enabled DMA_TCD1_NBYTES_MLOFFYES 32 R...

Page 201: ...E TCD Beginning Minor Loop Link Major Loop Count Channel Linking Disabled DMA_TCD2_BITER_ELINKNO 16 R W Undefined 13 3 36 240 4000_9060 TCD Source Address DMA_TCD3_SADDR 32 R W Undefined 13 3 22 227 4...

Page 202: ...s Offset DMA_TCD4_DOFF 16 R W Undefined 13 3 30 233 4000_9096 TCD Current Minor Loop Link Major Loop Count Channel Linking Enabled DMA_TCD4_CITER_ELINKYES 16 R W Undefined 13 3 31 233 4000_9096 DMA_TC...

Page 203: ...r Loop Mapping Disabled DMA_TCD6_NBYTES_MLNO 32 R W Undefined 13 3 25 229 4000_90C8 TCD Signed Minor Loop Offset Minor Loop Mapping Enabled and Offset Disabled DMA_TCD6_NBYTES_MLOFFNO 32 R W Undefined...

Page 204: ...6 R W Undefined 13 3 32 235 4000_90F8 TCD Last Destination Address Adjustment Scatter Gather Address DMA_TCD7_DLASTSGA 32 R W Undefined 13 3 33 236 4000_90FC TCD Control and Status DMA_TCD7_CSR 16 R W...

Page 205: ...plied to the source address TCDn_SADDR upon minor loop completion a destination enable bit DMLOE to specify the minor loop offset should be applied to the destination address TCDn_DADDR upon minor loo...

Page 206: ...er in the same fashion as the CX bit Stop the executing channel and force the minor loop to finish The cancel takes effect after the last write of the current read write sequence The ECX bit clears it...

Page 207: ...error causes the HALT bit to set Subsequently all service requests are ignored until the HALT bit is cleared 3 Reserved This field is reserved Reserved 2 ERCA Enable Round Robin Channel Arbitration 0...

Page 208: ...PE Channel Priority Error 0 No channel priority error 1 The last recorded error was a configuration error in the channel priorities Channel priorities are not unique 13 11 Reserved This field is reser...

Page 209: ...ter gather operation after major loop completion if TCDn_CSR ESG is enabled TCDn_DLASTSGA is not on a 32 byte boundary 1 SBE Source Bus Error 0 No source bus error 1 The last recorded error was a bus...

Page 210: ...st 5 0 The DMA request signal for the corresponding channel is disabled 1 The DMA request signal for the corresponding channel is enabled 4 ERQ4 Enable DMA Request 4 0 The DMA request signal for the c...

Page 211: ...nd always has the value 0 7 EEI7 Enable Error Interrupt 7 0 The error signal for corresponding channel does not generate an error interrupt 1 The assertion of the error signal for corresponding channe...

Page 212: ...ear a given bit in the EEI to disable the error interrupt for a given channel The data value on a register write causes the corresponding bit in the EEI to be cleared Setting the CAEE bit provides a g...

Page 213: ...is ignored This allows you to write multiple byte registers as a 32 bit word Reads of this register return all zeroes Address 4000_8000h base 19h offset 4000_8019h Bit 7 6 5 4 3 2 1 0 Read 0 0 0 Writ...

Page 214: ...f this register return all zeroes NOTE Disable a channel s hardware service request at the source before clearing the channel s ERQ bit Address 4000_8000h base 1Ah offset 4000_801Ah Bit 7 6 5 4 3 2 1...

Page 215: ...rs as a 32 bit word Reads of this register return all zeroes Address 4000_8000h base 1Bh offset 4000_801Bh Bit 7 6 5 4 3 2 1 0 Read 0 0 0 Write NOP SAER 0 SERQ Reset 0 0 0 0 0 0 0 0 DMA_SERQ field des...

Page 216: ...a 32 bit word Reads of this register return all zeroes Address 4000_8000h base 1Ch offset 4000_801Ch Bit 7 6 5 4 3 2 1 0 Read 0 0 0 Write NOP CADN 0 CDNE Reset 0 0 0 0 0 0 0 0 DMA_CDNE field descript...

Page 217: ...this register return all zeroes Address 4000_8000h base 1Dh offset 4000_801Dh Bit 7 6 5 4 3 2 1 0 Read 0 0 0 Write NOP SAST 0 SSRT Reset 0 0 0 0 0 0 0 0 DMA_SSRT field descriptions Field Description...

Page 218: ...e multiple byte registers as a 32 bit word Reads of this register return all zeroes Address 4000_8000h base 1Eh offset 4000_801Eh Bit 7 6 5 4 3 2 1 0 Read 0 0 0 Write NOP CAEI 0 CERR Reset 0 0 0 0 0 0...

Page 219: ...ite multiple byte registers as a 32 bit word Reads of this register return all zeroes Address 4000_8000h base 1Fh offset 4000_801Fh Bit 7 6 5 4 3 2 1 0 Read 0 0 0 Write NOP CAIR 0 CINT Reset 0 0 0 0 0...

Page 220: ...e corresponding channel s current interrupt status The CINT register is provided so the interrupt request for a single channel can easily be cleared without the need to perform a read modify write seq...

Page 221: ...by setting the appropriate bit in this register The outputs of this register are enabled by the contents of the EEI and then routed to the interrupt controller During the execution of the interrupt se...

Page 222: ...rred 1 An error in this channel has occurred 5 ERR5 Error In Channel 5 0 An error in this channel has not occurred 1 An error in this channel has occurred 4 ERR4 Error In Channel 4 0 An error in this...

Page 223: ...ion 31 8 Reserved This field is reserved This read only field is reserved and always has the value 0 7 HRS7 Hardware Request Status Channel 7 The HRS bit for its respective channel remains asserted fo...

Page 224: ...hardware service request for channel 3 is present 2 HRS2 Hardware Request Status Channel 2 The HRS bit for its respective channel remains asserted for the period when a Hardware Request is Present on...

Page 225: ...quest for channel 6 1 Enable asynchronous DMA request for channel 6 5 EDREQ_5 Enable asynchronous DMA request in stop mode for channel 5 0 Disable asynchronous DMA request for channel 5 1 Enable async...

Page 226: ...7 Address 4000_8000h base 100h offset 1d i where i 0d to 7d Bit 7 6 5 4 3 2 1 0 Read ECP DPA 0 CHPRI Write Reset 0 0 0 0 0 Notes CHPRI field See bit field description DMA_DCHPRIn field descriptions F...

Page 227: ...ng to the source data 13 3 23 TCD Signed Source Address Offset DMA_TCDn_SOFF Address 4000_8000h base 1004h offset 32d i where i 0d to 7d Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read SOFF Write Reset...

Page 228: ...d the SMOD field should be set to the appropriate value for the queue freezing the desired number of upper address bits The value programmed into this field specifies the number of lower address bits...

Page 229: ...the channel As a channel activates the appropriate TCD contents load into the eDMA engine and the appropriate reads and writes perform until the minor byte transfer count has transferred This is an i...

Page 230: ...plied to the SADDR 30 DMLOE Destination Minor Loop Offset enable Selects whether the minor loop offset is applied to the destination address upon minor loop completion 0 The minor loop offset is not a...

Page 231: ...s 4000_8000h base 1008h offset 32d i where i 0d to 7d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R SMLOE DMLOE MLOFF W Reset x x x x x x x x x x x x x x x x Bit 15 14 13 12 11 10 9 8 7 6 5 4...

Page 232: ...t is completed additional processing is performed 13 3 28 TCD Last Source Address Adjustment DMA_TCDn_SLAST Address 4000_8000h base 100Ch offset 32d i where i 0d to 7d Bit 31 30 29 28 27 26 25 24 23 2...

Page 233: ...Sign extended offset applied to the current destination address to form the next state value as each destination write is completed 13 3 31 TCD Current Minor Loop Link Major Loop Count Channel Linking...

Page 234: ...enabled ELINK 1 then after the minor loop is exhausted the eDMA engine initiates a channel service request to the channel defined by this field by setting that channel s TCDn_CSR START bit CITER Curre...

Page 235: ...in favor of the MAJORELINK channel linking NOTE This bit must be equal to the BITER ELINK bit otherwise a configuration error is reported 0 The channel to channel linking is disabled 1 The channel to...

Page 236: ...ddress to the initial value or adjust the address to reference the next data structure This field uses two s complement notation for the final destination address adjustment Otherwise This address poi...

Page 237: ...o write the MAJORELINK or ESG bits 6 ACTIVE Channel Active This flag signals the channel is currently in execution It is set when channel service begins and is cleared by the eDMA as the minor loop co...

Page 238: ...e is CITER BITER 1 This halfway point interrupt request is provided to support double buffered also known as ping pong schemes or other types of data movement where the processor needs an early indica...

Page 239: ...al to the corresponding CITER field otherwise a configuration error is reported As the major iteration count is exhausted the contents of this field are reloaded into the CITER field 0 The channel to...

Page 240: ...channel initiates a channel service request via an internal mechanism that sets the TCDn_CSR START bit of the specified channel If channel linking is disabled the BITER value extends to 15 bits in pla...

Page 241: ...low of a data transfer can be partitioned into three segments As shown in the following diagram the first segment involves the channel activation 1 eDMA Engine Data Path eDMA 0 Program Model 64 Contro...

Page 242: ...ess the local memory for TCDn Next the TCD memory is accessed and the required descriptor read from the local memory and loaded into the eDMA engine address path channel x or y registers The TCD memor...

Page 243: ...unt is exhausted additional operations are performed These include the final address adjustments and reloading of the BITER field into the CITER Assertion of an optional interrupt request also occurs...

Page 244: ...er size respectively In fixed arbitration mode a configuration error is caused by any two channel priorities being equal All channel priority levels must be unique when fixed arbitration mode is enabl...

Page 245: ...the data captured during the bus error If a bus error occurs on the last write prior to switching to the next read sequence the read sequence executes before the channel terminates due to the destina...

Page 246: ...nel preemption is enabled on a per channel basis by setting the DCHPRIn ECP bit Channel preemption allows the executing channel s data transfers to temporarily suspend in favor of starting a higher pr...

Page 247: ...nternal SRAM can be accessed with zero wait states when viewed from the system bus data phase All internal peripheral bus reads require two wait states and internal peripheral bus writes three wait st...

Page 248: ...eral bus write it is 5 cycles Table 13 5 Hardware service request process Cycle Description With internal peripheral bus read and internal SRAM write With SRAM read and internal peripheral bus write 1...

Page 249: ...its TCD from the local memory This is equivalent to Cycle 4 for the first channel s service request Assuming zero wait states on the system bus DMA requests can be processed every 9 cycles Assuming a...

Page 250: ...the system bus data phase System operates at 150 MHz For an SRAM to internal peripheral bus transfer PEAKreq 150 MHz 4 1 1 1 3 3 cycles 11 5 Mreq sec For an internal peripheral bus to SRAM transfer P...

Page 251: ...Write to the CR if a configuration other than the default is desired 2 Write the channel priority levels to the DCHPRIn registers if a configuration other than the default is desired 3 Enable error in...

Page 252: ...dicating major loop completion cleared by software when using a software initiated DMA service D_REQ Control bit to disable DMA request at end of major loop completion when using a hardware initiated...

Page 253: ...programming errors are reported on a per channel basis with the exception of channel priority error ES CPE For all error types other than channel priority error the channel number causing the error i...

Page 254: ...pt generates if properly enabled For example the following TCD entry is configured to transfer 16 bytes of data The eDMA is programmed for one iteration of the major loop transferring 16 bytes per ite...

Page 255: ...rom 0x1006 read byte from 0x1007 d Write 32 bits to location 0x2004 second iteration of the minor loop e Read byte from location 0x1008 read byte from location 0x1009 read byte from 0x100A read byte f...

Page 256: ...ternal register file 5 The source to destination transfers are executed as follows a Read byte from location 0x1000 read byte from location 0x1001 read byte from 0x1002 read byte from 0x1003 b Write 3...

Page 257: ...location 0x1015 read byte from 0x1016 read byte from 0x1017 d Write 32 bits to location 0x2014 second iteration of the minor loop e Read byte from location 0x1018 read byte from location 0x1019 read b...

Page 258: ...a 24 byte 16 byte size queue Table 13 9 Modulo example Transfer Number Address 1 0x12345670 2 0x12345674 3 0x12345678 4 0x1234567C 5 0x12345670 6 0x12345674 13 5 5 Monitoring transfer descriptor statu...

Page 259: ...d is idle 3b 0 0 1 Channel has completed the major loop and is idle For both activation types the major loop complete status is explicitly indicated via the TCDn_CSR DONE bit The TCDn_CSR START bit is...

Page 260: ...is a mechanism where one channel sets the TCDn_CSR START bit of another channel or itself therefore initiating a service request for that channel When properly enabled the EDMA engine automatically pe...

Page 261: ...Control Field Name Description Link at end of Minor Loop CITER E_LINK Enable channel to channel linking on minor loop completion current iteration CITER LINKCH Link channel number when linking at end...

Page 262: ...e_link 1 the dynamic link attempt was successful If TCD major e_link 0 the attempted dynamic link did not succeed the channel was already retiring For this request the TCD local memory controller for...

Page 263: ...er a channel begins execution 13 5 7 3 1 Method 1 channel not using major loop channel linking For a channel not using major loop channel linking the coherency model described here may be used for a d...

Page 264: ...tempt fail setting the d_req bit will prevent a future hardware activation of this channel This stops the channel from executing with a destination address daddr that was calculated using a scatter ga...

Page 265: ...s no service request to the DMA channel being suspended Then disable the hardware service request by clearing the ERQ bit on the appropriate DMA channel 13 5 8 2 Resume a DMA channel To resume a DMA c...

Page 266: ...lication notes on this DMA module are as follows Using DMA for pulse counting on Kinetis Using DMA and GPIO to emulate timer functionality on Kinetis Family devices Using DMA to Emulate ADC Flexible S...

Page 267: ...rals which are located in one 4G bytes 32 bit address contiguous memory space This chapter describes the memory and peripheral locations within that memory space The following figure shows the system...

Page 268: ...x1C00_4000 0x1FF0_0000 0x2010_0000 0xE000_0000 0x1C00_0000 0xFFFF_FFFF 0xF000_0000 0xE010_0000 0x1800_0000 0x0000_0000 0x1000_0000 0x1400_0000 0x4010_0000 0x4000_0000 0x4400_0000 0x6000_0000 0x2200_00...

Page 269: ...FlexNVM consisting of 2 KB sectors 1 block 2 KB of FlexRAM The amounts of flash memory and the address range for the devices is shown in following table Device Program flash KB FlexNVM KB FlexRAM KB...

Page 270: ...eated as separate memory ranges for burst accesses The amount of SRAM for the devices covered in this document is shown in the following table Device SRAM_L size KB SRAM_U size KB Total SRAM KB Addres...

Page 271: ...FF AIPS Peripherals Cortex M0 core DMA 0x4008_0000 0x400F_EFFF Reserved 0x400F_F000 0x400F_FFFF General purpose input output GPIO Cortex M0 core DMA 0x4010_0000 0x41FF_FFFF Reserved 0x4200_0000 0x43FF...

Page 272: ...way with 32 bit operation and also could be accessed with bit operation through aliased bit band region 14 4 1 Aliased bit band regions The device supports aliased SRAM_U bit band region with Cortex...

Page 273: ...port in the Cortex M instruction set architecture with the concept of decorated storage provided by the BME the resulting implementation provides a robust and efficient read modify write capability to...

Page 274: ...e 14 2 Peripheral bridge slot assignments System 32 bit base address Slot number Module 0x4000_0000 0 0x4000_1000 1 MSCM 0x4000_2000 2 0x4000_3000 3 0x4000_4000 4 0x4000_5000 5 0x4000_6000 6 0x4000_70...

Page 275: ...SPI LPSPI 1 0x4002_E000 46 0x4002_F000 47 0x4003_0000 48 0x4003_1000 49 0x4003_2000 50 CRC 0x4003_3000 51 0x4003_4000 52 0x4003_5000 53 0x4003_6000 54 Programmable delay block PDB 0 0x4003_7000 55 Low...

Page 276: ...watchdog WDOG 0x4005_3000 83 0x4005_4000 84 0x4005_5000 85 0x4005_6000 86 Pulse Width Timer PWT 0x4005_7000 87 0x4005_8000 88 0x4005_9000 89 0x4005_A000 90 Flexible IO FlexIO 0x4005_B000 91 0x4005_C00...

Page 277: ...4007_E000 126 System Mode controller SMC 0x4007_F000 127 Reset Control Module RCM 0x400F_F000 GPIO controller 14 6 Private Peripheral Bus PPB memory map The PPB is part of the defined ARM bus architec...

Page 278: ...000_ED8F System Control Block 0xE000_ED90 0xE000_EDEF Reserved 0xE000_EDF0 0xE000_EEFF Debug 0xE000_EF00 0xE000_EFFF Reserved 0xE000_F000 0xE00F_EFFF Reserved 0xE00F_F000 0xE00F_FFFF Core ROM Space CR...

Page 279: ...bit flash memory location and a 4 way 4 set program flash memory cache can store previously accessed program flash memory data for quick access times 15 1 2 Modes of operation The FAU operates only w...

Page 280: ...ed Data speculation is disabled Data caching is enabled Though the default configuration provides flash acceleration advanced users may desire to customize the FAU buffer configurations to maximize th...

Page 281: ...spond to flash accesses with no added wait states in many cases Any time the requested information is available in the cache or prefetch buffer the FAU responds with no added wait states 15 2 2 FAU Co...

Page 282: ...he is still available for acceleration of flash accesses Cache replacement control The FAU cache replacement algorithm can be modified from the default setting where instruction and data are handled t...

Page 283: ...ported from ROM for customer use Please visit http www nxp com kboot for more information 16 2 Introduction The FTFE module includes the following accessible memory regions Program flash memory for ve...

Page 284: ...o degradation of the erased 1 states and or programmed 0 states Therefore it is recommended that each flash block or sector be re erased immediately prior to factory programming to ensure that the ful...

Page 285: ...ditional RAM operations When configured for EEPROM Protection scheme prevents accidental program or erase of data written for EEPROM Built in hardware emulation scheme to automate EEPROM record mainte...

Page 286: ...ccess Memory controller Program flash 0 FlexRAM EEPROM backup Data flash 0 Figure 16 1 FTFE block diagram 16 2 3 Glossary Command write sequence A series of MCU writes to the Flash FCCOB register grou...

Page 287: ...or The EEPROM backup data sector contains one EEPROM header and up to 255 EEPROM backup data records which are used by the EEPROM filing system Endurance The number of times that a flash memory locati...

Page 288: ...t portion of the program flash memory consecutive addresses that can be erased Retention The length of time that data can be kept in the NVM without experiencing errors upon readout Since erased 1 sta...

Page 289: ...am flash memory Flash Configuration Field Offset Address Size Bytes Field Description 0x0_0400 0x0_0407 8 Backdoor Comparison Key Refer to Verify Backdoor Access Key command and Unsecuring the MCU Usi...

Page 290: ...x09 0x3AC 0x3AF 4 Program Once XACCL 2 Field index 0x09 0x3B0 0x3B3 4 Program Once SACCH 1 Field index 0x0A 0x3B4 0x3B7 4 Program Once SACCL 1 Field index 0x0A 0x3B8 0x3BB 4 Program Once SACCH 2 Field...

Page 291: ...of the available EEPROM subsystems To program the EEERST EEESIZE value see the Program Partition command described in Program Partition command Table 16 1 EEPROM Data Set Size Data flash IFR 0x03FD 7...

Page 292: ...VM partition code The FlexNVM partition code byte in the data flash 0 IFR supplies a code which specifies how to split the FlexNVM block between data flash memory and EEPROM backup memory supporting E...

Page 293: ...11 32 0 1100 Reserved Reserved 1101 Reserved Reserved 1110 Reserved Reserved 1111 32 0 16 4 4 Register descriptions The FTFE module contains a set of memory mapped control and status registers NOTE Wh...

Page 294: ...ect Registers FTFE_FCCOB5 8 R W 00h 16 4 4 5 301 4002_000B Flash Common Command Object Registers FTFE_FCCOB4 8 R W 00h 16 4 4 5 301 4002_000C Flash Common Command Object Registers FTFE_FCCOBB 8 R W 00...

Page 295: ...CH2 8 R Undefined 16 4 4 10 306 4002_0022 Supervisor only Access Registers FTFE_SACCH1 8 R Undefined 16 4 4 10 306 4002_0023 Supervisor only Access Registers FTFE_SACCH0 8 R Undefined 16 4 4 10 306 40...

Page 296: ...The RDCOLERR error bit indicates that the MCU attempted a read from an FTFE resource that was being manipulated by an FTFE command CCIF 0 Any simultaneous access is detected as a collision error by t...

Page 297: ...d ERSSUSP have write restrictions PFLSH RAMRDY and EEERDY are read only status bits The reset values for the PFLSH RAMRDY and EEERDY bits are determined during the reset sequence Address 4002_0000h ba...

Page 298: ...1 Reserved 1 RAMRDY RAM Ready This flag indicates the current status of the FlexRAM The state of the RAMRDY flag is normally controlled by the Set FlexRAM Function command During the reset sequence t...

Page 299: ...nables and disables mass erase capability of the FTFE module When the SEC field is set to unsecure the MEEN setting does not matter 00 Mass erase is enabled 01 Mass erase is enabled 10 Mass erase is d...

Page 300: ...stomize its operations by examining the state of these read only bits which are loaded from NVM at reset The function of the bits is defined in the device s Chip Configuration details All bits in the...

Page 301: ...or queueing is provided the next command can be loaded only after the current command completes Some commands return information to the FCCOB registers Any values returned to FCCOB are available for...

Page 302: ...by any FTFE command Unprotected regions can be changed by program and erase operations The four FPROT registers allow up to 32 protectable regions of equal memory size Program flash protection registe...

Page 303: ...sitions are ignored Restriction The user must never write to any FPROT register while a command is running CCIF 0 Trying to alter data in any protected area in the program flash memory results in a pr...

Page 304: ...ster is loaded with the contents of the EEPROM protection byte in the Flash Configuration Field located in program flash The flash basis for the reset values is signified by X in the register diagram...

Page 305: ...ration Field located in program flash memory The flash basis for the reset values is signified by X in the register diagram To change the data flash protection that will be loaded during the reset seq...

Page 306: ...4 3 2 1 0 Read XA Write Reset x x x x x x x x Notes x Undefined at reset FTFE_XACCn field descriptions Field Description XA Execute only access control 0 Associated segment is accessible in execute mo...

Page 307: ...3B0 0x03B8 SACCL0 0x03B7 0x03BF SACCL1 0x03B6 0x03BE SACCL2 0x03B5 0x03BD SACCL3 0x03B4 0x03BC Use the Program Once command to program the supervisor only access control fields that are loaded during...

Page 308: ...ZE Segment Size The segment size is a fixed value based on the available program flash size divided by NUMSG Program Flash Size Segment Size Segment Size Encoding 256 KBytes 4 KBytes 0x4 512 KBytes 8...

Page 309: ...Program flash memory is divided into 64 segments 256 Kbytes 512 Kbytes 1 Mbyte 2 Mbytes 16 5 Functional Description The following sections describe functional details of the FTFE module 16 5 1 Flash...

Page 310: ...data flash memory as shown in the following figure Data flash size 8 DPROT0 0x0_0000 DPROT1 DPROT2 DPROT3 DPROT5 DPROT7 DPROT6 FlexNVM Last data flash address Data flash size 8 Data flash size 8 Data...

Page 311: ...vice 16 5 2 Flash Access Protection Individual segments within the program flash memory can be designated for restricted access Specific flash commands Program Check Program Phrase Erase Flash Block E...

Page 312: ...ents of the program flash memory as shown in the following figure Program flash size 64 SACCL3 SA0 0x0_0000 Program flash Last program flash address Program flash size 64 SACCL3 SA1 Program flash size...

Page 313: ...EPROM User Perspective The EEPROM system is shown in the following figure File system handler User access effective EEPROM FlexRAM EEPROM backup with 2KByte erase sectors Figure 16 7 Top Level EEPROM...

Page 314: ...o quickly store large amounts of data or store data that is static The EEPROM partition in FlexRAM is useful for storing smaller amounts of data that will be changed often DEPART Data flash EEPROM bac...

Page 315: ...OM When the FlexNVM partition code is not set to full data flash the EEPROM data set size can be set to any of several non zero values The bytes not assigned to data flash via the FlexNVM partition co...

Page 316: ...le can generate interrupt requests to the MCU upon the occurrence of various FTFE events These interrupt events and their associated status and control bits are shown in the following table Table 16 5...

Page 317: ...ery low power modes VLPR VLPW VLPS the FTFE module does not accept flash commands 16 5 6 Flash memory reads and ignored writes The FTFE module requires only the flash address to execute a flash memory...

Page 318: ...m and Erase All flash functions except read require the user to setup and launch an FTFE command through a series of peripheral bus writes The user cannot initiate any further FTFE commands until noti...

Page 319: ...ents a new command from launching can t clear CCIF if the previous command resulted in an access error FSTAT ACCERR 1 or a protection violation FSTAT FPVIOL 1 In error scenarios two writes to FSTAT ar...

Page 320: ...the FSTAT MGSTAT0 bit A command may have access errors protection errors and run time errors but the run time errors are not seen until all access and protection errors have been corrected 3 Command e...

Page 321: ...Read FSTAT register no yes Bit Polling for Command Completion Check Figure 16 10 Generic Flash Command Write Sequence Flowchart 16 5 9 2 Flash commands The following table summarizes the function of a...

Page 322: ...ram flash block or data flash block An erase of any flash block is only possible when unprotected FlexNVM block must not be partitioned for EEPROM 0x09 Erase Flash Sector Erase all bytes in a program...

Page 323: ...ed security keys to those stored in the program flash 0x49 Erase All Blocks Unsecure Erase all program flash blocks data flash blocks FlexRAM EEPROM backup data records and data flash IFR Then verify...

Page 324: ...ly on the program flash data flash and FlexRAM memories Some operations cannot be executed simultaneously because certain hardware resources are shared by the memories The priority has been placed on...

Page 325: ...ad These non standard read levels are applied only during the command execution All simple uncommanded flash array reads to the MCU always use the standard un margined read reference level Only the no...

Page 326: ...e used during verify of the initial factory programming 16 5 11 Flash command descriptions This section describes all flash commands that can be launched by a command write sequence The FTFE sets the...

Page 327: ...r 1s according to Table 16 8 and then reads all locations within the selected program flash or data flash block When the data flash is targeted DEPART must be set for no EEPROM else the Read 1s Block...

Page 328: ...e to be verified 2 Flash address 15 8 of the first phrase to be verified 3 Flash address 7 0 1 of the first phrase to be verified 4 Number of phrases to be verified 15 8 5 Number of phrases to be veri...

Page 329: ...Margin Choice 8 Byte 0 expected data 9 Byte 1 expected data A Byte 2 expected data B Byte 3 expected data 1 Must be longword aligned Flash address 1 0 00 Upon clearing CCIF to launch the Program Check...

Page 330: ...gned FSTAT ACCERR An invalid margin choice is supplied FSTAT ACCERR Flash address is located in an XA controlled segment and the Erase All Blocks Erase All Blocks Unsecure or the Read 1s All Blocks co...

Page 331: ...the selected resource at the provided relative address and stored in the FCCOB register The CCIF flag will set after the Read Resource operation has completed The Read Resource command exits with an a...

Page 332: ...hrase command the FTFE programs the data bytes into the flash using the supplied address The protection status is always checked The targeted flash locations must be currently unprotected see the desc...

Page 333: ...ed 1 Must be 64 bit aligned Flash address 2 0 000 Upon clearing CCIF to launch the Erase Flash Block command the FTFE erases the main array of the selected flash block and verifies that it is erased W...

Page 334: ...ligned Flash address 2 0 000 After clearing CCIF to launch the Erase Flash Sector command the FTFE erases the selected program flash or data flash sector and then verifies that it is erased The Erase...

Page 335: ...Erase Flash Sector Operation If the ERSSUSP bit is still set when CCIF is cleared to launch the next command the previous Erase Flash Sector operation resumes The FTFE acknowledges the request to resu...

Page 336: ...y the FTFE Note Aborting the erase leaves the bitcells in an indeterminate partially erased state Data in this sector is not reliable until a new erase command fully completes The following figure sho...

Page 337: ...ute Yes DONE No ERSSUSP 1 SaveEraseAlgo Set CCIF No Yes Start New ResumeErase No Abort User Cmd Interrupt Suspend Set SUSP ACK 1 ERSSCR Suspended Command Initiation Yes No Yes Yes ERSSCR Completed ERS...

Page 338: ...owed Re programming of existing 0s to 0 is not allowed as this overstresses the device Table 16 25 Program Section Command FCCOB Requirements FCCOB Number FCCOB Contents 7 0 0 0x0B PGMSEC 1 Flash addr...

Page 339: ...rogram Section command is as follows 1 If required execute the Set FlexRAM Function command to make the FlexRAM available as traditional RAM and initialize the FlexRAM to all ones 2 Launch the Erase F...

Page 340: ...rity byte in the flash configuration field see Flash configuration field description remains unaffected by the Read 1s All Blocks command If the read fails i e all flash memory resources are not in th...

Page 341: ...record is read from the program flash IFR and stored in the FCCOB register The CCIF flag is set after the Read Once operation completes Valid record index values for the Read Once command range from...

Page 342: ...rectly The CCIF flag is set after the Program Once operation has completed The reserved program flash IFR location accessed by the Program Once command cannot be erased and any attempt to program one...

Page 343: ...the Erase All Blocks operation completes Access control determined by the contents of the FXACC registers will not block execution of the Erase All Blocks command While most Flash memory will be erase...

Page 344: ...e erase all request is reflected in the FCNFG ERSAREQ bit The FCNFG ERSAREQ bit is cleared once the operation completes and the normal FSTAT error reporting except FPVIOL is available as described in...

Page 345: ...ect backdoor key is supplied FSTAT ACCERR Backdoor key access has not been enabled see the description of the FSEC register FSTAT ACCERR This command is launched and the backdoor key has mismatched si...

Page 346: ...Table 16 39 Erase All Blocks Unsecure Command Error Handling Error Condition Error Bit Command not available in current mode security FSTAT ACCERR Any errors have been encountered during erase or prog...

Page 347: ...An invalid margin choice is specified FSTAT ACCERR Read 1s fails FSTAT MGSTAT0 16 5 11 16 Erase All Execute only Segments Command The Erase All Execute only Segments operation erases all program flash...

Page 348: ...n encountered during the verify operation FSTAT MGSTAT0 16 5 11 17 Program Partition command The Program Partition command prepares the FlexNVM block for use as data flash EEPROM backup or a combinati...

Page 349: ...RT FCCOB5 3 0 1 Data flash Size Kbytes EEPROM backup Size Kbytes 0000 32 0 0011 0 32 1000 0 32 1001 8 24 1011 32 0 1 FCCOB5 7 4 0000 After clearing CCIF to launch the Program Partition command the FTF...

Page 350: ...ode allocates FlexRAM for EEPROM FSTAT ACCERR FlexNVM Partition Code allocates space for EEPROM backup but EEPROM Data Set Size Code allocates no FlexRAM for EEPROM FSTAT ACCERR FCCOB4 7 6 00 FSTAT AC...

Page 351: ...g during factory programming the FlexRAM can be used as the Section Program Buffer for the Program Section command see Program Section command When making the FlexRAM available for EEPROM the FTFE cle...

Page 352: ...ming the security byte of the flash configuration field This assumes that you are starting from a mode where the necessary program flash erase and program commands are available and that the region of...

Page 353: ...n the FSEC register only It does not alter the security byte or the keys stored in the Flash Configuration Field Flash configuration field description After the next reset of the MCU the security stat...

Page 354: ...cess Key command when a comparison fails After the backdoor keys have been correctly matched the MCU is unsecured by changing the FSEC SEC bits A successful execution of the Verify Backdoor Access Key...

Page 355: ...is not guaranteed Commands and operations do not automatically resume after exiting reset 16 7 Usage Guide Related application notes on this FTFE module are as follows Production Flash Programming Bes...

Page 356: ...Usage Guide Kinetis KE1xZ256 Sub Family Reference Manual Rev 3 07 2018 356 NXP Semiconductors...

Page 357: ...System Oscillator SOSC and LPFLL It controls which clock source is used to derive the system clocks The SCG also divides the selected clock source into a variety of clock domains including the clocks...

Page 358: ...2kHz 1kHz RTC 128 PORT Control CRC 8 bit DAC ACMPx TSI DMAMUX eDMA PDB TCLK2 TCLK1 TCLK0 FTMx PWT FLL_CLK SIRC_CLK FIRC_CLK SOSC_CLK SIM_CHIPCTL CLKOUTSEL RTC_CR LPOS SIM_CHIPCTL RTC32KCLKSEL SCG_CLKO...

Page 359: ...SCG_SOSCCSR SOSCERCLKEN For FTM its SOSC_CLK is with no dividers but gated by SCG_SOSCCSR SOSCERCLKEN For other peripherals LPUART etc its SOSC_CLK is divided by DIVx and not gated by SCG_SOSCCSR SOS...

Page 360: ...l that has its bus interface clock disabled CGC 0 in PCC module will generate a bus fault While any bus access to a peripheral that has its functional clock disabled PCS 0 in PCC module will not retur...

Page 361: ...MHz LPO_CLK 128kHz LPIT Yes FIRC_CLK SIRC_CLK FLL_CLK SOSC_CLK Max 48 MHz RTC Yes LPO_CLK OSC32_CLK RTC_CLKIN Max BUS_CLK LPO_CLK 1kHz PDB0 Yes SYS_CLK Max SYS_CLK FlexTimer0 FlexTimer2 Yes SYS_CLK S...

Page 362: ...ACMP1 Yes BUS_CLK Max BUS_CLK TSI Yes BUS_CLK Max BUS_CLK 1 The clock sources undergo clock divider DIVx in SCG output to PCC For details see the High Level clocking diagram section in Clocking chapt...

Page 363: ...ion The following figure shows the input clock sources available for this module Peripheral Clocking ADC PCC_ADCx CGC PCC module DIV2 DIV2 DIV2 DIV2 SOSC FLL FIRC SIRC SCG module SCG DIVSLOW FLLDIV2_C...

Page 364: ...ORE FTMx module SYS_CLK FTMx_SC CLKS Peripheral Interface Clock Registers SIM_FTMOPT0 FTMxCLKSEL TCLK0 TCLK1 TCLK2 10 01 11 Counter SOSC_CLK SCG_SOSCCSR SOSCERCLKEN NOTE Due to FTM hardware implementa...

Page 365: ...LK LPTMRx module BUS_CLK LPO_CLK OSC32_CLK x LPTMRx_PSR PCS Peripheral Interface Clock PCC_LPTMRx PCS 00 01 10 11 see PCC chapter for detailed setting Registers NOTE The chosen clock must remain enabl...

Page 366: ...E RTC_CR LPOS Counter SIM_FTMOPT0 FTMnCLKSEL SIM_CHIPCTL RTC32KCLKSEL 17 6 9 TSI Clocking Information This following figure shows the TSI clocks Peripheral Clocking TSI PCC_TSI CGC PCC module SCG modu...

Page 367: ...SCG module SCG DIVSLOW FLLDIV2_CLK SOSCDIV2_CLK SIRCDIV2_CLK FIRCDIV2_CLK LPUARTx module BUS_CLK Peripheral Interface Clock PCC_LPUARTx PCS see PCC chapter for detailed setting Registers Note this exa...

Page 368: ...Module clocks Kinetis KE1xZ256 Sub Family Reference Manual Rev 3 07 2018 368 NXP Semiconductors...

Page 369: ...n auto trim is disabled ERCLK External Reference Clock is either from an external pin or from the SCG internal OSC SOSC and configured with the SCG_SOSCCFG EREFS bit For the supported frequency range...

Page 370: ...n Run Very Low Power Figure 18 1 SCG Valid Mode Transition Diagram 18 1 1 1 2 Clocking configuration on SCG The following figure shows the clocking configuration on SCG for this device Chip specific i...

Page 371: ...Figure 18 2 Clocking configuration on SCG Chapter 18 System Clock Generator SCG Kinetis KE1xZ256 Sub Family Reference Manual Rev 3 07 2018 NXP Semiconductors 371...

Page 372: ...clock sources for the MCU systems clocks 18 2 1 Features Key features of the SCG module are Low Power Frequency Locked Loop LPFLL Programmable multiplier for up to 4 different frequency ranges Intern...

Page 373: ...8 VLPR Clock Control Register SCG_VCCR 32 R W See section 18 3 5 379 4006_4020 SCG CLKOUT Configuration Register SCG_CLKOUTCNFG 32 R W 0300_0000h 18 3 6 381 4006_4100 System OSC Control Status Registe...

Page 374: ...t 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R VERSION W Reset 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCG_VERID field descriptions F...

Page 375: ...y configured system clock source and the system clock dividers for the core DIVCORE and peripheral interface clock DIVSLOW The SCG_CSR reflects the configuration set by one of three clock control regi...

Page 376: ...y 7 0111 Divide by 8 1000 Divide by 9 1001 Divide by 10 1010 Divide by 11 1011 Divide by 12 1100 Divide by 13 1101 Divide by 14 1110 Divide by 15 1111 Divide by 16 15 12 Reserved This field is reserve...

Page 377: ...21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 SCS 0 DIVCORE Reserved 0 0 DIVSLOW W Reset 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Notes DIVCORE field The reset value is c...

Page 378: ...1 Divide by 16 15 12 Reserved This field is reserved Software should write 0 to these bits to maintain compatibility This field is reserved 11 8 Reserved This field is reserved This read only field is...

Page 379: ...0 0 DIVSLOW W Reset 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Notes DIVCORE field The reset value is controlled by user FOPT bits that get uploaded during reset The two option reset val...

Page 380: ...s field is reserved Software should write 0 to these bits to maintain compatibility This field is reserved 11 8 Reserved This field is reserved This read only field is reserved and always has the valu...

Page 381: ...field descriptions Field Description 31 28 Reserved This field is reserved This read only field is reserved and always has the value 0 27 24 CLKOUTSEL SCG Clkout Select Selects the SCG system clock 0...

Page 382: ...d This flag is reset on Chip POR only SCG_SOSCCSR field descriptions Field Description 31 27 Reserved This field is reserved This read only field is reserved and always has the value 0 26 SOSCERR Syst...

Page 383: ...lso disabled in the low power mode When the clock monitor is disabled in a low power mode it remains disabled until the clock valid flag is set following exit from the low power mode 0 System OSC Cloc...

Page 384: ...0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 SOSCDIV2 0 SOSCDIV1 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCG_SOSCDIV field descriptions Field Description 31 19 Reserved This field...

Page 385: ...this register are ignored and there is no transfer error Address 4006_4000h base 108h offset 4006_4108h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 386: ...crystal oscillator power mode of operations 0 Configure crystal oscillator for low gain operation 1 Configure crystal oscillator for high gain operation 2 EREFS External Reference Select Selects the s...

Page 387: ...ions Field Description 31 26 Reserved This field is reserved This read only field is reserved and always has the value 0 25 SIRCSEL Slow IRC Selected 0 Slow IRC is not the system clock source 1 Slow I...

Page 388: ...low IRC is enabled 18 3 11 Slow IRC Divide Register SCG_SIRCDIV To prevent glitches to the output divided clock change SIRDIV when the Slow IRC is disabled Address 4006_4000h base 204h offset 4006_420...

Page 389: ...e 000 Output disabled 001 Divide by 1 010 Divide by 2 011 Divide by 4 100 Divide by 8 101 Divide by 16 110 Divide by 32 111 Divide by 64 18 3 12 Slow IRC Configuration Register SCG_SIRCCFG The SIRCCFG...

Page 390: ...8 MHz 18 3 13 Fast IRC Control Status Register SCG_FIRCCSR Address 4006_4000h base 300h offset 4006_4300h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 FIRCERR FIRCSEL FIRCVLD LK 0 W w1c Re...

Page 391: ...2 10 Reserved This field is reserved This read only field is reserved and always has the value 0 9 FIRCTRUP Fast IRC Trim Update 0 Disable Fast IRC trimming updates 1 Enable Fast IRC trimming updates...

Page 392: ...his field is reserved This bit field is reserved Software should write 0 to this bit field to maintain compatibility 15 11 Reserved This field is reserved This read only field is reserved and always h...

Page 393: ...24 23 22 21 20 19 18 17 16 R 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 RANGE W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCG_FIRCCFG field descriptions Field...

Page 394: ...15 11 Reserved This field is reserved This read only field is reserved and always has the value 0 10 8 TRIMDIV Fast IRC Trim Predivide Divide the System OSC down for Fast IRC trimming 000 Divide by 1...

Page 395: ...ue 0 15 14 Reserved This field is reserved This read only field is reserved and always has the value 0 13 8 TRIMCOAR Trim Coarse TRIMCOAR bits are used to coursely trim the Fast IRC Clock to within ap...

Page 396: ...8 17 16 R 0 LPFLLERR LPFLLSEL LPFLLVLD LK 0 LPFLLCMRE LPFLLCM W w1c Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 LPFLLTRMLOCK LPFLLTRUP LPFLLTREN 0 0 LPFLLEN W R...

Page 397: ...d can be cleared set at any time 0 Control Status Register can be written 1 Control Status Register cannot be written 22 18 Reserved This field is reserved This read only field is reserved and always...

Page 398: ...LTRUP 0 lock conditions cannot be checked 18 3 19 Low Power FLL Divide Register SCG_LPFLLDIV Changes to LPFLLDIV should be done when LPFLL is disabled to prevent glitches to output divided clock Addre...

Page 399: ...00 Divide by 8 101 Divide by 16 110 Divide by 32 111 Divide by 64 18 3 20 Low Power FLL Configuration Register SCG_LPFLLCFG The LPFLLCFG register cannot be changed when the LPFLL is enabled When the L...

Page 400: ...7 6 5 4 3 2 1 0 R 0 TRIMDIV 0 TRIMSRC W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCG_LPFLLTCFG field descriptions Field Description 31 17 Reserved This field is reserved This read only field is reserved...

Page 401: ...erated by LPFLL auto trimming which is enabled when LPFLL is enabled and LPFLLTREN 1 and LPFLLTRUP 1 When LPFLL auto trimming is enabled and LPFLLTRUP is off writes to this register is allowed and val...

Page 402: ...the selected run mode For example if a transition from RUN mode to VLRUN is required first complete any required clock change Initiate the VLRUN request after the clock change has completed The power...

Page 403: ...nges to FIRC range settings will be ignored when FIRC clock is enabled Information regarding FIRC operation during normal and low power stop modes is found in the Stop row of this table Low Power FLL...

Page 404: ...wing conditions become true FIRCCSR FIRCEN 1 FIRCCSR FIRCSTEN 1 SOSCLK is available in following low power stop modes Normal Stop VLPS when all the below conditions are true SOSCCSR SOSCEN 1 SOSCCSR S...

Page 405: ...odes The key features of the RTC oscillator are as follows Supports 32 kHz crystals with very low power Consists of internal feed back resistor Automatic Gain Control AGC to optimize power consumption...

Page 406: ...nment section to find out which signals are actually connected to the external pins Table 19 1 RTC Signal Descriptions Signal Description I O EXTAL32 Oscillator Input I XTAL32 Oscillator Output O 19 2...

Page 407: ...The following section shows the memory map and explains the register OSC32 memory map Absolute address hex Register name Width in bits Access Reset value Section page 4006_0000 RTC Oscillator Control...

Page 408: ...e block 1 RTC 32k oscillator is stable 4 ROSCEREFS RTC 32k Oscillator external reference clcok selection NOTE If RTC_CR OSCE is set this bit will be bypassed OSC32 then works in crystal mode 0 Bypass...

Page 409: ...o reset state associated with the RTC oscillator 19 7 Interrupts The RTC oscillator does not generate any interrupts Chapter 19 RTC Oscillator OSC32 Kinetis KE1xZ256 Sub Family Reference Manual Rev 3...

Page 410: ...Interrupts Kinetis KE1xZ256 Sub Family Reference Manual Rev 3 07 2018 410 NXP Semiconductors...

Page 411: ...IRC clock SCGFIRCLK SFLLDIV2_CLK FLLDIV2 of LPFLL clock SCGFLLCLK 20 2 Introduction The Peripheral Clock Control module PCC provides peripheral clock control and configuration registers In addition to...

Page 412: ...le External Peripheral Specific Clock Source This clock is used by the Peripheral Functional Logic example derive baud rates Clock Divide Control PCD bits in the Peripheral s PCC register Post Divider...

Page 413: ...re blocked and result in a bus error 20 4 1 PCC Register Descriptions 20 4 1 1 PCC Memory Map Absolute address Register Width In bits Access Reset value 40065020h PCC DMA0 PCC_DMA0 32 RW C0000000h 400...

Page 414: ...0h 40065168h PCC FLEXIO PCC_FLEXIO 32 RW 80000000h 40065180h PCC OSC32 PCC_OSC32 32 RW 80000000h 40065184h PCC EWM PCC_EWM 32 RW 80000000h 40065198h PCC LPI2C0 PCC_LPI2C0 32 RW 80000000h 4006519Ch PCC...

Page 415: ...0 Clock disabled 1 Clock enabled 29 INUSE Clock Gate Control This read only bit shows that this peripheral is being used 0 Peripheral is not being used 1 Peripheral is being used Software cannot modi...

Page 416: ...s device 0 Peripheral is not present 1 Peripheral is present 30 CGC Clock Control This read write bit enables the clock for the peripheral 0 Clock disabled 1 Clock enabled 29 INUSE Clock Gate Control...

Page 417: ...ts 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R PR CGC INUS E Reserved Reserved Reserved W Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R Reserved Rese rved Re...

Page 418: ...28 27 This read only bit field is reserved and always has the value 0 26 24 This read only bit field is reserved and always has the value 0 23 4 This read only bit field is reserved and always has th...

Page 419: ...0 Peripheral is not being used 1 Peripheral is being used Software cannot modify the existing clocking configuration 28 27 This read only bit field is reserved and always has the value 0 26 24 PCS Pe...

Page 420: ...eserved W Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R Reserved Rese rved Reserved W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 20 4 1 6 3 Fields Field Function 31 PR...

Page 421: ...ten when the CGC bit is 0 clock disabled Likewise if the INUSE flag is set this field is locked 000 Clock is off 001 System Oscillator Bus Clock 010 Slow IRC Clock 011 Fast IRC Clock 100 Reserved 101...

Page 422: ...used 0 Peripheral is not being used 1 Peripheral is being used Software cannot modify the existing clocking configuration 28 27 This read only bit field is reserved and always has the value 0 26 24 PC...

Page 423: ...d W Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R Reserved Rese rved Reserved W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 20 4 1 8 3 Fields Field Function 31 PR Enable...

Page 424: ...d always has the value 0 3 This read only bit field is reserved and always has the value 0 2 0 This read only bit field is reserved and always has the value 0 20 4 1 9 PCC PDB0 PCC_PDB0 20 4 1 9 1 Add...

Page 425: ...tware cannot modify the existing clocking configuration 28 27 This read only bit field is reserved and always has the value 0 26 24 This read only bit field is reserved and always has the value 0 23 4...

Page 426: ...used 0 Peripheral is not being used 1 Peripheral is being used Software cannot modify the existing clocking configuration 28 27 This read only bit field is reserved and always has the value 0 26 24 P...

Page 427: ...d Reserved W Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R Reserved Rese rved Reserved W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 20 4 1 11 3 Fields Field Function 31...

Page 428: ...has the value 0 3 This read only bit field is reserved and always has the value 0 2 0 This read only bit field is reserved and always has the value 0 20 4 1 12 PCC FLEXTMR1 PCC_FLEXTMR1 20 4 1 12 1 A...

Page 429: ...e cannot modify the existing clocking configuration 28 27 This read only bit field is reserved and always has the value 0 26 24 This read only bit field is reserved and always has the value 0 23 4 Thi...

Page 430: ...heral 0 Clock disabled 1 Clock enabled 29 INUSE Clock Gate Control This read only bit shows that this peripheral is being used 0 Peripheral is not being used 1 Peripheral is being used Software cannot...

Page 431: ...ent on this device 0 Peripheral is not present 1 Peripheral is present 30 CGC Clock Control This read write bit enables the clock for the peripheral 0 Clock disabled 1 Clock enabled 29 INUSE Clock Gat...

Page 432: ...ved and always has the value 0 3 This read only bit field is reserved and always has the value 0 2 0 This read only bit field is reserved and always has the value 0 20 4 1 15 PCC RTC PCC_RTC 20 4 1 15...

Page 433: ...used 0 Peripheral is not being used 1 Peripheral is being used Software cannot modify the existing clocking configuration 28 27 This read only bit field is reserved and always has the value 0 26 24 Th...

Page 434: ...s being used 0 Peripheral is not being used 1 Peripheral is being used Software cannot modify the existing clocking configuration 28 27 This read only bit field is reserved and always has the value 0...

Page 435: ...e peripheral is present on this device 0 Peripheral is not present 1 Peripheral is present 30 CGC Clock Control This read write bit enables the clock for the peripheral 0 Clock disabled 1 Clock enable...

Page 436: ...PORTA 40065124h PCC Register 20 4 1 18 2 Diagram Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R PR CGC INUS E Reserved Reserved Reserved W Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits 15 14 13 1...

Page 437: ...uration 28 27 This read only bit field is reserved and always has the value 0 26 24 This read only bit field is reserved and always has the value 0 23 4 This read only bit field is reserved and always...

Page 438: ...heral 0 Clock disabled 1 Clock enabled 29 INUSE Clock Gate Control This read only bit shows that this peripheral is being used 0 Peripheral is not being used 1 Peripheral is being used Software cannot...

Page 439: ...device 0 Peripheral is not present 1 Peripheral is present 30 CGC Clock Control This read write bit enables the clock for the peripheral 0 Clock disabled 1 Clock enabled 29 INUSE Clock Gate Control Th...

Page 440: ...Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R PR CGC INUS E Reserved Reserved Reserved W Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R Reserved Rese rved...

Page 441: ...This read only bit field is reserved and always has the value 0 26 24 This read only bit field is reserved and always has the value 0 23 4 This read only bit field is reserved and always has the value...

Page 442: ...heral 0 Clock disabled 1 Clock enabled 29 INUSE Clock Gate Control This read only bit shows that this peripheral is being used 0 Peripheral is not being used 1 Peripheral is being used Software cannot...

Page 443: ...ice 0 Peripheral is not present 1 Peripheral is present 30 CGC Clock Control This read write bit enables the clock for the peripheral 0 Clock disabled 1 Clock enabled 29 INUSE Clock Gate Control This...

Page 444: ...ram Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R PR CGC INUS E Reserved PCS Reserved W Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R Reserved Rese rved R...

Page 445: ...arious clock selections This field can only be written when the CGC bit is 0 clock disabled Likewise if the INUSE flag is set this field is locked 000 Clock is off 001 System Oscillator Bus Clock 010...

Page 446: ...heral 0 Clock disabled 1 Clock enabled 29 INUSE Clock Gate Control This read only bit shows that this peripheral is being used 0 Peripheral is not being used 1 Peripheral is being used Software cannot...

Page 447: ...ice 0 Peripheral is not present 1 Peripheral is present 30 CGC Clock Control This read write bit enables the clock for the peripheral 0 Clock disabled 1 Clock enabled 29 INUSE Clock Gate Control This...

Page 448: ...ram Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R PR CGC INUS E Reserved PCS Reserved W Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R Reserved Rese rved R...

Page 449: ...rious clock selections This field can only be written when the CGC bit is 0 clock disabled Likewise if the INUSE flag is set this field is locked 000 Clock is off 001 System Oscillator Bus Clock 010 S...

Page 450: ...used 0 Peripheral is not being used 1 Peripheral is being used Software cannot modify the existing clocking configuration 28 27 This read only bit field is reserved and always has the value 0 26 24 P...

Page 451: ...served W Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R Reserved Rese rved Reserved W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 20 4 1 29 3 Fields Field Function 31 PR...

Page 452: ...tten when the CGC bit is 0 clock disabled Likewise if the INUSE flag is set this field is locked 000 Clock is off 001 System Oscillator Bus Clock 010 Slow IRC Clock 011 Fast IRC Clock 100 Reserved 101...

Page 453: ...d 0 Peripheral is not being used 1 Peripheral is being used Software cannot modify the existing clocking configuration 28 27 This read only bit field is reserved and always has the value 0 26 24 PCS P...

Page 454: ...S Reserved W Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R Reserved Rese rved Reserved W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 20 4 1 31 3 Fields Field Function 31...

Page 455: ...itten when the CGC bit is 0 clock disabled Likewise if the INUSE flag is set this field is locked 000 Clock is off 001 System Oscillator Bus Clock 010 Slow IRC Clock 011 Fast IRC Clock 100 Reserved 10...

Page 456: ...heral 0 Clock disabled 1 Clock enabled 29 INUSE Clock Gate Control This read only bit shows that this peripheral is being used 0 Peripheral is not being used 1 Peripheral is being used Software cannot...

Page 457: ...vice 0 Peripheral is not present 1 Peripheral is present 30 CGC Clock Control This read write bit enables the clock for the peripheral 0 Clock disabled 1 Clock enabled 29 INUSE Clock Gate Control This...

Page 458: ...has the value 0 3 This read only bit field is reserved and always has the value 0 2 0 This read only bit field is reserved and always has the value 0 Memory map and register definition Kinetis KE1xZ2...

Page 459: ...ug reset Debug reset Each of the reset sources has an associated bit in the system reset status RCM_SRS register Besides immediate reset the RCM module also supports optional delays of the system rese...

Page 460: ...Power on reset POR When power is initially applied to the MCU or when the supply voltage drops below the power on reset re arm voltage level VPOR the POR circuit causes a POR reset condition As the su...

Page 461: ...The reset value for each filter assumes the RESET pin is negated For all stop modes where LPO clock is still active the only filtering option is the LPO based digital filter The filtering logic either...

Page 462: ...the software This communication is generally known as servicing or refreshing the watchdog If this periodic refreshing does not occur the watchdog issues a system reset The reset causes the RCM_SRS W...

Page 463: ...ents except for the debug module A software reset causes the RCM_SRS SW bit to set 21 2 2 8 Lockup reset LOCKUP The LOCKUP gives immediate indication of seriously errant kernel software This is the re...

Page 464: ...21 2 3 4 Chip Reset Chip Reset asserts on all reset sources and only negates after flash initialization has completed and the RESET_b pin has also negated It resets the remaining modules the modules n...

Page 465: ...OTCFG0 NMI pin high 01 Boot from Flash 10 Boot from ROM 11 Boot from ROM 6 Reserved Reserved for future expansion 5 4 Reserved Reserved for future expansion 3 RESET_PIN_CFG Enables disables control fo...

Page 466: ...ore and system clock divider DIVCORE is 0x1 divide by 2 1 Normal boot Core and system clock divider DIVCORE is 0x0 divide by 1 This device supports cold booting from either internal flash or Boot ROM...

Page 467: ...inues to be held in reset Once the RESET_b pin is detected high the Core clock is enabled and the system is released from reset 6 When the system exits reset the processor sets up the stack program co...

Page 468: ...m reset IFR include FOPT load ftfx initialization complete release core hold 22 50us VDD POR LVR Clock Reset_b Core start FOPT load Flash reset System reset Figure 21 2 Boot Sequence Boot Kinetis KE1x...

Page 469: ...2 54 42 34 LPUART0_RX PTB0 2 27 22 18 LPSPI 0 LPSPI0_PCS 1 PTB5 3 28 23 19 LPSPI0_SOU T PTB4 3 47 39 31 LPSPI0_SIN PTB3 3 48 40 32 LPSPI0_SCK PTB2 3 72 59 47 LPI2C 0 LPI2C0_SCL PTA3 3 73 60 48 LPI2C0...

Page 470: ...mmunication For the Kinetis device the Kinetis Bootloader can interface with I2C SPI and UART peripherals in slave mode and respond to the commands sent by a master or host communicating on one of tho...

Page 471: ...ROM Command Description When flash security is enabled then this command is Execute Run user application code that never returns control to the bootloader Not supported FlashEraseAll Erase the entire...

Page 472: ...otloader uses a predefined default configuration A host application can use the Kinetis Bootloader to program the BCA for use during subsequent initializations of the bootloader Table 22 2 Configurati...

Page 473: ...8 Reserved 0x29 0x2F 7 Reserved 0x28 1 Reserved 0x30 4 Reserved 0x34 12 Reserved NOTE The flash sector containing the BCA should not be located in the execute only region because the Kinetis bootloade...

Page 474: ...the device will boot to ROM out of reset Flash memory defaults to all 1s when erased so a blank chip will automatically boot to ROM The BOOTCFG0 pin is shared with the NMI pin with NMI being the defa...

Page 475: ...ee Bootloader Exit state section If communication is detected then all inactive peripherals are shut down and the command phase is entered NOTE The flash sector containing the vector table should not...

Page 476: ...No No Yes Yes Yes Yes Yes Use the enabledPeripherals field in user config data to enable or not LPUARTn or LPSPIn or LPI2Cn Figure 22 2 Kinetis Bootloader Start up Flowchart 22 3 4 Clock Configuration...

Page 477: ..._0000 the API tree pointer is at address 0x1C00_001C The bootloader API tree is a structure that contains pointers to other structures which have the function and data addresses for the bootloader The...

Page 478: ...a transaction Each command sent from the host is replied to with a response command Commands may include an optional data phase If the data phase is incoming from host to bootloader then the data phas...

Page 479: ...ta phase The protocol for a command with an incoming data phase contains Command packet from host Generic response command packet to host Incoming data packets from host Generic response command packe...

Page 480: ...er packets while it the host is waiting for the response to a command If the Generic Response packet prior to the start of the data phase does not have a status of kStatus_Success then the data phase...

Page 481: ...etized NOTE The term target refers to the Kinetis Bootloader device There are 6 types of packets used in the device Ping packet Ping Response packet Framing packet Command packet Data packet Response...

Page 482: ...incoming Ping packet to determine the baud rate before replying with the Ping Response packet Once the Ping Response packet is received by the host the connection is established and the host starts s...

Page 483: ...ket type is used for synchronization between the host and target Table 22 8 Special Framing Packet Format Byte Value Parameter 0 0x5A start byte 1 0xAn packetType The Packet Type field specifies the t...

Page 484: ...byte 0 byte 1 byte 2 byte 3 Table 22 11 Command Header Format Byte Command Header Field 0 Command or Response tag The command header is 4 bytes long with these fields 1 Flags 2 Reserved Should be 0x0...

Page 485: ...ollow in the command sequence The number of bytes that will be transferred in the data phase is determined by a command specific parameter in the parameters array ParameterCount The number of paramete...

Page 486: ...22 14 GenericResponse Parameters Byte Parameter Descripton 0 3 Status code The Status codes are errors encountered during the execution of a command by the target Kinetis Bootloader If a command succ...

Page 487: ...or Codes NOTE All the examples in this section depict byte traffic on serial peripherals that use framing packets 22 3 8 1 Execute command The execute command results in the bootloader setting the pro...

Page 488: ...Reset 0x5a a4 04 00 6f 46 0b 00 00 00 GenericResponse 0x5a a4 0c 00 f8 0b a0 00 04 02 00 00 00 00 0b 00 00 00 ACK 0x5a a1 ACK 0x5a a1 Figure 22 6 Protocol Sequence for Reset Command Table 22 17 Reset...

Page 489: ...or SetProperty commands Properties may be read only or read write All read write properties are 32 bit integers so they can easily be carried in a command parameter For a list of properties and their...

Page 490: ...0xA7 The parameter count indicates the number of parameters sent for the property values with the first parameter showing status code 0 followed by the property value s The next table shows an exampl...

Page 491: ...mmand Byte Command 0 3 Property tag 4 7 Property value Process command Host Target SetProperty Property tag 10 Property Value 1 0x5a a4 0c 00 67 8d0c 00 00 02 0a 00 00 00 01 00 00 00 GenericResponse 0...

Page 492: ...shEraseAll command performs an erase of the entire flash memory If any flash regions are protected then the FlashEraseAll command will fail and return an error status code Executing the FlashEraseAll...

Page 493: ...reserved 0x00 parameterCount 0x00 MemoryID If MemoryID 0x00h then internal flash If MemoryID 0x01h then QSPI0 memory The FlashEraseAll command has no data phase Response The target Kinetis Bootloader...

Page 494: ...4 7 Byte count Process command Host Target ACK 0x5a a1 ACK 0x5a a1 Generic Response FlashEraseRegion startAddress 0 byteCount 1024 0x5a a4 0c 00 f9 a6 02 00 00 00 00 00 00 00 00 04 00 00 0x5a a4 0c 0...

Page 495: ...rase of the flash memory including protected sectors Flash security is immediately disabled if it flash security was enabled and the FSEC byte in the flash configuration field at address 0x40C is prog...

Page 496: ...for successful execution of the command or set to an appropriate error status code 22 3 8 8 FlashSecurityDisable command The FlashSecurityDisable command performs the flash security disable operation...

Page 497: ...x00 reserved 0x00 parameterCount 0x02 Backdoorkey_low 0x04 0x03 0x02 0x01 Backdoorkey_high 0x08 0x07 0x06 0x05 The FlashSecurityDisable command has no data phase Response The target Kinetis Bootloader...

Page 498: ...erase pattern 0xff If the VerifyWrites property is set to true then writes to flash will also perform a flash verify program operation When writing to RAM the start address need not be aligned and th...

Page 499: ...00 04 00 00 00 ACK 0x5a a1 0x5a a4 0c 00 a0 0e 04 01 00 02 00 04 00 20 40 00 00 00 Figure 22 13 Protocol Sequence for WriteMemory Command Table 22 32 WriteMemory Command Packet Format Example WriteMem...

Page 500: ...ing to the application entry point 22 4 Kinetis Flash Driver API To simplify flash code development the Kinetis ROM Bootloader has flash driver APIs that user applications can use and provides pointer...

Page 501: ...among different targets with ROM bootloader Table 22 33 Different versions of the flash driver Flash driver API version Supported targets V1 0 KL03Z4 KL43Z4 KL33Z4 KL27Z4 KL17Z4 V1 1 KL27Z644 KL17Z64...

Page 502: ...tedData flash_margin_value_t margin uint32_t failedAddress uint32_t failedData status_t flash_get_property flash_config_t config flash_property_tag_t whichProperty uint32_t value if defined FLASH_API_...

Page 503: ...lashSectorSize Size in bytes of sector of PFlash 10 4 PFlashCallback Pointer to a callback function used to do extra operations during erasure for example service watchdog 14 4 PFlashAccessSegmentSize...

Page 504: ...otalSize For FlexNVM device this is the size of FlexRAM For non FlexNVM device this is the size of acceleration RAM memory uint32_t DFlashBlockBase For FlexNVM device this is the base address of D Fla...

Page 505: ...SH_EraseAll flash_config_t config uint32_t key Table 22 37 Parameters Parameter Description config Pointer to flash_config_t data structure in memory to store driver runtime state key Key used to vali...

Page 506: ...set to 0x6B65666B Table 22 40 Possible Status Response Value Constant Description 4 kStatus_InvalidArgument Config pointer is NULL 103 kStatus_FLASH_AccessError Command is not available under current...

Page 507: ...102 kStatus_FLASH_AddressError The range to be erased is not a valid flash range 103 kStatus_FLASH_AccessError Command is not available under current mode security 104 kStatus_FLASH_ProtectionViolatio...

Page 508: ...under current mode security 104 kStatus_FLASH_ProtectionViolation The selected program flash address is protected 0 kStatus_Success This function has performed successfully Example uint32_t m_content...

Page 509: ...successfully Example flash_security_state_t state status_t status FLASH_GetSecurityState flashInstance state 22 4 5 7 FLASH_SecurityBypass Allows the user to bypass security with a backdoor key If the...

Page 510: ...status FLASH_SecurityBypass flashInstance backdoorKey 0 22 4 5 8 FLASH_VerifyEraseAll Checks if the entire flash has been erased to the specified read margin level To verify if the entire flash has be...

Page 511: ...sectors based on the desired start address and length to see if the flash has been erased at the specified read margin level FLASH_VerifyErase is often called after successfully performing the FLASH_...

Page 512: ..._Success This function has performed successfully Example Assume that flash region from 0x800 to 0xc00 has been successfully erased status_t status FLASH_VerifyErase flashInstance 0x800 1024 kFLASH_Ma...

Page 513: ...t Config or expectedData pointers are NULL 101 kStatus_FlashAlignmentError Start or lengthInBytes is not longword aligned 102 kStatus_FLASH_AddressError The range to be verified is invalid 103 kStatus...

Page 514: ...SH_PropertyPflashAccessSegmentSize 6 Get FAC segment size kFLASH_PropertyPflashAccessSegmentCou nt 7 Get FAC segment count kFLASH_PropertyVersion 32 Get version of Flash Driver API Value Pointer to th...

Page 515: ...tant Description 4 kStatus_InvalidArgument Config or src pointers are NULL 101 kStatus_FLASH_AlignmentError index or lengthInBytes is invalid 103 kStatus_FLASH_AddressError The following situation cau...

Page 516: ...rds or long words to be read Must be word aligned Table 22 62 Possible status response Value Constant Description 4 kStatus_InvalidArgument Config or dst pointers are NULL 101 kStatus_FlashAlignmentEr...

Page 517: ...0 IFR 1 Version ID of the flash module Table 22 64 Possible status response Value Constant Description 4 kStatus_InvalidArgument Config or dst pointers are NULL 101 kStatus_FLASH_AlignmentError Start...

Page 518: ...us_FLASH_CommandNotSupported This function is not supported 0 kStatus_Success This function has performed successfully Example Assume that there is a function void led_toggle void status_t status FLAS...

Page 519: ...be started by the host and each outgoing packet should be fetched by the host An incoming packet is sent by the host with a selected I2C slave address and the direction bit is set as write An outgoing...

Page 520: ...supported length Yes payload data from target No Set payload length to maximum supported length No No Reached maximum Report a timeout Yes End No 2 bytes Read 1 byte from target 0x5A received 0xA4 rec...

Page 521: ...ceived bytes should be ignored when host is sending out bytes to target Host starts reading bytes by sending 0x00s to target The byte 0x00 will be sent as response to host if target is under the follo...

Page 522: ...ds ping packet from target via SPI Fetch ACK No Yes No Next action No Process NAK Yes Report an error No Yes No maximum Report a timeout error Yes 0x5A received 0xA2 received 0xA1 received Send 0x00 t...

Page 523: ...he detection phase in order to comply with the autobaud detection algorithm After the bootloader detects the ping packet 0x5A 0xA6 on UARTn_RX the bootloader firmware executes the autobaud sequence If...

Page 524: ...n succeeds bootloader communications can take place over the UART peripheral The following flow charts show How the host detects an ACK from the target How the host detects a ping response from the ta...

Page 525: ...imeout error End Yes End No 0x5A received 0xA4 received Wait for 1 byte from target Wait for 1 byte from target retries target 2 bytes Figure 22 22 Host reads a command response from target via UART 2...

Page 526: ...bytes in the data phase ValidateRegions Yes 0Dh 4 Controls whether the bootloader will validate attempts to write to memory regions i e check if they are reserved before attempting to write ValidateR...

Page 527: ...t version of the bootloader Table 22 68 Fields of CurrentVersion property Bits 31 24 23 16 15 8 7 0 Field Name K 0x4B Major version Minor version Bugfix version 22 6 1 2 AvailablePeripherals Property...

Page 528: ...llUnsecure SetProperty Reset Reserved Execute Reserved GetProperty FlashSecurityDisable Reserved WriteMemory Reserved FlashEraseRegion FlashEraseAll 22 7 Kinetis Bootloader Status Error Codes This sec...

Page 529: ...equested command value is undefined kStatus_SecurityViolation 10001 Command is disallowed because flash security is enabled kStatus_AbortDataPhase 10002 Abort the data phase early kStatus_Ping 10003 I...

Page 530: ...OnlyProperty 10301 The requested property value cannot be written kStatus_InvalidPropertyValue 10302 The specified property value is invalid kStatus_AppCrcCheckPassed 10400 CRC check is valid and pass...

Page 531: ...rrupt on this device NOTE High Voltage Detect HVD is not supported on this device Therefore HVD related descriptions are not applicable in RCM_SRS LVD 23 2 Introduction Information found here describe...

Page 532: ...4007_F010 Mode Register RCM_MR 32 R W See section 23 3 5 540 4007_F014 Force Mode Register RCM_FM 32 R W 0000_0000h 23 3 6 541 4007_F018 Sticky System Reset Status Register RCM_SSRS 32 R W 0000_0082h...

Page 533: ...s the minor version number for the specification FEATURE Feature Specification Number This read only field returns the feature set number 0x0003 Standard feature set Chapter 23 Reset Control Module RC...

Page 534: ...ESW ELOCKUP Reserved EPOR EPIN EWDOG Reserved ELOL ELOC ELVD Reserved W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 RCM_PARAM field descriptions Field Description 31 17 Reserved This field is reserved This...

Page 535: ...feature is available on the device 0 The feature is not available 1 The feature is available 9 ELOCKUP Existence of SRS LOCKUP status indication feature This static bit states whether or not the feat...

Page 536: ...ture This static bit states whether or not the feature is available on the device 0 The feature is not available 1 The feature is available 0 Reserved This field is reserved 23 3 3 System Reset Status...

Page 537: ...erved and always has the value 0 14 Reserved This field is reserved This read only field is reserved and always has the value 0 13 SACKERR Stop Acknowledge Error Indicates that after an attempt to ent...

Page 538: ...power on detection logic Because the internal supply voltage was ramping up at the time the low voltage reset LVD status bit is also set to indicate that the reset occurred while the internal supply w...

Page 539: ...field is also set by POR 0 Reset not caused by LVD trip HVD trip or POR 1 Reset caused by LVD trip HVD trip or POR 0 Reserved This field is reserved This read only field is reserved and always has the...

Page 540: ...ng disabled 1 LPO clock filter enabled RSTFLTSRW Reset Pin Filter Select in Run and Wait Modes Selects how the reset pin filter is enabled in run and wait modes 00 All filtering disabled 01 Bus clock...

Page 541: ...guration 0 Reserved This field is reserved This read only field is reserved and always has the value 0 23 3 6 Force Mode Register RCM_FM NOTE The reset values of the bits in the FORCEROM field are for...

Page 542: ...D that have not been cleared by software Software can clear the status flags by writing a logic one to a flag Address 4007_F000h base 18h offset 4007_F018h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 1...

Page 543: ...st debugger system setting of the System Reset Request bit 1 Reset was caused by host debugger system setting of the System Reset Request bit 10 SSW Sticky Software Indicates a reset has been caused b...

Page 544: ...to the detailed SCG description for information on enabling the clock monitor 0 Reset not caused by a loss of external clock 1 Reset caused by a loss of external clock 1 SLVD Sticky Low Voltage Detec...

Page 545: ...This field is reserved This read only field is reserved and always has the value 0 13 SACKERR Stop Acknowledge Error Interrupt 0 Interrupt disabled 1 Interrupt enabled 12 Reserved This field is reser...

Page 546: ...Interrupt enabled 4 Reserved This field is reserved This read only field is reserved and always has the value 0 3 LOL Loss of Lock Interrupt 0 Interrupt disabled 1 Interrupt enabled 2 LOC Loss of Cloc...

Page 547: ...es in these modes Following stated are general power modes which are supported additionally by certain clocking mode options Clock gating technique is used for general power modes and for the addition...

Page 548: ...ator is on Run Normal Wait via WFI Allows peripherals to function while the core is in sleep mode reducing power NVIC remains sensitive to interrupts peripherals continue to be clocked Sleep Interrupt...

Page 549: ...to the corresponding module Prior to initializing a module set the corresponding bit in the PCC peripheral control register to enable the clock Before turning off the clock make sure to disable the m...

Page 550: ...automatically on detection of an interrupt which is required in order to service most interrupts Only the core system interrupts exceptions including NMI and SysTick and any edge sensitive interrupts...

Page 551: ...rupt In the Stop mode some peripherals can remain operational with asynchronous clock and can wake up the MCU as needed Stop mode configurations can be selected by configuring SMC_PMCTRL In Stop mode...

Page 552: ...t not the core clock and negating the stop mode signal to the bus masters and bus slaves The only difference is that the CPU will remain in the low power mode with the CPU clock disabled During Comput...

Page 553: ...peripherals can generate an asynchronous DMA request in stop modes although in general if a peripheral can generate synchronous DMA requests and also supports asynchronous interrupts in stop modes th...

Page 554: ...chapter describes interrupt operation and what peripherals can cause interrupts NOTE The WFE instruction can have the side effect of entering a low power mode but that is not its intended usage See AR...

Page 555: ...place the chip in the targeted low power state All low power entry sequences are initiated by the core executing an WFI instruction The ARM core s outputs SLEEPDEEP and SLEEPING trigger entry to the v...

Page 556: ...tiated by setting the Debug Request bit in MDM AP control register As part of this transition system clocking is re established and is equivalent to normal run VLPR mode clocking configuration 24 5 Mo...

Page 557: ...or SOSC SOSC_CLK optional ON SOSC_CLK optional ON SOSC_CLK optional ON SOSC_CLK optional ON 32 kHz oscillator OSC32 Optional ON Optional ON Optional ON Optional ON SCG SOSC SIRC FIRC LPFLL optional ON...

Page 558: ...F SIRC FIRC and SOSC clocks only FF SIRC FIRC and SOSC clocks only FF SIRC FIRC and SOSC clocks only FF SIRC FIRC and SOSC clocks only CMP 3 LS compare only LS compare only LS compare FF in PSTOP2 LS...

Page 559: ...tion of a DMA wakeup The CPU is in Compute Operation including the entry sequence and for the duration of a DMA wakeup Peripheral Doze can therefore be used to disable selected bus masters or slaves f...

Page 560: ...rom SIRC or OSC LPUART Functional in Stop VLPS modes with clock source from SIRC or OSC LPSPI Functional in Stop VLPS modes with clock source from SIRC or OSC LPIT Functional in Stop VLPS modes with c...

Page 561: ...m can start The LVD circuit can be used to monitor the power supply voltage by comparing it to a configurable threshold User can choose to generate LVD reset or LVW interrupt when power supply voltage...

Page 562: ...Power supply supervisor Kinetis KE1xZ256 Sub Family Reference Manual Rev 3 07 2018 562 NXP Semiconductors...

Page 563: ...each mode and the functionality available while in each of the modes The SMC is able to function during even the deepest low power modes See AN4503 Power Management for Kinetis MCUs for further detail...

Page 564: ...memory I O states are held in all modes of operation Several registers are used to configure the various modes of operation for the device The following table describes the power modes available for t...

Page 565: ...ing entered correctly SMC memory map Absolute address hex Register name Width in bits Access Reset value Section page 4007_E000 SMC Version ID Register SMC_VERID 32 R 0100_0000h 25 3 1 565 4007_E004 S...

Page 566: ...mber This read only field returns the feature set number 0x0000 Standard features implemented 25 3 2 SMC Parameter Register SMC_PARAM Address 4007_E000h base 4h offset 4007_E004h Bit 31 30 29 28 27 26...

Page 567: ...he feature is available 2 1 Reserved This field is reserved This read only field is reserved and always has the value 0 0 EHSRUN Existence of HSRUN feature This static bit states whether or not the fe...

Page 568: ...ways has the value 0 5 AVLP Allow Very Low Power Modes Provided the appropriate control bits are set up in PMCTRL this write once field allows the MCU to enter any very low power mode VLPR VLPW and VL...

Page 569: ...29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 RUNM 0 STOPA STOPM W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SMC_PMCT...

Page 570: ...selected stop mode when Sleep Now or Sleep On Exit mode is entered with SLEEPDEEP 1 Writes to this field are blocked if the protection level has not been enabled using the PMPROT register After any s...

Page 571: ...consumption In PSTOP2 only system clocks are gated allowing peripherals running on bus clock to remain fully functional In PSTOP1 both system and bus clocks are gated 00 STOP Normal Stop mode 01 PSTOP...

Page 572: ...0 0 0 0 0 0 0 0 0 0 0 0 0 1 SMC_PMSTAT field descriptions Field Description 31 8 Reserved This field is reserved This read only field is reserved and always has the value 0 PMSTAT Power Mode Status N...

Page 573: ...re Table 25 2 Power mode transition triggers Transition From To Trigger conditions 1 RUN WAIT Sleep now or sleep on exit modes entered with SLEEPDEEP clear controlled in System Control Register in Arm...

Page 574: ...was entered directly from RUN transition 7 hardware forces exit back to RUN and does not allow a transition to VLPR 7 RUN VLPS PMPROT AVLP 1 PMCTRL STOPM 010 Sleep now or sleep on exit modes entered w...

Page 575: ...igure 25 2 Low power system components and connections 25 4 2 1 Stop mode entry sequence Entry into a low power stop mode Stop VLPS is initiated by a CPU executing the WFI instruction After the instru...

Page 576: ...e the SMC can abort the transition early and return to RUN mode without completely entering the stop mode An aborted entry is possible only if the interrupt occurs before the PMC begins the transition...

Page 577: ...r reduce power in this mode disable the clocks to unused modules using their corresponding clock gating control bits in the PCC s registers Before entering this mode the following conditions must be m...

Page 578: ...ut peripherals continue to be clocked provided they are enabled When an interrupt request occurs the CPU exits WAIT mode and resumes processing in RUN mode beginning with the stacking operations leadi...

Page 579: ...t entry with the SLEEPDEEP bit set in the System Control Register in the Arm core The available stop modes are Normal Stop STOP Very Low Power Stop VLPS 25 4 5 1 STOP mode STOP mode is entered via the...

Page 580: ...l also cause a VLPS exit returning the device to normal RUN mode 25 4 6 Debug in low power modes When the MCU is secure the device disables limits debugger operation When the MCU is unsecure the Arm d...

Page 581: ...ction The PMC contains the internal voltage regulator power on reset POR and the low voltage detect LVD system 26 3 Features The PMC features include Internal voltage regulator offering a variety of p...

Page 582: ...status of the low voltage detect system The low voltage detect flag LVDF operates in a level sensitive manner The LVDF bit is set when the supply voltage falls below the trip point VLVD The LVDF bit...

Page 583: ...o indicate that the supply voltage is approaching but is above the LVD voltage The LVW also has an interrupt which is enabled by setting the PMC_LVDSC2 LVWIE bit If enabled an LVW interrupt request oc...

Page 584: ...ator is in low power mode the LVD system is disabled regardless of the PMC_LVDSC1 settings Address 4007_D000h base 0h offset 4007_D000h Bit 7 6 5 4 3 2 1 0 Read LVDF LVDIE LVDRE 0 Write LVDACK Reset 0...

Page 585: ...the low voltage warning LVW function NOTE When the internal voltage regulator is in low power mode the LVD system is disabled regardless of the PMC_LVDSC2 settings Address 4007_D000h base 1h offset 40...

Page 586: ...tion 7 LPODIS LPO Disable Bit This bit enables or disable the low power oscillator NOTE After disabling the LPO a time of 2 LPO clock cycles is required before it is allowed to enable it again Violati...

Page 587: ...e the bias currents and reference voltages for the following clock modules are disabled SIRC FIRC PLL if available on device 0 BIASEN Bias Enable Bit This bit enables source and well biasing for the c...

Page 588: ...field After POR reset automatically loaded from Flash Memory IFR after Reset normal system reset PMC_LPOTRIM field descriptions Field Description 7 5 Reserved This field is reserved This read only fi...

Page 589: ...read only The SEC bit of FSEC byte controls the chip security status After enabling device security the debug port SWD cannot access the memory resources of the MCU and ROM boot loader also limited t...

Page 590: ...and can no longer unsecure the MCU When backdoor key access is disabled FlashSecurityDisable command cannot be used Please refer to the ROM chapter for more details 27 2 2 Flash access protection FAC...

Page 591: ...DMH SIM_UIDML and SIM_UIDL registers Please refer to the SIM chapter for more details 27 4 2 Program Once Field This device also contains 96 bytes Program Once Field in the program flash 0 IFR User ca...

Page 592: ...General security features Kinetis KE1xZ256 Sub Family Reference Manual Rev 3 07 2018 592 NXP Semiconductors...

Page 593: ...nter must not occur if the software code works well and services the watchdog to re start the actual counter The EWM differs from the internal watchdog in that it does not reset the MCU s CPU and peri...

Page 594: ...ough a reset the EWM remains disabled On exit from stop mode by an interrupt the EWM is re enabled and the counter continues to be clocked from the same value prior to entry to stop mode Note the foll...

Page 595: ...k Divider Logic LPO_CLK Low Power Clock Clock Gating Cell AND Enable EWM_CTRL EWMEN EWM_CLKPRESCALER CLK_DIV 8 bit Counter OR Counter Value Reset to Counter EWM Refresh And EWM_out Output Control Mech...

Page 596: ...ontrol Register EWM_CTRL 8 R W 00h 28 3 1 596 4006_1001 Service Register EWM_SERV 8 W always reads 0 00h 28 3 2 597 4006_1002 Compare Low Register EWM_CMPL 8 R W 00h 28 3 3 597 4006_1003 Compare High...

Page 597: ...Register EWM_SERV The SERV register provides the interface from the CPU to the EWM module It is write only and reads of this register return zero Address 4006_1000h base 1h offset 4006_1001h Bit 7 6...

Page 598: ...ocks time for the CPU to refresh the EWM counter NOTE This register can be written only once after a CPU reset Writing this register more than once generates a bus transfer error NOTE The valid values...

Page 599: ...ected low power clock source for running the EWM counter can be prescaled as below Prescaled clock frequency low power clock source frequency 1 CLK_DIV 28 4 Functional Description The following sectio...

Page 600: ...the EWM_out signal only after the EWM is enabled by the EWMEN bit in the CTRL register Note EWM_out pad must be in pull down state when EWM functionality is used and when EWM is under Reset 28 4 2 The...

Page 601: ...accessible to the CPU 28 4 4 EWM Compare Registers The compare registers CMPL and CMPH are write once after a CPU reset and cannot be modified until another CPU reset occurs The EWM compare registers...

Page 602: ...signal is asserted irrespective of the input EWM_in 28 4 6 EWM Interrupt When EWM_out is asserted an interrupt request is generated to indicate the assertion of the EWM reset out signal This interrup...

Page 603: ...the EWM module It enables EWM_in pin input with assert state logic zero enables interrupt when EWM_out is assert The compare value is also set into CMPL H register before enabling EWM Initialize the E...

Page 604: ...Usage Guide Kinetis KE1xZ256 Sub Family Reference Manual Rev 3 07 2018 604 NXP Semiconductors...

Page 605: ...s module Peripheral Clocking WDOG PCC module SOSC SIRC SCG module SCG DIVSLOW SOSC_CLK SIRC_CLK WDOG module BUS_CLK LPO_CLK WDOG_CS CLK Peripheral Interface Clock 00 01 10 11 Registers 29 1 2 WDOG low...

Page 606: ...inputs independent from the bus clock Bus clock slow clock LPO clock from PMC SIRC 8 MHz IRC from SCG ERCLK external reference clock from SCG Programmable timeout period Programmable 16 bit timeout va...

Page 607: ...ow 29 2 2 Block diagram The following figure shows a block diagram of the WDOG module MUX MUX MUX ERCLK SIRC UPDATE EN CLK PRES WIN INT BUS_CLK 256 16 bit Window Register 0xD928 0xC520 Control Status...

Page 608: ...g Control and Status Register NOTE TST is cleared 0 0 on POR only Any other reset does not affect the value of this field Address 4005_2000h base 0h offset 4005_2000h Bit 31 30 29 28 27 26 25 24 23 22...

Page 609: ...6 pre scaling of watchdog counter reference clock The block diagram shows this clock divider option 0 256 prescaler disabled 1 256 prescaler enabled 11 ULK Unlock status This read only bit indicates w...

Page 610: ...nter to demonstrate that the watchdog is functioning properly See the Fast testing of the watchdog section This write once field is cleared 0 0 on POR only Any other reset does not affect the value of...

Page 611: ...base 4h offset 4005_2004h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 CNTHIGH CNTLOW W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 612: ...he watchdog window register When window mode is enabled CS WIN is set The WIN register determines the earliest time that a refresh sequence is considered valid See the Watchdog refresh mechanism secti...

Page 613: ...ce independent of the bus clock for applications that need to meet more robust safety requirements Using a clock source other than the bus clock ensures that the watchdog counter continues to run if t...

Page 614: ...he configuration time period 128 bus clocks ends This delay ensures a smooth transition before restarting the counter with the new configuration 29 4 2 Watchdog refresh mechanism The watchdog resets t...

Page 615: ...early When Window mode is enabled the watchdog must be refreshed after the counter has reached a minimum expected time value otherwise the watchdog resets the MCU The minimum expected time value is sp...

Page 616: ...ts and ensuring that CS UPDATE is also set to 0 This provides a robust mechanism to configure the watchdog and ensure that a runaway condition cannot mistakenly disable or modify the watchdog configur...

Page 617: ...bled CS INT 1 After a reset triggering event like a counter timeout or invalid refresh attempt the watchdog first generates an interrupt request Next the watchdog delays 128 bus clocks from the interr...

Page 618: ...t run to the overflow value takes a relatively long time 64 kHz clocks To help minimize the startup delay for application code after reset the watchdog has a feature to test the watchdog more quickly...

Page 619: ...and compare functions work for the selected byte Repeat the procedure selecting the other byte in step 2 NOTE CS TST is cleared by a POR only and not affected by other resets 29 4 7 2 Entering user mo...

Page 620: ...be configured once by set the WDOG_CS UPDATE 0 After that the watchdog cannot be reconfigured until a reset If set WDOG_CS UPDATE 1 when configuring the watchdog the watchdog can be reconfigured with...

Page 621: ...shing the Watchdog To refresh the watchdog and reset the watchdog counter to zero a refresh sequence is required DisableInterrupts disable global interrupt WDOG_CNT 0xB480A602 refresh watchdog EnableI...

Page 622: ...Application Information Kinetis KE1xZ256 Sub Family Reference Manual Rev 3 07 2018 622 NXP Semiconductors...

Page 623: ...t or 32 bit programmable shift register Programmable initial seed value and polynomial Option to transpose input data or output data the CRC result bitwise or bytewise This option is required for cert...

Page 624: ...CRC calculation in progress stops when the MCU enters a low power mode that disables the module clock It resumes after the clock is enabled or via the system reset for exiting the low power mode Cloc...

Page 625: ...1 0 R HU HL LU LL W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 CRC_DATA field descriptions Field Description 31 24 HU CRC High Upper Byte In 16 bit CRC mode CTRL TCRC is 0...

Page 626: ...al Half word Writable and readable in 32 bit CRC mode CTRL TCRC is 1 This field is not writable in 16 bit CRC mode CTRL TCRC is 0 LOW Low Polynominal Half word Writable and readable in both 32 bit and...

Page 627: ...ransposed 27 Reserved This field is reserved This read only field is reserved and always has the value 0 26 FXOR Complement Read Of CRC Data Register Some CRC protocols require the final checksum to b...

Page 628: ...compute a 16 bit CRC 1 Clear CRC_CTRL TCRC to enable 16 bit CRC mode 2 Program the transpose and complement options in the CTRL register as required for the CRC calculation See Transpose feature and...

Page 629: ...result complement for details 30 3 3 Transpose feature By default the transpose feature is not enabled However some CRC standards require the input data and or the final checksum to be transposed The...

Page 630: ...Transpose type 01 3 CTRL TOT or CTRL TOTR is 10 Both bits in bytes and bytes are transposed reg 31 0 becomes reg 0 7 reg 8 15 reg 16 23 reg 24 31 31 31 0 0 Figure 30 3 Transpose type 10 4 CTRL TOT or...

Page 631: ...complement When CTRL FXOR is set the checksum is complemented The CRC result complement function outputs the complement of the checksum value stored in the CRC data register every time the CRC data re...

Page 632: ...CRC_CTRL_TOT 3 CRC_CTRL_TOTR 0 CRC_CTRL_FXOR 1 CRC_CTRL_TCRC 1 CRC_CTRL_WAS 0 write polynomial register CRC_GPOLY 0x04c11bd7 write pre computed control register value along with WAS to start checksum...

Page 633: ...L CRC_CTRL_WAS 1 write seed initial checksum CRC_DATA 0 deassert WAS by writing pre computed CRC control register value CRC_CTRL CRC_CTRL_WAS 1 write data dataSize sizeof data 8 bit reads and writes t...

Page 634: ...Usage Guide Kinetis KE1xZ256 Sub Family Reference Manual Rev 3 07 2018 634 NXP Semiconductors...

Page 635: ...ins default to their SWD functionality after power on reset POR Table 31 1 Serial wire debug pin description Pin Name Type Description SWD_CLK Input Serial Wire Clock This pin is the clock for debug l...

Page 636: ...DAP control and status registers are not memory mapped within the system memory map and are only accessible via the Debug Access Port using SWD The MDM AP is accessible as Debug Access Port 1 with the...

Page 637: ...t SELECT Read Buffer RDBUFF DP Registers 0x00 0x04 0x08 0x0C Data 31 0 A 3 2 RnW DPACC Data 31 0 A 3 2 RnW APACC Debug Port DP Generic See the ARM Debug Interface v5p1 Supplement Figure 31 1 MDM AP ad...

Page 638: ...e 31 4 MDM AP Control register assignments Bit Name Secure1 Description 0 Flash Mass Erase in Progress Y Set to cause mass erase Cleared by hardware after mass erase operation completes 1 Debug Disabl...

Page 639: ...system reset in the DAP control register which allows the debugger to hold the core in reset 31 5 Micro Trace Buffer MTB The Micro Trace Buffer MTB provides a simple execution trace capability for th...

Page 640: ...de exits and the system returns to a state with active debug If the debugger logic is powered off the debugger is reset on recovery and must be reconfigured once the low power mode is exited The activ...

Page 641: ...AM controller manages requests from two sources AMBA AHB reads and writes from the system bus program trace packet writes from the processor As part of the MTB functionality there is a DWT Data Watchp...

Page 642: ...ort from the processor core The private MTB port signals the instruction address information needed for the 64 bit program trace packets written into the system RAM The PRAM controller output interfac...

Page 643: ...ond higher addressed word contains the destination of the branch the address it branched to The value stored only records bits 31 1 of the branch address The least significant bit of the value is the...

Page 644: ...o approximately 1600 processor cycles per KB This metric is obviously very sensitive to the runtime characteristics of the user code The MTB_DWT function not shown in the core platform block diagram m...

Page 645: ...priate crossbar slave port plus the private execution trace bus from the processor core The signals in the private execution trace bus are detailed in the following table taken from the Arm CoreSight...

Page 646: ...ions Attempting to access these locations can result in UNPREDICTABLE behavior The behavior of the MTB is UNPREDICTABLE if the registers with UNKNOWN reset values are not programmed prior to enabling...

Page 647: ...2 R See section 32 3 1 14 658 F000_0FD4 Peripheral ID Register MTB_PERIPHID5 32 R See section 32 3 1 14 658 F000_0FD8 Peripheral ID Register MTB_PERIPHID6 32 R See section 32 3 1 14 658 F000_0FDC Peri...

Page 648: ...In this configuration the MTB_POSITION register is initialized to 0x2000_0000 0x0000_7FF8 0x0000_00000 Following these two suggested placements provides a full featured circular memory buffer contain...

Page 649: ...re RAZ WI Therefore the active bits in this field are POSITION 14 3 POSITION POINTER 11 0 2 WRAP WRAP This field is set to 1 automatically when the POINTER value wraps as determined by the MTB_MASTER...

Page 650: ...cause MTB_FLOW WATERMARK is set then it is not automatically set to 1 if TSTARTEN is 1 and the TSTART input is HIGH In this case tracing can only be restarted if MTB_FLOW WATERMARK or MTB_POSITION POI...

Page 651: ...nd the MTB_POSITION 14 MASK 3 MTB_POSITION POINTER 11 MASK 1 bits remain unchanged This field causes the trace packet information to be stored in a circular buffer of size 2 MASK 4 bytes that can be p...

Page 652: ...RK field value actions defined by the AUTOHALT and AUTOSTOP bits are performed 2 Reserved This field is reserved This read only field is reserved and always has the value 0 1 AUTOHALT AUTOHALT If this...

Page 653: ...DR BASEADDR This value is defined with a hardwired signal and the expression 0x2000_0000 RAM_Size 4 For example if the total RAM capacity is 16 KB this field is 0x1FFF_F000 32 3 1 5 Integration Mode C...

Page 654: ...32 3 1 7 Claim TAG Clear Register MTB_TAGCLEAR The read write Claim Tag Clear Register is used to read the claim status on debug resources A read indicates the claim tag status Writing 1 to a specifi...

Page 655: ...r It is hardwired to specific values used during the auto discovery process by an external debug agent Address F000_0000h base FB4h offset F000_0FB4h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1...

Page 656: ...field is reserved and always has the value 0 3 Reserved BIT3 This read only field is reserved and always has the value 1 2 BIT2 BIT2 Connected to NIDEN or DBGEN signal 1 Reserved BIT1 This read only...

Page 657: ...ICECFG field descriptions Field Description DEVICECFG DEVICECFG Hardwired to 0x0000_0000 32 3 1 13 Device Type Identifier Register MTB_DEVICETYPID This register indicates the device type ID It is hard...

Page 658: ...ID Register MTB_COMPIDn These registers indicate the component IDs They are hardwired to specific values used during the auto discovery process by an external debug agent Address F000_0000h base FF0h...

Page 659: ...MTBDWT_DEVICETYPID 32 R 0000_0004h 32 3 2 8 667 F000_1FD0 Peripheral ID Register MTBDWT_PERIPHID4 32 R See section 32 3 2 9 668 F000_1FD4 Peripheral ID Register MTBDWT_PERIPHID5 32 R See section 32 3...

Page 660: ...NOCYCCNT 1 cycle counter is not supported MTBDWT_CTRL 24 NOPRFCNT 1 profiling counters are not supported MTBDWT_CTRL 22 CYCEBTENA 0 no POSTCNT underflow packets generated MTBDWT_CTRL 21 FOLDEVTENA 0 n...

Page 661: ...MASTER MASK Address F000_1000h base 24h offset 16d i where i 0d to 1d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 MASK W Reset 0 0 0 0 0 0 0 0 0 0 0 0...

Page 662: ...31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 MATCHED 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R DATAVADDR0 DATAVSIZE 0 DATAVMATCH 0 FUNCTION W Rese...

Page 663: ...rd 10 Word 11 Reserved Any attempts to use this value results in UNPREDICTABLE behavior 9 Reserved This field is reserved This read only field is reserved and always has the value 0 8 DATAVMATCH Data...

Page 664: ...0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 FUNCTION W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MTBDWT_FCT1 field descriptions Field Description 31 25 Reserved This field is reserved...

Page 665: ...o use this value results in UNPREDICTABLE behavior 32 3 2 6 MTB_DWT Trace Buffer Control Register MTBDWT_TBCTRL The MTBDWT_TBCTRL register defines how the watchpoint comparisons control the actual tra...

Page 666: ...of MTBDWT_FCT1 MATCHED 1 Trigger TSTART based on the assertion of MTBDWT_FCT1 MATCHED 0 ACOMP0 Action based on Comparator 0 match When the MTBDWT_FCT0 MATCHED is set it indicates MTBDWT_COMP0 address...

Page 667: ...CFG DEVICECFG Hardwired to 0x0000_0000 32 3 2 8 Device Type Identifier Register MTBDWT_DEVICETYPID This register indicates the device type ID It is hardwired to specific values used during the auto di...

Page 668: ...t ID Register MTBDWT_COMPIDn These registers indicate the component IDs They are hardwired to specific values used during the auto discovery process by an external debug agent Address F000_1000h base...

Page 669: ...ID Debug control Data watchpoint unit CoreSight ID Watchpoint control Breakpoint unit CoreSight ID Breakpoint control Optional component Figure 32 3 CoreSight discovery process ROM memory map Absolute...

Page 670: ...nt ID Register ROM_COMPID1 32 R See section 32 3 3 5 672 F000_2FF8 Component ID Register ROM_COMPID2 32 R See section 32 3 3 5 672 F000_2FFC Component ID Register ROM_COMPID3 32 R See section 32 3 3 5...

Page 671: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ROM_TABLEMARK field descriptions Field Description MARK MARK Hardwired to 0x0000_0000 32 3 3 3 System Access Register ROM_SYSACCESS This register indicates system a...

Page 672: ...0x0000_0008 and all the others to 0x0000_0000 32 3 3 5 Component ID Register ROM_COMPIDn These registers indicate the component IDs They are hardwired to specific values used during the auto discovery...

Page 673: ...more information about MTB please refer to the ARM document ARM Debug Interface Architecture Specification Chapter 32 Micro Trace Buffer MTB Kinetis KE1xZ256 Sub Family Reference Manual Rev 3 07 2018...

Page 674: ...Usage Guide Kinetis KE1xZ256 Sub Family Reference Manual Rev 3 07 2018 674 NXP Semiconductors...

Page 675: ...pin and the locations of these pins on the devices The Port Control Module is responsible for selecting which ALT functionality is available on each pin NOTE On this device there are several special...

Page 676: ...VREFH VREFH VREFH 13 VREFL VREFL VREFL 14 VSS VSS VSS 15 11 PTB7 EXTAL EXTAL PTB7 LPI2C0_SCL 16 12 PTB6 XTAL XTAL PTB6 LPI2C0_SDA 17 PTE14 DISABLED PTE14 FTM0_FLT1 18 13 PTE3 TSI0_CH24 TSI0_CH24 PTE3...

Page 677: ...T3 LPI2C1_SCLS 44 28 PTC16 ADC0_SE14 ADC0_SE14 PTC16 FTM1_FLT2 LPI2C1_SDAS 45 29 PTC15 ADC0_SE13 ADC0_SE13 PTC15 FTM1_CH3 46 30 PTC14 ADC0_SE12 ADC0_SE12 PTC14 FTM1_CH2 47 31 PTB3 ADC0_SE7 TSI0_CH21 A...

Page 678: ...C0_SE1 ACMP0_IN1 TSI0_CH18 PTA1 FTM1_CH1 LPI2C0_SDAS FXIO_D3 FTM1_QD_ PHA LPUART0_ RTS TRGMUX_ OUT0 79 50 PTA0 ADC0_SE0 ACMP0_IN0 TSI0_CH17 ADC0_SE0 ACMP0_IN0 TSI0_CH17 PTA0 FTM2_CH1 LPI2C0_SCLS FXIO_...

Page 679: ...lease see the respective module chapter and Port control and interrupt module features for details 100 LQFP 64 LQFP Pin Name Driver strength Default status after POR Pullup pulldown setting after POR...

Page 680: ...Y 32 23 PTD6 ND Hi Z Y 33 24 PTD5 ND Hi Z Y 34 PTD12 ND Hi Z Y 35 PTD11 ND Hi Z Y 36 PTD10 ND Hi Z Y 37 VSS 38 VDD 39 25 PTC1 ND Hi Z Y 40 26 PTC0 ND Hi Z Y 41 PTD9 ND Hi Z Y 42 PTD8 ND Hi Z Y 43 27 P...

Page 681: ...D Hi Z Y 72 47 PTA3 ND Hi Z Y 73 48 PTA2 ND Hi Z Y 74 PTB11 ND Hi Z Y 75 PTB10 ND Hi Z Y 76 PTB9 ND Hi Z Y 77 PTB8 ND Hi Z Y 78 49 PTA1 ND Hi Z Y 79 50 PTA0 ND Hi Z Y 80 51 PTC7 ND Hi Z Y 81 52 PTC6 N...

Page 682: ...gh impendence H High level L Low level Pullup pulldown setting after POR PU Pullup PD Pulldown Slew rate after POR FS Fast slew rate SS Slow slew rate Passive Pin Filter after POR N Disabled Y Enabled...

Page 683: ...TE9 PTD15 PTD16 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 99 79 78 77 76 PTA9 PTA0 PTA1 PTB8 PTB9 50 49 48 47 46 45 44 43 42 41 PTC12 PTC13 PTB2 PTB3 PTC14 PTC15 PTC16 PTC17 PTD8 PTD9 PTC0 PTC1 VDD...

Page 684: ...PTA13 PTE2 PTE6 PTC6 PTC7 PTA0 PTA1 PTA2 PTA3 PTD2 PTD3 PTD4 PTB12 PTB13 VDD VSS PTE7 PTA6 PTA7 PTC8 PTC9 PTB0 PTB1 PTB2 PTB3 PTC14 PTC15 PTC16 PTC17 PTC0 PTC1 PTD5 PTD6 PTD7 PTC2 Figure 33 2 64 LQFP...

Page 685: ...signal I O VDD MCU power I VSS MCU ground I Table 33 3 EWM Signal Descriptions Chip signal name Module signal name Description I O EWM_IN EWM_in EWM input for safety status of external safety circuit...

Page 686: ...Chip signal name Module signal name Description I O ADC1_SE 11 0 AD 11 0 Single Ended Analog Channel Inputs I VREFH VREFSH Voltage Reference Select High I VREFL VREFSL Voltage Reference Select Low I V...

Page 687: ...M external clock can be selected to drive the FTM counter I Table 33 13 FTM1 Signal Descriptions Chip signal name Module signal name Description I O FTM1_CH 1 0 CHn FTM channel n where n can be 1 0 I...

Page 688: ...Q Host request can initiate an LPI2C master transfer if asserted and the I2C bus is idle I LPI2Cn_SCLS SCLS Secondary I2C clock line I O LPI2Cn_SDAS SDAS Secondary I2C data line I O Table 33 17 LPUART...

Page 689: ...17 0 PORTC17 PORTC0 General purpose input output I O PTD 17 0 PORTD17 PORTD0 General purpose input output I O PTE 16 0 PORTE16 PORTE0 General purpose input output I O Table 33 20 TSI0 Signal Descripti...

Page 690: ...Module Signal Description Tables Kinetis KE1xZ256 Sub Family Reference Manual Rev 3 07 2018 690 NXP Semiconductors...

Page 691: ...T7 out en ALT5 out en ALT6 out en MUX 0 1 2 3 4 5 6 7 PDO ALT2 out data ALT3 out data ALT4 out data ALT7 out data ALT5 out data ALT6 out data glitch filter VDD PE PS VDD 0 1 1 1 1 PFE SRE DSE ODE 0 1...

Page 692: ...d Others Disabled Disabled Disabled Disabled Disabled Open drain enable control I2C and UART Tx Enabled Others Disabled I2C and UART Tx Enabled Others Disabled I2C and UART Tx Enabled Others Disabled...

Page 693: ...pport for port control digital filtering and external interrupt functions Most functions can be configured independently for each pin in the 32 bit port and affect the pin regardless of its pin muxing...

Page 694: ...al pin muxing modes 34 3 2 Modes of operation 34 3 2 1 Run mode In Run mode the PORT operates normally 34 3 2 2 Wait mode In Wait mode PORT continues to operate normally and may be configured to exit...

Page 695: ...ynchronously to the system clock Negation may occur at any time and can assert asynchronously to the system clock 34 6 Memory map and register definition Any read or write access to the PORT memory sp...

Page 696: ...ee section 34 6 1 702 4004_9050 Pin Control Register n PORTA_PCR20 32 R W See section 34 6 1 702 4004_9054 Pin Control Register n PORTA_PCR21 32 R W See section 34 6 1 702 4004_9058 Pin Control Regist...

Page 697: ...1 702 4004_A044 Pin Control Register n PORTB_PCR17 32 R W See section 34 6 1 702 4004_A048 Pin Control Register n PORTB_PCR18 32 R W See section 34 6 1 702 4004_A04C Pin Control Register n PORTB_PCR1...

Page 698: ..._B038 Pin Control Register n PORTC_PCR14 32 R W See section 34 6 1 702 4004_B03C Pin Control Register n PORTC_PCR15 32 R W See section 34 6 1 702 4004_B040 Pin Control Register n PORTC_PCR16 32 R W Se...

Page 699: ...tion 34 6 1 702 4004_C030 Pin Control Register n PORTD_PCR12 32 R W See section 34 6 1 702 4004_C034 Pin Control Register n PORTD_PCR13 32 R W See section 34 6 1 702 4004_C038 Pin Control Register n P...

Page 700: ...D024 Pin Control Register n PORTE_PCR9 32 R W See section 34 6 1 702 4004_D028 Pin Control Register n PORTE_PCR10 32 R W See section 34 6 1 702 4004_D02C Pin Control Register n PORTE_PCR11 32 R W See...

Page 701: ...Pin Control Low Register PORTE_GPCLR 32 W always reads 0 0000_0000h 34 6 2 705 4004_D084 Global Pin Control High Register PORTE_GPCHR 32 W always reads 0 0000_0000h 34 6 3 705 4004_D0A0 Interrupt Stat...

Page 702: ...0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R LK 0 MUX 0 DSE Reserved PFE 0 Reserved PE PS W Reset 0 0 0 0 0 0 0 0 0 Notes MUX field Varies by port See Signal Multiplexing and Signal D...

Page 703: ...0001 ISF flag and DMA request on rising edge 0010 ISF flag and DMA request on falling edge 0011 ISF flag and DMA request on either edge 0100 Reserved 0101 Reserved 0110 Reserved 0111 Reserved 1000 IS...

Page 704: ...the corresponding pin 1 Passive input filter is enabled on the corresponding pin if the pin is configured as a digital input Refer to the device data sheet for filter characteristics 3 Reserved This...

Page 705: ...bits 15 0 that are selected by GPWE 34 6 3 Global Pin Control High Register PORTx_GPCHR Only 32 bit writes are supported to this register Address Base address 84h offset Bit 31 30 29 28 27 26 25 24 23...

Page 706: ...he completion of the requested DMA transfer Otherwise the flag remains set until a logic 1 is written to the flag If the pin is configured for a level sensitive interrupt and the pin remains asserted...

Page 707: ...s field is reserved This read only field is reserved and always has the value 0 0 CS Clock Source The digital filter configuration is valid in all digital pin muxing modes Configures the clock source...

Page 708: ...rt pin It also includes a flag to indicate that an interrupt has occurred The lower half of the Pin Control register configures the following functions for each pin within the 32 bit port Pullup or pu...

Page 709: ...ower consumption 34 7 2 Global pin control The two global pin control registers allow a single register write to update the lower half of the pin control register on up to 16 pins all with the same va...

Page 710: ...s detected This also generates an asynchronous wake up signal to exit the Low Power mode 34 7 4 Digital filter The digital filter capabilities of the PORT module are available in all digital Pin Muxin...

Page 711: ...he output of the digital filter updates to equal the synchronized filter input The maximum latency through a digital filter equals three filter clock cycles plus the filter width configuration registe...

Page 712: ...Functional description Kinetis KE1xZ256 Sub Family Reference Manual Rev 3 07 2018 712 NXP Semiconductors...

Page 713: ...GPIO accessibility in the memory map The GPIO is multi ported and can be accessed directly by the core with zero wait states at base address 0xF800_0000 It can also be accessed by the core and DMA ma...

Page 714: ...sters Port Data Direction register Zero wait state access to GPIO registers through IOPORT NOTE The GPIO module is clocked by system clock 35 2 2 Modes of operation The following table depicts differe...

Page 715: ...ng Assertion When output this signal occurs on the rising edge of the system clock For input it may occur at any time and input may be asserted asynchronously to the system clock Deassertion When outp...

Page 716: ...32 W always reads 0 0000_0000h 35 3 4 719 400F_F050 Port Data Input Register GPIOB_PDIR 32 R 0000_0000h 35 3 5 719 400F_F054 Port Data Direction Register GPIOB_PDDR 32 R W 0000_0000h 35 3 6 720 400F_...

Page 717: ...32 R W 0000_0000h 35 3 6 720 35 3 1 Port Data Output Register GPIOx_PDOR This register configures the logic levels that are driven on each general purpose output pins NOTE Do not modify pin configura...

Page 718: ...n PDORn is set to logic 1 35 3 3 Port Clear Output Register GPIOx_PCOR This register configures whether to clear the fields of PDOR Address Base address 8h offset Bit 31 30 29 28 27 26 25 24 23 22 21...

Page 719: ...lable in your selected package All unbonded pins not available in your package will default to DISABLE state for lowest power consumption Address Base address 10h offset Bit 31 30 29 28 27 26 25 24 23...

Page 720: ...0000 Accesses via the IOPORT interface occur in parallel with any instruction fetches and will therefore complete in a single cycle This aliased Fast GPIO memory map is called FGPIO Any read or write...

Page 721: ...et Output Register FGPIOC_PSOR 32 W always reads 0 0000_0000h 35 4 2 722 F800_0088 Port Clear Output Register FGPIOC_PCOR 32 W always reads 0 0000_0000h 35 4 3 723 F800_008C Port Toggle Output Registe...

Page 722: ...t Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R PDO W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FGPIOx_PDOR field descriptions...

Page 723: ...d Description PTCO Port Clear Output Writing to this register will update the contents of the corresponding bit in the Port Data Output Register PDOR as follows 0 Corresponding bit in PDORn does not c...

Page 724: ...abled then the corresponding bit in PDIR does not update 0 Pin logic level is logic 0 or is not configured for use by digital function 1 Pin logic level is logic 1 35 4 6 Port Data Direction Register...

Page 725: ...for the GPIO function The following table depicts the conditions for a pin to be configured as input output If Then A pin is configured for the GPIO function and the corresponding port data direction...

Page 726: ...ur in parallel with any instruction fetches and will therefore complete in a single cycle If the DMA attempts to access the GPIO registers on the same cycle as an IOPORT access then the DMA access wil...

Page 727: ...indicated in following table For details regarding a specific ADC channel available on a particular package refer to the signal multiplexing chapter of this MCU Table 36 1 ADC external channels per p...

Page 728: ..._SE9 01010 AD10 PTC2 ADC0_SE10 01011 AD11 PTC3 ADC0_SE11 01100 AD12 PTC14 ADC0_SE12 01101 AD13 PTC15 ADC0_SE13 01110 AD14 PTC16 ADC0_SE14 01111 AD15 PTC17 ADC0_SE15 10000 AD16 Reserved 10001 AD17 Rese...

Page 729: ...01001 AD9 PTB14 ADC1_SE9 01010 AD10 PTE2 ADC1_SE10 01011 AD11 PTE6 ADC1_SE11 01100 AD12 Reserved 01101 AD13 Reserved 01110 AD14 Reserved 01111 AD15 Reserved 10000 AD16 Reserved 10001 AD17 Reserved 100...

Page 730: ...CDIV2_CLK FIRCDIV2_CLK ADCx module BUS_CLK Peripheral Interface Clock PCC_ADCx PCS 00 01 10 11 see PCC chapter for detailed setting Registers NA ALTCLK1 ALTCLK2 ALTCLK3 ALTCLK4 NA NA NOTE ALTCLK2 4 ar...

Page 731: ...ADC0_SE4 and ADC1_SE14 channels as an example these two channels can work independently but they can also be hardware interleaved as shown in the following diagram In the hardware interleaved mode a s...

Page 732: ...s are interleaved on PTB14 pin Figure 36 1 ADC0 and ADC1 hardware interleaved channels integration 36 1 4 2 ADC Reference Options The ADC supports the following references VREFH VREFL connected as the...

Page 733: ...gger schemes by controlling SIM_ADCOPT ADCxSWPRETRG registers Besides the hardware triggers through ADHWT the ADC module itself also supports software trigger mode by setting SC2 ADTRG 0 Following a w...

Page 734: ...ADC triggering source scheme When ADCxTRGSEL 0 the ADC pre trigger is coming from PDB directly When ADCxTRGSEL 1 the ADC pre trigger is coming from TRGMUX e g LPIT ADHWT cocoA cocoB SIM_ADCOPT ADC0TR...

Page 735: ...X triggering scheme TRGMUX supports many trigger sources here we take LPIT as an example typical but the trigger source can also be others which mentioned above LPIT supports up to 4 channels each cha...

Page 736: ...de only support SC1A and data register A Configure SC2 ADTRG 1 ADC is in hardware triggering mode By setting SIM_ADCOPT ADCxSWPRETRG the pre trigger for ADC is selected The software trigger trough TRG...

Page 737: ...s Operation in low power modes for lower noise Selectable hardware conversion trigger with hardware channel select Automatic compare with interrupt for less than greater than or equal to within range...

Page 738: ...LSMP ADLSTS Control sequencer Clock divide ALTCLK2 SAR converter Offset subtractor Averager Formatting Compare logic initialize sample convert transfer abort V REFL BNGP VREFH VREFL ALTCLK3 TEMPSENSE...

Page 739: ...same voltage potential as VSS 36 3 3 Voltage Reference Select VREFSH and VREFSL are the high and low reference voltages for the ADC module The ADC can be configured to accept one of the voltage refere...

Page 740: ...4 1 742 4002_7040 ADC Configuration Register 1 ADC1_CFG1 32 R W 0000_0000h 36 4 2 745 4002_7044 ADC Configuration Register 2 ADC1_CFG2 32 R W 0000_000Ch 36 4 3 746 4002_7048 ADC Data Result Registers...

Page 741: ...h 36 4 24 761 4002_70DC ADC Plus Side General Calibration Offset Value Register 1 ADC1_CLP1_OFS 32 R W 0000_0000h 36 4 25 761 4002_70E0 ADC Plus Side General Calibration Offset Value Register 0 ADC1_C...

Page 742: ...W See section 36 4 19 758 4003_B0C8 ADC Plus Side General Calibration Value Register X ADC0_CLPX 32 R W See section 36 4 20 758 4003_B0CC ADC Plus Side General Calibration Value Register 9 ADC0_CLP9...

Page 743: ...rs are used for software trigger operation and therefore writes to the SC1B SC1n registers do not initiate a new conversion Address Base address 0h offset 4d i where i 0d to 1d Bit 31 30 29 28 27 26 2...

Page 744: ...s NOTE Some of the input channel options in the bitfield setting descriptions might not be available for your chip For the actual ADC channel assignments for your device see the chip specific informat...

Page 745: ...100 Internal channel 3 is selected as input 11101 VREFSH is selected as input Voltage reference selected is determined by SC2 REFSEL 11110 VREFSL is selected as input Voltage reference selected is det...

Page 746: ...ADC resolution 00 8 bit conversion 01 12 bit conversion 10 10 bit conversion 11 Reserved ADICLK Input Clock Select Selects the input clock source to generate the internal clock ADCK See the clock dist...

Page 747: ...er there is a corresponding data result register Unused bits in Rn are cleared The following table describes the behavior of the data result registers in the different modes of operation Table 36 5 Da...

Page 748: ...ed only when the compare range function is enabled that is SC2 ACREN 1 Address Base address 88h offset 4d i where i 0d to 1d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7...

Page 749: ...served This field is reserved This read only field is reserved and always has the value 0 15 Reserved This field is reserved This read only field is reserved and always has the value 0 14 13 Reserved...

Page 750: ...ee Table 36 7 Compare modes for further details 3 ACREN Compare Function Range Enable Configures the compare function to check if the conversion result of the input being monitored is either between o...

Page 751: ...writes to the ADC registers or the results will be invalid Setting CAL will abort any current conversion NOTE For calibration it is mandatory to use averaging and average number 32 NOTE If several ADC...

Page 752: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 ADCx_BASE_OFS field descriptions Field Description 31 8 Reserved This field is reserved This read only field is reserved and always has the value...

Page 753: ...value 0 OFS Offset Error Correction Value 36 4 10 USER Offset Correction Register ADCx_USR_OFS The ADC USER Offset Correction Register USR_OFS contains the user defined offset error correction value u...

Page 754: ...t error correction value 36 4 12 ADC Y Offset Correction Register ADCx_YOFS The ADC Y Offset Correction Register YOFS contains the Y offset used in the conversion result error correction algorithm Add...

Page 755: ...ddress Base address B0h offset Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 UG W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0...

Page 756: ...on Value 36 4 16 ADC Plus Side General Calibration Value Register 3 ADCx_CLP3 Address Base address B8h offset Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...

Page 757: ...s the value 0 CLP2 Calibration Value 36 4 18 ADC Plus Side General Calibration Value Register 1 ADCx_CLP1 Address Base address C0h offset Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 1...

Page 758: ...CLP0 Calibration Value 36 4 20 ADC Plus Side General Calibration Value Register X ADCx_CLPX Address Base address C8h offset Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 W Reset 0 0 0 0 0 0...

Page 759: ...0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 Reserved CLP9 W Reset 0 0 0 0 0 0 0 0 0 Notes CLP9 field Reset values are loaded out of IFR ADCx_CLP9 field descriptions Field Des...

Page 760: ...t Capacitor offset correction value 36 4 23 ADC Plus Side General Calibration Offset Value Register 3 ADCx_CLP3_OFS Address Base address D4h offset Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16...

Page 761: ...ffset Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 CLP1_OFS W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADCx_CLP1_OFS field...

Page 762: ...rved This field is reserved This read only field is reserved and always has the value 0 CLPX_OFS CLPX Offset Capacitor offset correction value 36 4 28 ADC Plus Side General Calibration Offset Value Re...

Page 763: ...has been enabled or when SC1n AIEN 1 The ADC module has the capability of automatically comparing the result of a conversion with the contents of the CV1 and CV2 registers The compare function is enab...

Page 764: ...cted using SC2 REFSEL The alternate VALTH voltage reference may select additional external pin or internal source depending on MCU configuration See the chip configuration information for the voltage...

Page 765: ...ion When the conversion is completed the result is placed in the Rn registers associated with the ADHWTSn received For example ADHWTSA active selects RA register ADHWTSn active selects Rn register The...

Page 766: ...ion In software triggered operation that is when SC2 ADTRG 0 continuous conversions begin after SC1A is written and continue until aborted In hardware triggered operation that is when SC2 ADTRG 1 and...

Page 767: ...rolling a conversion aborts the current conversion In Software Trigger mode when SC2 ADTRG 0 a write to SC1A initiates a new conversion if SC1A ADCH is equal to a value other than all 1s Writing to an...

Page 768: ...completion of the conversion algorithm The maximum total conversion time is determined by the clock source chosen and the divide ratio selected The clock source is selectable by CFG1 ADICLK and the di...

Page 769: ...ult falls within or outside a range determined by two compare values The compare mode is determined by SC2 ACFGT SC2 ACREN and the values in the Compare Value registers CV1 and CV2 After the input is...

Page 770: ...gister Rn If the hardware averaging function is enabled the compare function compares the averaged result to the compare values The same compare function definitions apply An ADC interrupt is generate...

Page 771: ...VDDA and VSSA Suggested cap sizes 1 nF 100 nF 10 F Place caps on PCB as close as possible to the device pins VDDA and VSSA Routing of VDDA VSSA VREFH and VREFL on PCB Low impedance between the bypass...

Page 772: ...e from which recovery is fast because the clock sources remain active If a conversion is in progress when the MCU enters Wait mode it continues until completion Conversions can be initiated while the...

Page 773: ...completed conversion that occurred during Normal Stop mode If the hardware averaging function is enabled SC1n COCO will set and generate an interrupt if enabled when the selected number of conversion...

Page 774: ...LSMP 1 Configures for long sample time Bit 3 2 MODE 10 Selects the single ended 10 bit conversion Bit 1 0 ADICLK 00 Selects the bus clock ADC_SC2 0x00 Bit 7 ADACT 0 Flag indicates if a conversion is i...

Page 775: ...than specified accuracy In order to calibrate ADC correctly the following steps have to be done On startup wait until reference voltage VREFH VREFL has stabilized use 3 bypass capacitance in the range...

Page 776: ...6 5 DMA Support on ADC Applications may require continuous sampling of the ADC 4K samples sec that may have considerable load on the CPU Though using PDB to trigger ADC may reduce some CPU load the AD...

Page 777: ...and trigger output of PDB to ADC Every time when one PDB pre trigger and trigger output starts an ADC conversion an internal lock associated with the corresponding pre trigger is activated This lock...

Page 778: ...ontains a self calibration function that is required to achieve the specified accuracy Calibration must be run or valid calibration values written after any reset and before a conversion is initiated...

Page 779: ...upports output to pad through a buffer 2 In summary this allow the CMP to operate independently in STOP and VLPS mode whilst being triggered periodically to sample up to 6 inputs Only if an input chan...

Page 780: ...r 8 bit DAC0 supports output to pad through a buffer 8 bit DAC1 output could be used as ADC0 reference input ANL0 ADC0 DAC_OUT 8 bit DAC0 1 0 ANL1 8 bit DAC1 1 0 CMP1 CMP0 Buffer 37 1 2 CMP Clocking I...

Page 781: ...module BUS_CLK Peripheral Interface Clock Registers Main Clock internal 37 1 3 Inter connectivity Information The CMP inter connectivity is shown in following diagram Chapter 37 Comparator CMP Kineti...

Page 782: ...The CMP could get external reference through the tightly integrated 8 bit DAC sub block The 8 bit DAC sub block supports selection of two references For this device the references are connected as fol...

Page 783: ...CMP The trigger event will initiate a compare sequence that must first enable the CMP and DAC prior to performing a CMP operation and capturing the output In this device control for this two staged s...

Page 784: ...gital signal input selects the output voltage level which varies from Vin to Vin 256 Vin can be selected from two voltage sources Vin1 and Vin2 The DAC from a comparator is available as an on chip int...

Page 785: ...ailable on this MCU The window and filter functions are not available in STOP modes The comparator can be triggered by other peripherals to work for only a small fraction of the time 37 3 2 8 bit DAC...

Page 786: ...L 2 0 CMP CMP MUX DAC output DACEN Vin1 Vin2 Window and filter control CMPO Reference Input 0 Reference Input 1 Reference Input 2 Reference Input 3 Reference Input 4 Reference Input 5 Reference Input...

Page 787: ...PO To other SOC functions Internal bus Figure 37 2 Comparator module block diagram In the CMP block diagram The Window Control block is bypassed when C0 WE 0 If C0 WE 1 the comparator output is sample...

Page 788: ...section provides the comparator pin descriptions The external inputs IN 7 0 are muxed by CMP_C1 PSEL and CMP_C1 MSEL beforehand and multiplexed output will then go to the second stage of multiplex wi...

Page 789: ...simplest case only one sample must agree In this case the filter acts as a simple sampler The external sample input is enabled using C0 SE When set the output of the comparator is sampled only on risi...

Page 790: ...al determined by C0 FPR to generate COUT See the Windowed Resampled mode 6 7 1 1 0 0x01 0x01 0xFF Windowed Filtered mode Comparator output is sampled on every rising bus clock edge when SAMPLE 1 to ge...

Page 791: ...in Continuous mode NOTE See the chip configuration section for the source of sample window input The analog comparator block is powered and active CMPO may be optionally inverted but is not subject t...

Page 792: ...s powered and active The path from analog inputs to COUTA is combinational unclocked Windowing control is completely bypassed COUTA is sampled whenever a rising edge is detected on the filter block cl...

Page 793: ...ure illustrates comparator operation in this mode assuming the polarity select is set to non inverting state Sample Point CMPO COUT Figure 37 7 Sampled Non Filtered Mode Timing Diagram 37 7 4 Sampled...

Page 794: ...1 WE 0 SE 1 CGMUX COS 1 0 FILT_PER bus clock COS IER F CFR F WINDOW SAMPLE 1 0 EN PMODE HYSTCTR 1 0 divided bus clock CMPO 0x01 Internal bus Polarity select Window control Filter block Interrupt cont...

Page 795: ...w C0 FILTER_CNT 1 which activates filter operation 37 7 5 Windowed mode s 5A 5B The following figure illustrates comparator operation in the Windowed mode ignoring latency of the analog comparator pol...

Page 796: ...ndow control Filter block Interrupt control divided bus clock Clock prescaler CMPO Internal bus To other SOC functions Figure 37 11 Windowed mode For control configurations which result in disabling t...

Page 797: ...n the sampling rate and window placement COUT may not see zero crossing events detected by the analog comparator Sampling period and or window placement must be carefully considered for a given applic...

Page 798: ...clocked by the bus clock whenever WINDOW 1 The last latched value is held when WINDOW 0 IRQ EN PMODE HYSCTR 1 0 INP INM FILTER_CNT INV COUT COUT OPE SE CMPO to PAD COUTA 0 1 WE 1 0 SE 0 CGMUX COS 0 1...

Page 799: ...4007_3004 CMP Control Register 1 CMP0_C1 32 R W 0000_0000h 37 8 2 803 4007_3008 CMP Control Register 2 CMP0_C2 32 R W 0000_0000h 37 8 3 806 4007_4000 CMP Control Register 0 CMP1_C0 32 R W 0000_0000h 3...

Page 800: ...EN DMA Enable Enables the DMA transfer triggered from the CMP module When this field is set a DMA request is asserted when CFR or CFF is set 0 DMA is disabled 1 DMA is enabled 29 Reserved This field i...

Page 801: ...omparator output filter when C0 SE 0 Setting FPR to 0x0 disables the filter Filter programming and latency details are provided in the CMP functional description This field has no effect when C0 SE 1...

Page 802: ...ower 0 Analog Comparator is disabled 1 Analog Comparator is enabled 7 Reserved This field is reserved This read only field is reserved and always has the value 0 6 4 FILTER_CNT Filter Sample Count Thi...

Page 803: ...ally 01 The hard block output has level 1 hysteresis internally 10 The hard block output has level 2 hysteresis internally 11 The hard block output has level 3 hysteresis internally 37 8 2 CMP Control...

Page 804: ...from the analog 8 1 mux 10 Reserved 11 Reserved 23 CHN7 Channel 7 input enable Channel 7 of the input enable for the round robin checker If CHN7 is set then the corresponding channel to the non fixed...

Page 805: ...HN0 is set then the corresponding channel to the non fixed mux port is enabled to check its voltage value in the round robin mode If the same channel is selected as the reference voltage this bit has...

Page 806: ...IN3 100 IN4 101 IN5 110 IN6 111 IN7 VOSEL DAC Output Voltage Select This bit selects an output voltage from one of 256 distinct levels DACO Vin 256 VOSEL 7 0 1 so the DACO range is from Vin 256 to Vin...

Page 807: ...XMXCH Fixed channel selection This field indicates which channel in the mux port is fixed in a given round robin mode 000 Channel 0 is selected as the fixed reference input for the fixed mux port 001...

Page 808: ...cles after the next cycle of the round robin clock 11 The sampling takes place 3 round robin clock cycles after the next cycle of the round robin clock 13 8 INITMOD Comparator and DAC initialization d...

Page 809: ...he low pass filter operates on the unfiltered and unsynchronized and optionally inverted comparator output COUTA and generates the filtered and synchronized output COUT Both COUTA and COUT can be conf...

Page 810: ...samples agree that the output value has changed 37 9 2 2 Latency issues The value of C0 FPR or SAMPLE period must be set such that the sampling period is just longer than the period of the expected no...

Page 811: ...e analog component plus the polarity select logic TSAMPLE is the clock period of the external sample clock Tper is the period of the bus clock 37 10 Interrupts The CMP module is capable of generating...

Page 812: ...nother DMA request 37 12 DAC functional description This section provides DAC functional description 37 12 1 Digital to analog converter block diagram The following figure shows the block diagram of t...

Page 813: ...ed to support the trigger mode operation which is enabled when the MCU enters STOP modes with C2 RRE and C0 EN are set With this mode enabled the trigger events that include the operation clock and a...

Page 814: ...ock It is suggested to configure the comparator in low power comparison mode as well In programming the C2 INITMOD registers the INITMOD round robin clock period must be longer than the initialization...

Page 815: ...wing table shows the channel decoding in both functional mode and trigger mode Other cases not listed in the table are illegal Table 37 6 CMP channel decoding in functional mode and trigger mode Mode...

Page 816: ...gnal function It is a commonly used in electronics application especially for systems which send digital data over AC circuits When in some cases the Zero point could be other voltage than actual 0 V...

Page 817: ...mode and disable the sample mode CMPx_C0 CMPx_C0 CMP_C0_SE_MASK CMP_C0_WE_MASK Then enable the window s generator to produce the WINDOW signal of related module For detailed information about CMP s wi...

Page 818: ...e Sample channels comparison result Channels result Channel 1 Channel 1 2 Channel 1 Channel 2 Channel 3 Channel 1 2 3 Initialization delay Possible interrupt MCU Wake Up Detect comparison result chang...

Page 819: ...XMXCH 0 CMP_C2_NSAM 0 CMP_C2_INITMOD 0 CMP_C2_RRE_MASK CMP_C2_RRIE_MASK Set all the pre state of round robin checker channel0 7 to 1 CMPx C2 CMPx C2 CMP_C2_ACOn_MASK CMP_C2_CHnF_MASK 0xFF CMP_C2_ACOn_...

Page 820: ...Usage Guide Kinetis KE1xZ256 Sub Family Reference Manual Rev 3 07 2018 820 NXP Semiconductors...

Page 821: ...er 2 Each PDB channel supports one hardware trigger for one ADC Number of pre triggers for ADC channel select per PDB channel 2 PDB pre triggers are used to select ADC channel for the ADC hardware tri...

Page 822: ..._PULSE0 PDB0_PULSE1 PDB0_EXTRG ADHWTS A ADHWTS B ch0_trigger ch0_pretrig0 ch0_pretrig1 S H Conversion ADC0_CHx ADHWT ADHWTS A ADHWTS B ch1_trigger ch1_pretrig0 ch1_pretrig1 S H Conversion ADC1_CHx ADH...

Page 823: ...ity PDB0 channel 0 ADC0 hardware trigger PDB0 channel 1 ADC1 hardware trigger PDB0 pulse out 0 Pulse out 0 connects to TRGMUX PDB0 pulse out 1 Pulse out 1 connects to TRGMUX Back to back acknowledge c...

Page 824: ...onfigurable PDB channels for ADC hardware trigger One PDB channel is associated with one ADC One trigger output for ADC hardware trigger and up to 8 pre trigger outputs for ADC trigger select per PDB...

Page 825: ...nnel number valid from 0 to N 1 M Total available pre trigger per PDB channel m Pre trigger number valid from 0 to M 1 Y Total number of Pulse Out s y Pulse Out number valid value is from 0 to Y 1 NOT...

Page 826: ...m MULT Ack m Pre trigger m Trigger In 0 Sequence Error Detection ERR M 1 0 PRESCALER PDB Counter PDBCNT PDBMOD Control Logic CONT Trigger In 1 Trigger In 14 SWTRIG TRIGSEL PDBIDLY PDB interrupt TOEx P...

Page 827: ...he count reaches the value specified in the modulus register and the counting is restarted This enables a continuous stream of pre triggers trigger outputs as a result of a single trigger input event...

Page 828: ...Y0 32 R W 0000_0000h 38 4 7 835 4003_601C Channel n Delay 1 register PDB0_CH0DLY1 32 R W 0000_0000h 38 4 8 836 4003_6038 Channel n Control register 1 PDB0_CH1C1 32 R W 0000_0000h 38 4 5 833 4003_603C...

Page 829: ...their buffers immediately after 1 is written to LDOK 01 The internal registers are loaded with the values from their buffers when the PDB counter CNT MOD 1 CNT delay elapsed after 1 is written to LDOK...

Page 830: ...100 Counting uses the peripheral clock divided by 16 x MULT the multiplication factor 101 Counting uses the peripheral clock divided by 32 x MULT the multiplication factor 110 Counting uses the periph...

Page 831: ...uous mode 0 PDB operation in One Shot mode 1 PDB operation in Continuous mode 0 LDOK Load OK Writing 1 to LDOK bit updates the MOD IDLY CHnDLYm and POyDLY registers with the values previously written...

Page 832: ...d This field is reserved This read only field is reserved and always has the value 0 MOD PDB Modulus Specifies the period of the counter When the counter reaches this value it will be reset back to ze...

Page 833: ...ions Field Description 31 16 Reserved This field is reserved This read only field is reserved and always has the value 0 IDLY PDB Interrupt Delay Specifies the delay value to schedule the PDB interrup...

Page 834: ...ing edge is detected on selected trigger input source or software trigger is selected and SWTRIG is written with 1 1 PDB channel s corresponding pre trigger asserts when the counter reaches the channe...

Page 835: ...es written to the register are written to its internal buffer instead in other words the internal device bus does not write directly to this register The value in this register s internal buffer is lo...

Page 836: ...alue 0 DLY PDB Channel Delay These bits specify the delay value for the channel s corresponding pre trigger The pre trigger asserts when the counter is equal to DLY Reading these bits returns the valu...

Page 837: ...r that is effective for the current PDB cycle DLY2 PDB Pulse Out Delay 2 Specifies the delay 2 value for the PDB Pulse Out Pulse Out goes low when the PDB counter is equal to the DLY2 Reading this fie...

Page 838: ...eforms shown in the following diagram show the pre trigger and trigger outputs of PDB channel n The delays can be independently set using the channel delay registers CHnDLYm and the pre triggers can b...

Page 839: ...upt is generated A sequence error typically happens because the delay m is set too short and the pre trigger m asserts before the previously triggered ADC conversion finishes If the pre trigger delay...

Page 840: ...puts of configurable width When the PDB counter reaches the value set in POyDLY DLY1 then the Pulse Out goes high When the PDB counter reaches POyDLY DLY2 then it goes low POyDLY DLY2 can be set eithe...

Page 841: ...se Out is generated 38 5 4 Updating the delay registers The following registers control the timing of the PDB operation and in some of the applications they may need to become effective at the same ti...

Page 842: ...10 A trigger input event is detected after 1 is written to SC LDOK 11 Either the PDB counter reaches PDB_MOD MOD 1 value or a trigger input event is detected after 1 is written to SC LDOK After 1 is w...

Page 843: ...upts Table 38 6 PDB interrupt summary Interrupt Flags Enable bit PDB Interrupt SC PDBIF SC PDBIE 1 and SC DMAEN 0 PDB Sequence Error Interrupt CHnS ERRm SC PDBEIE 1 38 5 6 DMA If SC DMAEN is set PDB c...

Page 844: ...values if prescaler is set to 4 then the only values of total peripheral clocks that can be decoded as detected are mod 4 and so forth If the applications need a really long delay value and use a pres...

Page 845: ...channels Features usage FTM0 8 FTM enhanced features GTB_EN FTM1 4 FTM enhanced features GTB_EN Qua drature Decoder FTM2 4 FTM enhanced features GTB_EN Qua drature Decoder Compared with the FTM0 conf...

Page 846: ...quency clock must not exceed 1 2 of the FTM system clock frequency SYS_CLK NOTE The external clock are synchronized by FTM system clock SYS_CLK Therefore to meet Nyquist criteria considering also jitt...

Page 847: ...FTM Fault Detection Inputs for details 39 1 3 1 FTM Fault Detection Inputs The following fault detection input options for the FTM modules are selected via the SIM_FTMOPT0 register The external pin o...

Page 848: ...TM0 Fault Detection Inputs Trigger source_0 TRGMUX Trigger source_1 Trigger source_n FTMx FTMx_FLT2 FTMx_FLT3 FAULT0 FAULT1 FAULT2 FAULT3 Figure 39 2 FTM1 FTM2 Fault Detection Inputs 39 1 3 2 FTM Hard...

Page 849: ...be from many other modules via TRGMUX like LPIT Low Power Timer CMP etc It also supports FlexTimer s self trigger outputs ex counter initlization trigger init_trig and channel match trigger ext_trig...

Page 850: ...ific FTM information to see how many channels are supported for each module instance For example if a module instance supports only six channels references to channel numbers 6 and 7 do not apply for...

Page 851: ...e options available for used FlexTimer configuration More than one FlexTimers may be synchronized to provide a larger timer with their counters incrementing in unison assuming the initialization the i...

Page 852: ...h complementary outputs or independent channels with independent outputs The deadtime insertion is available for each complementary pair Generation of match triggers Software control of PWM outputs Up...

Page 853: ...ed to produce a real time reference or provide the interrupt sources needed to wake the chip from Wait mode the power can then be saved by disabling FTM functions before entering Wait mode 39 2 4 Bloc...

Page 854: ...ol deadtime insertion output mask fault control and polarity control output modes logic input capture mode prescaler 1 2 4 8 16 32 64 or 128 DECAPEN COMBINE0 CPWMS MS0B MS0A ELS0B ELS0A MS1B MS1A ELS1...

Page 855: ...ch FAULTj input may affect all channels selectively since FAULTM 1 0 and FAULTEN control bits are defined for each pair of channels Because there are several FAULTj inputs maximum of 4 for the FTM mod...

Page 856: ...nnel n Value FTM0_C0V 32 R W 0000_0000h 39 4 7 869 4003_8014 Channel n Status And Control FTM0_C1SC 32 R W 0000_0000h 39 4 6 867 4003_8018 Channel n Value FTM0_C1V 32 R W 0000_0000h 39 4 7 869 4003_80...

Page 857: ...0000_0000h 39 4 18 890 4003_8078 Input Capture Filter Control FTM0_FILTER 32 R W 0000_0000h 39 4 19 892 4003_807C Fault Control FTM0_FLTCTRL 32 R W 0000_0000h 39 4 20 893 4003_8080 Quadrature Decoder...

Page 858: ...9 4003_901C Channel n Status And Control FTM1_C2SC 32 R W 0000_0000h 39 4 6 867 4003_9020 Channel n Value FTM1_C2V 32 R W 0000_0000h 39 4 7 869 4003_9024 Channel n Status And Control FTM1_C3SC 32 R W...

Page 859: ...1_FLTPOL 32 R W 0000_0000h 39 4 23 899 4003_908C Synchronization Configuration FTM1_SYNCONF 32 R W 0000_0000h 39 4 24 900 4003_9090 FTM Inverting Control FTM1_INVCTRL 32 R W 0000_0000h 39 4 25 902 400...

Page 860: ...FTM2_C4SC 32 R W 0000_0000h 39 4 6 867 4003_A030 Channel n Value FTM2_C4V 32 R W 0000_0000h 39 4 7 869 4003_A034 Channel n Status And Control FTM2_C5SC 32 R W 0000_0000h 39 4 6 867 4003_A038 Channel n...

Page 861: ...39 4 26 903 4003_A098 FTM PWM Load FTM2_PWMLOAD 32 R W 0000_0000h 39 4 27 906 4003_A09C Half Cycle Register FTM2_HCR 32 R W 0000_0000h 39 4 28 908 4003_A200 Mirror of Modulo Value FTM2_MOD_MIRROR 32...

Page 862: ...MEN6 PWMEN5 PWMEN4 PWMEN3 PWMEN2 PWMEN1 PWMEN0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 TOF TOIE RF RIE CPWMS CLKS PS W 0 0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 863: ...led 1 Channel output port is enabled 19 PWMEN3 Channel 3 PWM enable bit This bit enables the PWM channel output This bit should be set to 0 output disabled when an input mode is used 0 Channel output...

Page 864: ...gister The RF bit is cleared by reading the SC register while RF is set and then writing a 0 to RF bit Writing 1 to RF has no effect If another reload point is reached between the read and write opera...

Page 865: ...s the counter with its initial value CNTIN Address Base address 4h offset Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 COUNT W Reset 0 0 0 0 0 0 0 0 0...

Page 866: ...fusion about when the first counter overflow will occur Address Base address 8h offset Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 MOD W Reset 0 0 0 0...

Page 867: ...CnSC field descriptions Field Description 31 11 Reserved This field is reserved This read only field is reserved and always has the value 0 10 Reserved This field is reserved This read only field is r...

Page 868: ...then writing a 0 to the CHF bit Writing a 1 to CHF has no effect If another event occurs between the read and write operations the write operation has no effect therefore CHF remains set indicating an...

Page 869: ...gnored In output modes writes to the CnV register are done on its write buffer The CnV register is updated with its write buffer value according to Registers updated from write buffers If FTMEN 0 a wr...

Page 870: ...field is reserved and always has the value 0 INIT Initial Value Of The FTM Counter 39 4 9 Capture And Compare Status FTMx_STATUS The STATUS register contains a copy of the status flag CHF bit in CnSC...

Page 871: ...s reserved and always has the value 0 7 CH7F Channel 7 Flag See the register description 0 No channel event has occurred 1 A channel event has occurred 6 CH6F Channel 6 Flag See the register descripti...

Page 872: ...nel 0 Flag See the register description 0 No channel event has occurred 1 A channel event has occurred 39 4 10 Features Mode Selection FTMx_MODE This register contains the global enable bit for FTM sp...

Page 873: ...TEST Capture Test Mode Enable Enables the capture test mode This field is write protected It can be written only when MODE WPDIS 1 0 Capture test mode is disabled 1 Capture test mode is enabled 3 PWMS...

Page 874: ...of MOD CV and OUTMASK registers with the value of their write buffer and the FTM counter initialization NOTE The software trigger SWSYNC bit and hardware triggers TRIG0 TRIG1 and TRIG2 bits have a pot...

Page 875: ...les hardware trigger 2 to the PWM synchronization Hardware trigger 2 happens when a rising edge is detected at the trigger 2 input signal 0 Trigger is disabled 1 Trigger is enabled 5 TRIG1 PWM Synchro...

Page 876: ...its maximum value MOD register 0 The maximum loading point is disabled 1 The maximum loading point is enabled 0 CNTMIN Minimum Loading Point Enable Selects the minimum loading point to PWM synchroniz...

Page 877: ...n occurs 0 The initialization value is 0 1 The initialization value is 1 3 CH3OI Channel 3 Output Initialization Value Selects the value that is forced into the channel output when the initialization...

Page 878: ...6 5 4 3 2 1 0 R 0 CH7OM CH6OM CH5OM CH4OM CH3OM CH2OM CH1OM CH0OM W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FTMx_OUTMASK field descriptions Field Description 31 8 Reserved This field is reserved This r...

Page 879: ...is forced to its inactive state 2 CH2OM Channel 2 Output Mask Defines if the channel output is masked or unmasked 0 Channel output is not masked It continues to operate normally 1 Channel output is ma...

Page 880: ...Enables the fault control in channels n and n 1 This field is write protected It can be written only when MODE WPDIS 1 0 The fault control in this pair of channels is disabled 1 The fault control in t...

Page 881: ...s write protected It can be written only when MODE WPDIS 1 23 Reserved This field is reserved This read only field is reserved and always has the value 0 22 FAULTEN2 Fault Control Enable For n 4 Enabl...

Page 882: ...TEN1 Fault Control Enable For n 2 Enables the fault control in channels n and n 1 This field is write protected It can be written only when MODE WPDIS 1 0 The fault control in this pair of channels is...

Page 883: ...ted It can be written only when MODE WPDIS 1 0 The fault control in this pair of channels is disabled 1 The fault control in this pair of channels is enabled 5 SYNCEN0 Synchronization Enable For n 0 E...

Page 884: ...e for all pair of channels Address Base address 68h offset Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 0 0 DTPS DTVAL W Reset 0 0 0 0 0 0 0 0 0 0 0 0...

Page 885: ...tion of a trigger when the FTM counter is equal to its initial value Selects which channels are used in the generation of the channel triggers Several channels can be selected to generate multiple tri...

Page 886: ...ed 1 The generation of the channel trigger is enabled 7 TRIGF Channel Trigger Flag Set by hardware when a channel trigger is generated Clear TRIGF by reading EXTTRIG while TRIGF is set and then writin...

Page 887: ...equal to the CnV register 0 The generation of the channel trigger is disabled 1 The generation of the channel trigger is enabled 1 CH3TRIG Channel 3 Trigger Enable Enables the generation of the channe...

Page 888: ...tten only when MODE WPDIS 1 0 The channel polarity is active high 1 The channel polarity is active low 5 POL5 Channel 5 Polarity Defines the polarity of the channel output This field is write protecte...

Page 889: ...the channel output This field is write protected It can be written only when MODE WPDIS 1 0 The channel polarity is active high 1 The channel polarity is active low 0 POL0 Channel 0 Polarity Defines...

Page 890: ...Detection Flag Represents the logic OR of the individual FAULTFj bits where j 3 2 1 0 Clear FAULTF by reading the FMS register while FAULTF is set and then writing a 0 to FAULTF while there is no exi...

Page 891: ...ins set after the clearing sequence is completed for the earlier fault condition 0 No fault condition was detected at the fault input 1 A fault condition was detected at the fault input 2 FAULTF2 Faul...

Page 892: ...after the clearing sequence is completed for the earlier fault condition 0 No fault condition was detected at the fault input 1 A fault condition was detected at the fault input 39 4 19 Input Capture...

Page 893: ...tput state when a fault event happens Address Base address 7Ch offset Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4...

Page 894: ...lter Enable Enables the filter for the fault input This field is write protected It can be written only when MODE WPDIS 1 0 Fault input filter is disabled 1 Fault input filter is enabled 5 FFLTR1EN Fa...

Page 895: ...tected It can be written only when MODE WPDIS 1 0 Fault input is disabled 1 Fault input is enabled 0 FAULT0EN Fault Input 0 Enable Enables the fault input This field is write protected It can be writt...

Page 896: ...0 0 0 FTMx_QDCTRL field descriptions Field Description 31 8 Reserved This field is reserved This read only field is reserved and always has the value 0 7 PHAFLTREN Phase A Input Filter Enable Enables...

Page 897: ...ed in the Quadrature Decoder mode 0 Phase A and phase B encoding mode 1 Count and direction encoding mode 2 QUADIR FTM Counter Direction In Quadrature Decoder Mode Indicates the counting direction 0 C...

Page 898: ...ys has the value 0 11 ITRIGR Initialization trigger on Reload Point This bit controls whether an initialization trigger is generated when a reload point configured by PWMLOAD register is reached consi...

Page 899: ...a maximum of 32 39 4 23 FTM Fault Input Polarity FTMx_FLTPOL This register defines the fault inputs polarity Address Base address 88h offset Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 W R...

Page 900: ...put indicates a fault 0 FLT0POL Fault Input 0 Polarity Defines the polarity of the fault input This field is write protected It can be written only when MODE WPDIS 1 0 The fault input polarity is acti...

Page 901: ...on 15 13 Reserved This field is reserved This read only field is reserved and always has the value 0 12 SWSOC Software output control synchronization is activated by the software trigger 0 The softwar...

Page 902: ...ffer value at all rising edges of FTM input clock 1 CNTIN register is updated with its buffer value by the PWM synchronization 1 Reserved This field is reserved This read only field is reserved and al...

Page 903: ...0 Inverting is disabled 1 Inverting is enabled 0 INV0EN Pair Channels 0 Inverting Enable 0 Inverting is disabled 1 Inverting is enabled 39 4 26 FTM Software Output Control FTMx_SWOCTRL This register e...

Page 904: ...are Output Control Value 0 The software output control forces 0 to the channel output 1 The software output control forces 1 to the channel output 12 CH4OCV Channel 4 Software Output Control Value 0 T...

Page 905: ...ol Enable 0 The channel output is not affected by software output control 1 The channel output is affected by software output control 3 CH3OC Channel 3 Software Output Control Enable 0 The channel out...

Page 906: ...L CH7SEL CH6SEL CH5SEL CH4SEL CH3SEL CH2SEL CH1SEL CH0SEL W GLDOK Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FTMx_PWMLOAD field descriptions Field Description 31 12 Reserved This field is reserved This rea...

Page 907: ...is enabled and it is considered as a reload opportunity 7 CH7SEL Channel 7 Select 0 Channel match is not included as a reload opportunity 1 Channel match is included as a reload opportunity 6 CH6SEL C...

Page 908: ...s 9Ch offset Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 HCVAL W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FTMx_HCR field...

Page 909: ...16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R VAL FRACVAL 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FTMx_CnV_MIRROR field descriptions Field Description 31 16 VAL Mirror...

Page 910: ...he FTM counter After any chip reset CLKS 1 0 0 0 so no clock source is selected The CLKS 1 0 bits may be read or written at any time Disabling the FTM counter by writing 0 0 to the CLKS 1 0 bits does...

Page 911: ...example of the prescaler counter and FTM counter FTM counter 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 2 2 3 3 1 1 1 1 1 1 1 1 1 selected input clock prescaler counter FTM counting is up PS 2 0 001 CNTIN 0x0000 M...

Page 912: ...counter clock MOD 0x0004 TOF bit set TOF bit set TOF bit set TOF bit 4 4 3 2 1 4 3 2 1 0 1 2 3 4 0 1 2 3 4 4 3 CNTIN 0xFFFC in two s complement is equal to 4 period of counting MOD CNTIN 0x0001 x peri...

Page 913: ...gisters meet this requirement Any values of CNTIN and MOD that do not satisfy this criteria can result in unpredictable behavior MOD CNTIN is a redundant condition In this case the FTM counter is alwa...

Page 914: ...D defines the final value of the count The value of CNTIN is loaded into the FTM counter and the counter increments until the value of MOD is reached at which point the counter is decremented until it...

Page 915: ...or if CnV 15 1 In this case 0 CPWM is generated The figure below shows the possible counter events when in up down counting mode See Counter events for more details FTM counter 0 0 1 1 1 1 2 2 2 2 3...

Page 916: ...TOF bit MOD 0x0000 counter event Figure 39 11 Example when the FTM counter is free running The FTM counter is also a free running counter when FTMEN 1 QUADEN 0 CPWMS 0 CNTIN 0x0000 and MOD 0xFFFF 39 5...

Page 917: ...will be used to generate the counter event Figure at Up down counting shows the possible counter events FTM counter is reseted see Counter reset or a value different from zero is written at CLKS field...

Page 918: ...w true pulses set Output on match up 1 0 XX 10 Combine PWM High true pulses set on channel n match and clear on channel n 1 match X1 Low true pulses clear on channel n match and set on channel n 1 mat...

Page 919: ...ctly is FTM input clock divided by 4 which is required to meet Nyquist criteria for signal sampling Writes to the CnV register is ignored in Input Capture mode While in Debug mode the input capture fu...

Page 920: ...hen there is a state change in the input signal the counter is reset and starts counting up As long as the new state is stable on the input the counter continues to increment When the counter is equal...

Page 921: ...e input signal is delayed only by the synchronizer and edge dector logic if the filter is disabled FTM input clock channel n input FTM counter CHnFVAL 3 0 filter counter C n V CHF 1 2 3 4 5 6 7 8 9 10...

Page 922: ...6 0x25 0x24 0x23 0x22 0x21 0x20 Figure 39 16 Example of the Input Capture mode with ICRST 1 NOTE It is expected that the ICRST bit be set only when the channel is in input capture mode If the FTM coun...

Page 923: ...output counter overflow counter overflow counter overflow channel n match channel n match CNT MOD 0x0005 CnV 0x0003 CHF bit Figure 39 18 Example of the Output Compare mode when the match clears the ch...

Page 924: ...nels within an FTM period counter overflow counter overflow counter overflow channel n output channel n match channel n match channel n match pulse width Figure 39 20 EPWM period and pulse width with...

Page 925: ...ter overflow 0 1 2 3 4 5 6 7 8 0 1 2 previous value Figure 39 22 EPWM signal with ELSB ELSA X 1 If CnV 0x0000 then the channel n output is a 0 duty cycle EPWM signal and CHF bit is not set even when t...

Page 926: ...all channels are aligned with the value of CNTIN The other channel modes are not compatible with the up down counter CPWMS 1 Therefore all FTM channels must be used in CPWM mode when CPWMS 1 pulse wi...

Page 927: ...0005 Figure 39 25 CPWM signal with ELSB ELSA X 1 If CnV 0x0000 or CnV is a negative value that is CnV 15 1 then the channel n output is a 0 duty cycle CPWM signal and CHF bit is not set even when ther...

Page 928: ...at the channel n match FTM counter C n V See the following figure If ELSB ELSA X 1 then the channel n output is forced high at the beginning of the period FTM counter CNTIN and at the channel n 1 matc...

Page 929: ...h ELSB ELSA 1 0 channel n output with ELSB ELSA X 1 MOD C n 1 V C n V CNTIN Figure 39 28 Channel n output if CNTIN C n V MOD and C n 1 V MOD FTM counter C n 1 V channel n output with ELSB ELSA 1 0 cha...

Page 930: ...C n V is Almost Equal to CNTIN and C n 1 V MOD FTM counter not fully 100 duty cycle channel n output with ELSB ELSA 1 0 channel n output with ELSB ELSA X 1 not fully 0 duty cycle MOD C n V CNTIN C n 1...

Page 931: ...C n 1 V are not between CNTIN and MOD FTM counter 0 duty cycle channel n output with ELSB ELSA 1 0 channel n output with ELSB ELSA X 1 100 duty cycle MOD CNTIN C n 1 V C n V Figure 39 33 Channel n ou...

Page 932: ...LSB ELSA X 1 100 duty cycle 0 duty cycle MOD C n 1 V C n V Figure 39 35 Channel n output if C n V C n 1 V MOD channel n match is ignored FTM counter channel n output with ELSB ELSA 1 0 channel n outpu...

Page 933: ...37 Channel n output if C n V CNTIN and CNTIN C n 1 V MOD C n 1 V channel n output with ELSB ELSA X 1 FTM counter CNTIN channel n output with ELSB ELSA 1 0 C n V MOD Figure 39 38 Channel n output if C...

Page 934: ...ure 39 39 Channel n output if C n V MOD and CNTIN C n 1 V MOD C n V CNTIN channel n output with ELSB ELSA X 1 channel n output with ELSB ELSA 1 0 FTM counter C n 1 V MOD Figure 39 40 Channel n output...

Page 935: ...ut with ELSB ELSA X 1 0 duty cycle MOD C n V CNTIN C n 1 V Figure 39 42 Channel n output if C n V CNTIN and C n 1 V MOD 39 5 9 1 Asymmetrical PWM In Combine mode the PWM first edge channel n match FTM...

Page 936: ...l n 1 output with COMP 1 channel n 1 output with COMP 0 channel n output with ELSB ELSA X 1 channel n match Figure 39 44 Channel n 1 output in Complementary mode with ELSB ELSA X 1 NOTE The Complement...

Page 937: ...mode is not CPWM then MOD or HCR is updated after MOD or HCR register was written and the FTM counter changes from MOD to CNTIN If the FTM counter is at free running counter mode then this update occu...

Page 938: ...e end of the prescaler counting If SYNCEN 1 then CnV register is updated by the C n V and C n 1 V register synchronization If the selected mode is not output compare and SYNCEN 1 then CnV register is...

Page 939: ...itten to it NOTE The HWTRIGMODE bit must be 1 only with enhanced PWM synchronization SYNCMODE 1 39 5 12 2 Software trigger A software trigger event occurs when 1 is written to the SYNC SWSYNC bit The...

Page 940: ...nt write 1 to SWSYNC bit Figure 39 46 Software trigger event 39 5 12 3 Synchronization Points The synchronization points are points where the registers can be updated with their write buffer by PWM sy...

Page 941: ...OD register with its buffer value This synchronization is enabled if FTMEN 1 The MOD register synchronization can be done by either the enhanced PWM synchronization SYNCMODE 1 or the legacy PWM synchr...

Page 942: ...bit wait hardware trigger n HWTRIGMODE bit clear TRIGn bit wait the next selected loading point update MOD with its buffer value update MOD with its buffer value HWRSTCNT bit Figure 39 48 MOD register...

Page 943: ...1 to TRIG0 bit TRIG0 bit trigger 0 event FTM input clock Figure 39 50 MOD synchronization with SYNCMODE 0 HWTRIGMODE 0 PWMSYNC 0 REINIT 0 and a hardware trigger was used If SYNCMODE 0 PWMSYNC 0 and RE...

Page 944: ...PWMSYNC 0 REINIT 1 and a hardware trigger was used If SYNCMODE 0 and PWMSYNC 1 then this synchronization is made on the next selected loading point after the software trigger event takes place The SW...

Page 945: ...mechanism is the same as the MOD register synchronization However it is expected that the C n V and C n 1 V registers be synchronized only by the enhanced PWM synchronization SYNCMODE 1 39 5 12 7 OUT...

Page 946: ...trigger n TRIGn bit HWOM bit SWOM bit SWSYNC bit rising edge of FTM input clock update OUTMASK with its buffer value hardware trigger OUTMASK is updated by software trigger OUTMASK is updated by hard...

Page 947: ...trigger event FTM input clock Figure 39 55 OUTMASK synchronization with SYNCMODE 0 SYNCHOM 1 PWMSYNC 0 and software trigger was used write 1 to TRIG0 bit TRIG0 bit trigger 0 event OUTMASK register is...

Page 948: ...NVCTRL register synchronization updates the INVCTRL register with its buffer value The INVCTRL register can be updated at each rising edge of FTM input clock INVC 0 or by the enhanced PWM synchronizat...

Page 949: ...ising edge of FTM input clock update INVCTRL with its buffer value update INVCTRL with its buffer value HWINVC bit TRIGn bit wait hardware trigger n update INVCTRL with its buffer value HWTRIGMODE bit...

Page 950: ...WOCTRL is updated by hardware trigger enhanced PWM synchronization update SWOCTRL register by PWM synchronization update SWOCTRL register at each rising edge of FTM input clock yes 0 1 0 0 no 1 SWOC b...

Page 951: ...put from transitioning to 1 If no deadtime insertion is selected then the channel n 1 transitions to logical value 1 immediately after the synchronization event occurs synchronization event channel n...

Page 952: ...dware trigger TRIGn bit 0 0 0 0 0 1 Figure 39 61 FTM counter synchronization flowchart In the case of legacy PWM synchronization the FTM counter synchronization depends on REINIT and PWMSYNC bits acco...

Page 953: ...counter synchronization with SYNCMODE 0 HWTRIGMODE 0 REINIT 1 PWMSYNC 0 and a hardware trigger was used If SYNCMODE 0 REINIT 1 and PWMSYNC 1 then this synchronization is made on the next enabled hardw...

Page 954: ...lected the channel n output behavior is changed to force high at the beginning of the PWM period force low at the channel n match and force high at the channel n 1 match See the following figure NOTE...

Page 955: ...RL register synchronization INV m bit channel n output after the inverting channel n 1 output after the inverting INV m bit selects the inverting to the pair channels n and n 1 channel n output before...

Page 956: ...NOTE CH n OCV 1 and CH n 1 OCV 0 SWOCTRL register synchronization SWOCTRL register synchronization write to SWOCTRL register write to SWOCTRL register Figure 39 67 Example of software output control i...

Page 957: ...the DEADTIME delay is the FTM input clock divided by DTPS bits and the DTVAL 5 0 bits define the deadtime modulo that is the number of the deadtime prescaler clocks The deadtime delay insertion ensur...

Page 958: ...1 0 POL n 0 and POL n 1 0 FTM counter channel n 1 match channel n output before deadtime insertion channel n 1 output before deadtime insertion channel n output after deadtime insertion channel n 1 o...

Page 959: ...annel n output before deadtime insertion channel n output after deadtime insertion channel n 1 output before deadtime insertion channel n 1 output after deadtime insertion Figure 39 70 Example of the...

Page 960: ...the following figure FTM counter channel n output before output mask channel n output after output mask the beginning of new PWM cycles configured PWM signal starts to be available in the channel n ou...

Page 961: ...ow the counter is reset At the next input transition the counter starts counting again Any pulse that is shorter than the minimum value selected by FFVAL 3 0 bits system clock is regarded as a glitch...

Page 962: ...FAULTEN 1 then outputs are forced to their safe values Channel n output takes the value of POL n Channel n 1 takes the value of POL n 1 The fault interrupt is generated when FAULTF 1 and FAULTIE 1 Thi...

Page 963: ...OLn 0 NOTE Figure 39 75 Fault control with automatic fault clearing 39 5 17 2 Manual fault clearing If the manual fault clearing is selected FAULTM 1 0 0 1 or 1 0 then the channels output disabled by...

Page 964: ...ut polarity is high so the logical one at the fault input j indicates a fault If FLTjPOL 1 the fault j input polarity is low so the logical zero at the fault input j indicates a fault 39 5 18 Polarity...

Page 965: ...is forced to one is forced to one The following table shows the values that channels n and n 1 are forced by initialization when COMP 1 or DTEN 1 Table 39 14 Initialization behavior when COMP 1 or DT...

Page 966: ...bine modes channel n output channel n MSA channel n ELSB channel n ELSA channel n 1 MSA channel n 1 ELSB channel n 1 ELSA Figure 39 77 Priority of the features used at the generation of channels n and...

Page 967: ...IG 1 d CH0TRIG 1 CH1TRIG 1 CH2TRIG 1 CH3TRIG 1 CH4TRIG 1 CH5TRIG 1 the beginning of new PWM cycles MOD FTM counter C5V FTM counter C4V FTM counter C3V FTM counter C2V FTM counter C1V FTM counter C0V C...

Page 968: ...trigger generation in the output channel for up down counting mode 39 5 23 Initialization trigger Initialization trigger allows FTM to generate an external trigger in some specific points of FTM coun...

Page 969: ...02 0x03 0x04 0x05 initialization trigger FTM counter FTM input clock CNTIN 0x0000 MOD 0x000F ITRIGR 0 Figure 39 81 Initialization trigger is generated when the FTM counting achieves the CNTIN register...

Page 970: ...CNT CNTIN CLKS 1 0 0 0 and a value different from zero is written to CLKS 1 0 bits FTM input clock CNT channel n input CHF bit C n V XX 0x27 selected channel n input event rising edge NOTE Channel n i...

Page 971: ...configured to the Up counting When the Capture Test mode is enabled CAPTEST 1 the FTM counter is frozen and any write to CNT register updates directly the FTM counter see the following figure After i...

Page 972: ...Request Channel Interrupt 0 0 The channel DMA transfer request is not generated The channel interrupt is not generated 0 1 The channel DMA transfer request is not generated The channel interrupt is ge...

Page 973: ...interrupt channel n 1 interrupt C n 1 V 15 0 C n V 15 0 channel n 1 CHIE channel n CHIE FTMEN DECAPEN DECAP channel n MSA channel n ELSB ELSA CLK CLK D Q D Q 0 1 FTM input clock channel n 1 ELSB ELSA...

Page 974: ...B and channel n 1 ELSA bits are channel n 1 bits The Dual Edge Capture mode must be used with channel n ELSB ELSA 0 1 or 1 0 channel n 1 ELSB ELSA 0 1 or 1 0 and the FTM counter in Free running counte...

Page 975: ...egisters For a new sequence of the measurements in the Dual Edge Capture Continuous mode clear the channel n CHF and channel n 1 CHF bits to start new measurements 39 5 26 3 Pulse width measurement If...

Page 976: ...nel n 1 CHF C n V channel n 1 CHF bit channel n CHF bit clear channel n CHF 1 Figure 39 88 Dual Edge Capture One Shot mode for positive polarity pulse width measurement The following figure shows an e...

Page 977: ...od measurement If the channels n and n 1 are configured to capture consecutive edges of the same polarity then the period of the channel n input signal is measured If both channels n and n 1 are confi...

Page 978: ...DECAPEN set DECAP clear channel n CHF and clear channel n 1 CHF are made by the user 4 9 11 12 13 14 6 15 16 17 18 19 20 21 22 23 24 25 26 27 28 17 20 15 20 23 C n V channel n 1 CHF bit channel n CHF...

Page 979: ...channel n CHF 1 8 12 22 24 11 19 21 23 25 27 23 20 19 17 7 9 11 13 15 6 8 10 12 16 14 24 22 20 18 26 25 21 Figure 39 91 Dual Edge Capture Continuous mode to measure of the period between two consecuti...

Page 980: ...curred and the read of C n 1 V returns the FTM counter value when the event 2 occurred read C n 1 V FTM counter channel n input after the filter channel input channel n capture buffer C n V C n 1 V ch...

Page 981: ...n FILTER0 register The phase B input filter is enabled by PHBFLTREN bit and this filter s value is defined by CH1FVAL 3 0 bits CH n 1 FVAL 3 0 bits in FILTER0 register Except for CH0FVAL 3 0 and CH1FV...

Page 982: ...e A and B signals define the counting rate The FTM counter is updated when there is an edge either at the phase A or phase B signals If PHAPOL 0 and PHBPOL 0 then the FTM counter increment happens whe...

Page 983: ...nter overflow occurred phase A phase B FTM counter increment decrement FTM counter MOD CNTIN 0x0000 Time 1 1 1 1 1 1 1 set TOF set TOFDIR set TOF set TOFDIR 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Figure 39...

Page 984: ...uadrature Decoder boundary conditions The following figures show the FTM counter responding to motor jittering typical in motor position control applications phase A phase B FTM counter MOD CNTIN 0x00...

Page 985: ...lations 39 5 28 Debug mode When the chip is in Debug mode the BDMMODE 1 0 bits select the behavior of the FTM counter the channel n CHF bit the channels output and the writes to the MOD CNTIN and C n...

Page 986: ...alue except for channels in Output Compare mode In the channels outputs initialization the channel n output is forced to the CH n OI bit value when the value 1 is written to INIT bit See Initializatio...

Page 987: ...ate an initialization trigger and a register reload when a load point is reached Note that Load Frequency configuration can modify the RF generation half cycle match HCSEL counter event channel 0 matc...

Page 988: ...up counting The table below shows the possible counter events selection reload opportunities to up down counting mode Table 39 19 Reload opportunities to up down counting mode FTM_SYNC bits Reload op...

Page 989: ...t select these reload points at the safe points in time 39 5 30 Global Load The global load mechanism allows several modules to have their double buffered registers synchronously reloaded after a sync...

Page 990: ...counter enable logic FTM counter enable gtb_out Figure 39 103 Global time base GTB block diagram The GTB functionality is implemented by the GTBEEN and GTBEOUT bits in the CONF register the input sig...

Page 991: ...3 Write 1 to CONF GTBEEN and write 0 to CONF GTBEOUT at the same time 4 Select the intended FTM counter clock source in SC CLKS The clock source needs to be consistent across all participating module...

Page 992: ...be used by applications where more resolution than one unit of the FTM counter is needed Two kinds of dithering are available PWM period dithering and edge dithering 39 5 33 1 PWM Period Dithering Th...

Page 993: ...accumulator overflows that is the result of the adding is greater or equal than 0x20 then one unit of FTM counter is added to the end of the current PWM period and the accumulator remains with the re...

Page 994: ...x0001 0x0001 x T 0x000E x T Figure 39 104 PWM Period Dithering with Up Counting Assuming the FTM counter is an up counter T is one unit of FTM counter the PWM period without period dithering is MOD CN...

Page 995: ...d Dithering it is recommended to use C n MOD 1 For the generation of PWM signals in the channel n with channel n ELSB ELSA 2 b10 using Combine mode and PWM Period Dithering it is recommended to use Fo...

Page 996: ...sing CPWM mode and PWM Period Dithering it is recommended to use C n V 15 0 and C n V MOD 1 and MOD 0x0000 39 5 33 2 PWM Edge Dithering The channel n internal accumulator used in the PWM edge ditherin...

Page 997: ...s on the channel n match FTM counter C n V that is its position is not modified by the edge dithering However if there was the overflow of the channel n accumulator in the current EPWM period then the...

Page 998: ...al are DC1 50 x T DC2 51 x T average duty cycle 50 5 32 x T 50 15625 x T PWM edge dithering PWM edge dithering PWM edge dithering PWM edge dithering PWM edge dithering Figure 39 108 Example of Average...

Page 999: ...ode with PWM Edge Dithering 39 5 33 2 3 Combine Mode In the Combine mode the PWM edge dithering can be done in the channel n match FTM counter C n V edge or in the channel n 1 match FTM counter C n 1...

Page 1000: ...ering in Combine Mode The channel n 1 match edge dithering is enabled when a non zero value is written to the channel n 1 FRACVAL For the channel n 1 match edge dithering the channel n 1 has an intern...

Page 1001: ...Combine duty cycle DC1 C n V C n 1 V x T 0x0002 x T Figure 39 111 Channel n 1 Match Edge Dithering in Combine Mode NOTE It is recommended to use only one PWM Edge Dithering channel n PWM Edge Ditheri...

Page 1002: ...This write updates the FTM counter with the CNTIN register value and the channels output with its initial value except for channels in output compare mode Counter reset The next step is to select the...

Page 1003: ...and the channel n output is toggled when there is a match C n V 0x0014 00 XX 01 4 use of software output control or initialization to update the channel output to the zero Figure 39 113 FTM behavior a...

Page 1004: ...ntrol Do not use the SWOC without SW synchronization see item 6 Do not use the Inverting without SW synchronization see item 6 Do not use the Initialization Do not change the polarity control Do not c...

Page 1005: ...owever these sources are OR d together to generate a single interrupt request to the interrupt controller When an FTM interrupt occurs read the FTM status registers FMS SC and STATUS to determine the...

Page 1006: ...l is asserted Any of the 8 channels of FTM0 can be configured to support this modulation function The SIM_FTMOPT1 register has control bits FTMxCHySEL that allow the user to select normal PWM Output C...

Page 1007: ...ature Any of the FTM module could be used as the GTB_EN source The global timer base only allows the FTM counters to start their operation synchronously it does not automatically provide continuous sy...

Page 1008: ...d debug halt mode In the FTM chapter references to the chip being in BDM are the same as the chip being in debug halt mode Usage Guide Kinetis KE1xZ256 Sub Family Reference Manual Rev 3 07 2018 1008 N...

Page 1009: ...ral Clocking LPUART PCC_LPUARTx CGC PCC module DIV2 DIV2 DIV2 DIV2 SOSC FLL FIRC SIRC SCG module SCG DIVSLOW FLLDIV2_CLK SOSCDIV2_CLK SIRCDIV2_CLK FIRCDIV2_CLK LPUARTx module BUS_CLK Peripheral Interf...

Page 1010: ...LPIT_EXT_TRG3 40 2 Introduction 40 2 1 Overview The Low Power Periodic Interrupt Timer LPIT is a multi channel timer module generating independent pre trigger and trigger outputs These timer channels...

Page 1011: ...nels are chained By chaining timer channels applications can achieve larger timeout durations In capture mode the timer can be used to perform measurements as the timer value is captured in the timer...

Page 1012: ...t External Trigger Inputs per channel Sync ed Reset to all Timer channels Channel Registers Access Synchronizer Counter Value Timeout Load Enable Sync ed External Triggers per channel Timer Channel n...

Page 1013: ...014 Set Timer Enable Register LPIT0_SETTEN 32 R W 0000_0000h 40 4 6 1018 4003_7018 Clear Timer Enable Register LPIT0_CLRTEN 32 W always reads 0 0000_0000h 40 4 7 1019 4003_7020 Timer Value Register LP...

Page 1014: ...ture set number 40 4 2 Parameter Register LPITx_PARAM This register provides details on the parameter settings that were used while including this module in the device Address 4003_7000h base 4h offse...

Page 1015: ...ode 0 Timer channels are stopped in DOZE mode 1 Timer channels continue to run in DOZE mode 1 SW_RST Software Reset Bit Resets all channels and registers except the Module Control Register Remains set...

Page 1016: ...g clears it Writing 0 has no effect 0 Timer has not timed out 1 Timeout has occurred 2 TIF2 Channel 2 Timer Interrupt Flag In compare modes sets to 1 at the end of the timer period In capture modes se...

Page 1017: ...upt Flag is asserted 0 Interrupt generation is disabled 1 Interrupt generation is enabled 2 TIE2 Channel 2 Timer Interrupt Enable Enables interrupt generation when this bit is set to 1 and if correspo...

Page 1018: ...ad only field is reserved and always has the value 0 3 SET_T_EN_3 Set Timer 3 Enable Writing 1 to this bit will enable the timer channel 3 This bit can be used in addition to T_EN bit in TCTRL3 regist...

Page 1019: ...n to T_EN bit in TCTRL0 register Writing a 0 will not disable the counter This bit will be cleared when T_EN bit in TCTRL0 is set to 0 or 1 is written to the CLR_T_EN_0 bit in CLRTEN register 0 No eff...

Page 1020: ...CTRL1 register Writing a 1 will not enable the counter This bit is self clearing and will always read 0 0 No Action 1 Clear T_EN bit for Timer Channel 1 0 CLR_T_EN_0 Clear Timer 0 Enable Writing a 1 t...

Page 1021: ...ter whenever the trigger asserts 0 Invalid load value in compare modes 0 Value to be loaded Compare Mode or Value of Timer Capture Mode 40 4 9 Current Timer Value LPITx_CVALn These registers indicate...

Page 1022: ...t one trigger from the set of internal or external triggers selected by TRG_SRC 0 Timer channel 0 trigger source is selected 1 Timer channel 1 trigger source is selected 2 Timer channel 2 trigger sour...

Page 1023: ...s decrementing 0 Timer starts to decrement immediately based on restart condition controlled by TSOI bit 1 Timer starts to decrement when rising edge on selected trigger is detected 15 4 Reserved This...

Page 1024: ...gured in Compare Mode set the timer timeout value by programming the appropriate value in TVAL register for those channels Configure TIEn bits in MIER register for those channels which are required to...

Page 1025: ...SOI TROT which control the timer load reload start and restart of the timers NOTE The trigger output is asserted one Protocol Timer Clock cycle later than pre trigger output The trigger output and the...

Page 1026: ...channels can be chained together to achieve a larger value of timeout Chaining the timer channel causes them to work in a nested loop manner thereby leading to an effective timeout value of TVALCHn TV...

Page 1027: ...LUE LPIT0_MIER LPIT_MIER_TIE0_MASK NVIC_EnableIRQ LPIT0_IRQ LPIT0_SETTEN LPIT_SETTEN_SET_T_EN_0_MASK 40 6 2 LPIT ADC Trigger The LPIT could be used as an alternate ADC hardware trigger source whose im...

Page 1028: ...operation in debug and doze modes and enable LPIT module Setup the LPIT_CH0 and LPIT_CH1 counters mode to 32 bit Periodic Counter and keep default values for the trigger source Set timer period for L...

Page 1029: ...PRETRG_DELAY_VALUE1 LPIT0_TVAL1 ADC_PRETRG_DELAY_VALUE2 LPIT0_SETTEN LPIT_SETTEN_SET_T_EN_0_MASK LPIT_SETTEN_SET_T_EN_1_MASK SIM_ADCOPT SIM_ADCOPT_ADC0TRGSEL 1 SIM_ADCOPT_ADC0PRETRGSEL 1 TRGMUX0_ADC0...

Page 1030: ...Usage Guide Kinetis KE1xZ256 Sub Family Reference Manual Rev 3 07 2018 1030 NXP Semiconductors...

Page 1031: ...PWT has two selectable clocks sources and support up to BUS_CLK with internal timer clock PWT module supports programmable positive or negative pulse edges and programmable interrupt generation upon...

Page 1032: ...K1 TCLK2 41 1 3 Inter connectivity Information PWT module has four input channels which is connected as shown in the following table Table 41 1 PWT input connections PWT input channel Connection 0 TRG...

Page 1033: ...tive pulse width measurements Programmable measuring time between successive alternating edges rising edges or falling edges Programmable pre scaler from clock input as 16 bit counter time base Two se...

Page 1034: ...resets If stop exits with another source the module resumes operation based on module status upon exit Active Background Mode Upon entering BDM mode the PWT suspends all counting and pulse edge detect...

Page 1035: ...YNC PWTIN2 PWTIN0 PINSEL 1 0 PWTIN PWTIN3 Decode PINEN0 MUX PINEN1 PINEN2 PINEN3 PWTLVL Figure 41 1 Pulse width timer PWT block diagram External signal description 41 3 1 Overview PWT has the followin...

Page 1036: ...rth of the bus frequency The ALTCLK pin can be shared with a general purpose port pin See the Pins and Connections chapter for the pin location and priority of this function Memory Map and Register De...

Page 1037: ...generate interrupt when PWTRDY is set 1 Enable PWT to generate interrupt when PWTRDY is set 4 POVIE PWT Counter Overflow Interrupt Enable Enables disables the PWT to generate an interrupt when PWTOV i...

Page 1038: ...4 2 Pulse Width Timer Control Register PWT_CR Address 4005_6000h base 1h offset 4005_6001h Bit 7 6 5 4 3 2 1 0 Read PCLKS PINSEL TGL LVL PRE Write w1c Reset 0 0 0 0 0 0 0 0 PWT_CR field descriptions...

Page 1039: ...vided by 8 100 Clock divided by 16 101 Clock divided by 32 110 Clock divided by 64 111 Clock divided by 128 41 4 3 Pulse Width Timer Positive Pulse Width Register High PWT_PPH Address 4005_6000h base...

Page 1040: ...ions Field Description NPWH Negative Pulse Width 15 8 High byte of captured negative pulse width value 41 4 6 Pulse Width Timer Negative Pulse Width Register Low PWT_NPL Address 4005_6000h base 5h off...

Page 1041: ...field descriptions Field Description PWTL PWT counter 7 0 Low byte of PWT counter register Functional description 41 5 1 PWT counter and PWT clock pre scaler The pulse width timer PWT measures duratio...

Page 1042: ...free counter will begin to count up until a edge transistion on the selected PWTIN Determined by PWT_CS FCTLE and PWTIN state the counter contents can be uploaded to the corresponding registers If PWT...

Page 1043: ...1 12 0x0 0x0 0xD1 0xD2 0x00 0xD1 0x00 0xD2 0x00 0x00 PWTEN FCTLE 0 PWTIN NPH L PPH L READY CNTH L Figure 41 2 PWT normal measurement with FCTLE 0 1 2 3 4 5 6 7 8 9 10 11 12 0x0 0x0 0xD4 0xD3 0x00 0xD4...

Page 1044: ...CTLE 1 1 2 3 4 5 6 7 8 9 10 11 12 PWTEN PWTIN PWTOV TGL LVL CNTH L 0x00 0xFFFF Figure 41 5 PWT measurement overflows with PWTIN toggles 1 2 3 4 5 6 7 8 9 10 11 12 0x00 0xFFFF PWTEN PWTIN PWTOV TGL LVL...

Page 1045: ...r If another pulse measurement is completed and the pulse width registers are updated the clearing of the PWTRDY flag fails i e the PWTRDY will still be set but the 16 bit read buffer s will be update...

Page 1046: ...e is no missing count the PWTxCNTH L and the clock pre scaler output are reset in a bus clock cycle after the completion of a pulse width measurement Reset overview 41 6 1 Description of reset operati...

Page 1047: ...except that the reset state will be held until the PWTEN bit is set to 1 Interrupts 41 7 1 Description of interrupt operation The other major component of the PWT is the interrupts control logic When...

Page 1048: ...0 212223 err 1 pwtclk 1 bus clock Figure 41 8 Example at PWTCLK is bus clock divided by 1 0 1 2 3 4 5 6 7 8 9 10 11 0 1 2 3 4 5 6 7 8 9 1011 counter read result 11 pwtclk counter read result 11 pwtclk...

Page 1049: ...2 pwtclk err 0 err 1 pwtclk 1 bus clock 0 1 2 Figure 41 11 Example at PWTCLK is bus clock divided by 8 41 8 Initialization Application information Following are the recommended steps to initialize th...

Page 1050: ...ture control and period measurement PWT typical usage is external signal input capture and time period measurement Example PWT input channel 1 capture external signal and measure its time period Enabl...

Page 1051: ...S PWT_CR_PCLKS 0 PWT_CR_PRE 0 PWT_CR_PINSEL 1 PWT_CS PWT_CS_PWTEN_MASK EnableIRQ PWT_IRQ Chapter 41 Pulse Width Timer PWT Kinetis KE1xZ256 Sub Family Reference Manual Rev 3 07 2018 NXP Semiconductors...

Page 1052: ...Usage Guide Kinetis KE1xZ256 Sub Family Reference Manual Rev 3 07 2018 1052 NXP Semiconductors...

Page 1053: ...input clock sources available for this module Peripheral Clocking LPTMR PCC_LPTMRx CGC PCC module DIV2 DIV2 DIV2 DIV2 SOSC FLL FIRC SIRC SCG module SCG DIVSLOW FLLDIV2_CLK SOSCDIV2_CLK SIRCDIV2_CLK FI...

Page 1054: ...TPS Pulse counter input number Chip input 00 0 TRGMUX output 01 1 LPTMR0_ALT1 pin 10 2 LPTMR0_ALT2 pin 11 3 LPTMR0_ALT3 pin TRGMUX LPTMRx_HW_TRG LPTMRx LPTMRx_ALT2 LPTMRx_ALT1 LPTMRx_ALT3 PERIPHERAL B...

Page 1055: ...source for prescaler glitch filter Configurable input source for pulse counter Rising edge or falling edge 42 2 2 Modes of operation The following table describes the operation of the LPTMR module in...

Page 1056: ...ming Assertion or deassertion may occur at any time input may assert asynchronously to the bus clock 42 4 Memory map and register definition NOTE The LPTMR registers are reset only on a POR or LVD eve...

Page 1057: ...PTMR is enabled and the CNR equals the CMR and increments TCF is cleared when the LPTMR is disabled or a logic 1 is written to it 0 The value of CNR is not equal to CMR and increments 1 The value of C...

Page 1058: ...TMR is disabled 0 Time Counter mode 1 Pulse Counter mode 0 TEN Timer Enable When TEN is clear it resets the LPTMR internal logic including the CNR and TCF When TEN is set the LPTMR is enabled While wr...

Page 1059: ...er divides the prescaler clock by 2048 glitch filter recognizes change on input pin after 1024 rising clock edges 1011 Prescaler divides the prescaler clock by 4096 glitch filter recognizes change on...

Page 1060: ...rdware trigger asserts until the next time the CNR increments If the CMR is 0 the hardware trigger will remain asserted until the LPTMR is disabled If the LPTMR is enabled the CMR must be altered only...

Page 1061: ...The clock source selected may need to be configured to remain enabled in low power modes otherwise the LPTMR will not operate during low power modes In Pulse Counter mode with the prescaler glitch fi...

Page 1062: ...MR is first enabled the output of the glitch filter is asserted that is logic 1 for active high and logic 0 for active low The following table shows the change in glitch filter output with the selecte...

Page 1063: ...scaler bypassed Prescaler output in Time Counter mode with prescaler enabled Input source assertion in Pulse Counter mode with glitch filter bypassed Glitch filter output in Pulse Counter mode with gl...

Page 1064: ...1 to it CSR TIE can be altered and CSR TCF can be cleared while the LPTMR is enabled The LPTMR interrupt is generated asynchronously to the system clock and can be used to generate a wakeup from any l...

Page 1065: ...t pulses on LPTMR0_ALT1 pin Enable the LPTMR module clock Configure LPTMR to Pulse counter mode use LPO 128K as clock source bypass the glitch filter Set the compare value register to the value you wa...

Page 1066: ...Usage Guide Kinetis KE1xZ256 Sub Family Reference Manual Rev 3 07 2018 1066 NXP Semiconductors...

Page 1067: ...ore the related register bitfields are not applicable e g RTC_CR WPS RTC_CR WPE and RTC_IER WPON NOTE Also there is no integrated capacitor for this device therefore no tunable capacitors included in...

Page 1068: ...Hz 1kHz 128 LPO 128K OSC32 LPO_CLK OSC32_CLK OSCE RTC_CR LPOS Counter SIM_FTMOPT0 FTMnCLKSEL SIM_CHIPCTL RTC32KCLKSEL 43 1 3 Inter connectivity Information The SRTC inter connectivity is shown in foll...

Page 1069: ...32 bit seconds counter with roll over protection and 32 bit alarm 16 bit prescaler with compensation that can correct errors between 0 12 ppm and 3906 ppm Option to increment prescaler using the LPO p...

Page 1070: ...prescaler output configurable to 1 2 4 8 16 32 64 or 128 Hz or the 32 kHz crystal clock 43 3 Register definition All registers must be accessed using 32 bit writes and all register accesses incur thre...

Page 1071: ...h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R TSR W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RTC_TSR field descriptions Fie...

Page 1072: ...ld descriptions Field Description TAR Time Alarm Register When the time counter is enabled the SR TAF is set whenever the TAR TAR equals the TSR TSR and the TSR TSR increments Writing to the TAR clear...

Page 1073: ...o configure for a compensation interval of one second This register is double buffered and writes do not take affect until the end of the current compensation interval TCR Time Compensation Register C...

Page 1074: ...field is reserved This read only field is reserved and always has the value 0 25 24 CPE Clock Pin Enable NOTE The CPE field should be configured to 01 or 11 i e CPE 0 1 if we want the RTC_CLKOUT signa...

Page 1075: ...aler are bypassed 6 Reserved This field is reserved This read only field is reserved and always has the value 0 5 CPS Clock Pin Select 0 The prescaler output clock as configured by TSIC is output on R...

Page 1076: ...descriptions Field Description 31 5 Reserved This field is reserved This read only field is reserved and always has the value 0 4 TCE Time Counter Enable When time counter is disabled the TSR registe...

Page 1077: ...0 19 18 17 16 R 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 1 LRL SRL CRL TCL 1 W Reset 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 RTC_LR field descriptions Field Desc...

Page 1078: ...ss 4003_D000h base 1Ch offset 4003_D01Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 TSIC W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 WPON Reserve...

Page 1079: ...cated interrupt vector It is generated once a second and requires no software overhead there is no corresponding status flag to clear 0 Seconds interrupt is disabled 1 Seconds interrupt is enabled 3 R...

Page 1080: ...Register Write After being cleared this bit is set only by system reset It is not affected by software reset 0 Writes to the Lock Register are ignored 1 Writes to the Lock Register complete as normal...

Page 1081: ...0 Writes to the Time Seconds Register are ignored 1 Writes to the Time Seconds Register complete as normal 43 3 10 RTC Read Access Register RTC_RAR Address 4003_D000h base 804h offset 4003_D804h Bit 3...

Page 1082: ...tion Register are ignored 1 Reads to the Time Compensation Register complete as normal 2 TARR Time Alarm Register Read After being cleared this bit is set only by system reset It is not affected by so...

Page 1083: ...reset by the chip reset 43 4 1 3 Supervisor access When the supervisor access control bit is clear only supervisor mode software can write to the RTC registers non supervisor mode software will genera...

Page 1084: ...s high as 3906 ppm and as low as 0 12 ppm The compensation factor must be calculated externally to the RTC and supplied by software to the compensation register The RTC itself does not calculate the a...

Page 1085: ...l usually be the next alarm value although writing a value that is less than TSR such as 0 will prevent SR TAF from setting again SR TAF cannot otherwise be disabled although the interrupt it generate...

Page 1086: ...nerated once a second and requires no software overhead there is no corresponding status flag to clear It is enabled in the RTC by the time seconds interrupt enable bit and enabled at the chip level b...

Page 1087: ...initialized user can set the date time before starting the timer Please make sure the timer is stopped when setting the date time by RTC_TSR register stop timer first RTC_SR RTC_SR_TCE_MASK convert th...

Page 1088: ...output configurable to 1 2 4 8 16 32 64 or 128 Hz or 32 kHz output derived from RTC oscillator as shown below RTC_CR CPS RTC_CLKOUT RTC 1 2 4 8 16 32 64 128 Hz clock configurable via RTC_IER TSIC RTC...

Page 1089: ...nfiguration TX FIFO word 32bit RX FIFO word 32bit Chip Selects LPSPI0 4 4 4 LPSPI1 4 4 4 NOTE The TX RX FIFO word does not refer to system bus width 32 bit and it varies for different communication mo...

Page 1090: ...2_CLK FIRCDIV2_CLK LPUARTx module BUS_CLK Peripheral Interface Clock PCC_LPUARTx PCS see PCC chapter for detailed setting Registers Note this example figure also applies similarly to the clocking for...

Page 1091: ...Interface SPI module that supports an efficient interface to an SPI bus as a master and or a slave The LPSPI can continue operating in stop modes provided an appropriate clock is available and is desi...

Page 1092: ...s Clock External Clock Functional Clock Clock Domains Command TX FIFO RX FIFO Shift Register SCK PCS 3 0 Everywhere else Figure 44 1 Block Diagram 44 2 4 Modes of operation The LPSPI module supports t...

Page 1093: ...hen used as Host Request output in master mode I O PCS 2 DATA 2 Peripheral Chip Select or data pin 2 during quad data transfers Input in slave mode output in master mode input in quad data receive tra...

Page 1094: ...tus Register LPSPI0_FSR 32 R 0000_0000h 44 3 13 1107 4002_C060 Transmit Command Register LPSPI0_TCR 32 R W 0000_001Fh 44 3 14 1108 4002_C064 Transmit Data Register LPSPI0_TDR 32 W 0000_0000h 44 3 15 1...

Page 1095: ...13 44 3 1 Version ID Register LPSPIx_VERID Address Base address 0h offset Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R MAJOR MINOR FEATURE W Reset 0 0 0...

Page 1096: ...0 0 0 0 0 0 1 0 LPSPIx_PARAM field descriptions Field Description 31 16 Reserved This field is reserved This read only field is reserved and always has the value 0 15 8 RXFIFO Receive FIFO Size The n...

Page 1097: ...ield is reserved and always has the value 0 9 RRF Reset Receive FIFO 0 No effect 1 Receive FIFO is reset 8 RTF Reset Transmit FIFO 0 No effect 1 Transmit FIFO is reset 7 4 Reserved This field is reser...

Page 1098: ...9 8 7 6 5 4 3 2 1 0 R 0 DMF REF TEF TCF FCF WCF 0 RDF TDF W w1c w1c w1c w1c w1c w1c Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 LPSPIx_SR field descriptions Field Description 31 25 Reserved This field is r...

Page 1099: ...the PCS negates 0 Frame transfer has not completed 1 Frame transfer has completed 8 WCF Word Complete Flag This flag will set when the last bit of a received word is sampled 0 Transfer word not compl...

Page 1100: ...rror Interrupt Enable 0 Interrupt disabled 1 Interrupt enabled 11 TEIE Transmit Error Interrupt Enable 0 Interrupt disabled 1 Interrupt enabled 10 TCIE Transfer Complete Interrupt Enable 0 Interrupt d...

Page 1101: ...3 2 1 0 R 0 RDDE TDDE W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LPSPIx_DER field descriptions Field Description 31 2 Reserved This field is reserved This read only field is reserved and always has the...

Page 1102: ...d unless the DMF is set 8 CIRFIFO Circular FIFO Enable When enabled the transmit FIFO read pointer is saved to a temporary register The transmit FIFO will be emptied as normal but once the LPSPI is id...

Page 1103: ...G 0 MATCFG W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 PCSPOL 0 NOSTALL AUTOPCS SAMPLE MASTER W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LPSPIx_CFGR1 field descr...

Page 1104: ...erved This field is reserved This read only field is reserved and always has the value 0 11 8 PCSPOL Peripheral Chip Select Polarity Configures the polarity of each Peripheral Chip Select pin 0 The PC...

Page 1105: ...ve mode 1 Master mode 44 3 9 Data Match Register 0 LPSPIx_DMR0 Address Base address 30h offset Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R MATCH0 W Rese...

Page 1106: ...minimum delay is 1 cycle 15 8 DBT Delay Between Transfers Configures the delay in master mode from the PCS negation to the next PCS assertion The delay is equal to DBT 2 cycles of the LPSPI functiona...

Page 1107: ...Flag is set whenever the number of words in the transmit FIFO is equal or less than TXWATER Writing a value equal or greater than the FIFO size will be truncated 44 3 13 FIFO Status Register LPSPIx_F...

Page 1108: ...an existing frame has completed then the existing frame will terminate and the command word will then update The command word can be changed during a continuous transfer provided CONTC of the new comm...

Page 1109: ...nsfer This field is only updated between frames 00 Transfer using LPSPI_PCS 0 01 Transfer using LPSPI_PCS 1 10 Transfer using LPSPI_PCS 2 11 Transfer using LPSPI_PCS 3 23 LSBF LSB First 0 Data is tran...

Page 1110: ...er mode this bit will initiate a new transfer which cannot be aborted by another command word and the bit will be cleared by hardware at the end of the transfer 00 Normal transfer 01 Mask transmit dat...

Page 1111: ...19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W DATA Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LPSPIx_TDR field descriptions Field Description DATA Transmit Data Bot...

Page 1112: ...Field Description 31 2 Reserved This field is reserved This read only field is reserved and always has the value 0 1 RXEMPTY RX FIFO Empty 0 RX FIFO is not empty 1 RX FIFO is empty 0 SOF Start Of Fram...

Page 1113: ...sfers in both master and slave modes If the functional clock is disabled in slave mode the LPSPI can transfer a single word before the functional clock needs to be enabled The LPSPI divides the functi...

Page 1114: ...F A FIFO is empty after being reset 44 4 2 Master Mode 44 4 2 1 Transmit and Command FIFO The transmit and command FIFO is a combined FIFO that includes both transmit data and command words Command wo...

Page 1115: ...d on FRAMESZ configuration and the TXMSK bit will be cleared at the end of the transfer The following table describes the attributes that are controlled by the command word Table 44 3 LPSPI Command Wo...

Page 1116: ...sfers in either half duplex or full duplex data formats Two and four bit transfers are useful for interfacing to QuadSPI memory devices and only support half duplex data formats at least one of TXMSK...

Page 1117: ...nction that can match received data against one of two words or against a masked data word The data match function can also be configured to compare only the first one or two received data words since...

Page 1118: ...ds of a SPI bus transfer 0 1 cycle 255 256 cycles PCSSCK Configures the minimum delay between PCS assertion and the first SCK edge to PCSSCK 1 cycles 0 1 cycle 255 256 cycles SCKPCS Configures the min...

Page 1119: ...d configured by PCSPOL If PCSCFG is set then PCS 3 2 should not be selected LSBF Configures if LSB bit 0 or MSB bit 31 for a 32 bit word is transmitted received first BYSW Enables byte swap on each 32...

Page 1120: ...received data against one of two words or against a masked data word The data match function can also be configured to compare only the first one or two received data words since the start of the fram...

Page 1121: ...sampled Y N Y FCF Frame complete PCS has negated Y N Y TCF Transfer complete PCS has negated and transmit command FIFO is empty Y N Y TEF Transmit error flag indicates transmit command FIFO underrun T...

Page 1122: ...S negates and remains asserted until PCS next asserts The word output trigger asserts at the end of each received word and remains asserted for one LPSPI_SCK period 44 4 5 2 Input Trigger The LPSPI in...

Page 1123: ...mode provided the clock it is using remains enabled Table 45 1 LPI2C Configuration TX FIFO word 8bit RX FIFO word 8bit SMBus Slave mode enable LPI2C0 4 4 Yes Yes LPI2C1 4 4 Yes Yes 45 1 2 Module Clock...

Page 1124: ...ARTx PCS see PCC chapter for detailed setting Registers Note this example figure also applies similarly to the clocking for LPSPI LPI2C and LPIT ASYNCH MODULE CLOCK only for LPUART not in other module...

Page 1125: ...I2C bus as a master and or a slave The LPI2C can continue operating in stop modes provided an appropriate clock is available and is designed for low CPU overhead with DMA offloading of FIFO register a...

Page 1126: ...can be used to control the start time of an I2C bus transfer Flexible receive data match can generate interrupt on data match and or discard unwanted data Flag and optional interrupt to signal Repeate...

Page 1127: ...ation Registers Slave Logic SDAS SCLS Glitch Filter Bus Clock External Clock Functional Clock Clock Domains Command TX FIFO Figure 45 1 LPI2C block diagram 45 2 4 Modes of operation The LPI2C module s...

Page 1128: ...d to use separate pins this the LPI2C slave SCL pin I O SDAS Secondary I2C data line In 4 wire mode this is the SDA output pin If LPI2C master slave are configured to use separate pins this the LPI2C...

Page 1129: ..._4000h 45 3 17 1147 4006_6110 Slave Control Register LPI2C0_SCR 32 R W 0000_0000h 45 3 18 1148 4006_6114 Slave Status Register LPI2C0_SSR 32 R W 0000_0000h 45 3 19 1149 4006_6118 Slave Interrupt Enabl...

Page 1130: ...Control Register LPI2C1_MFCR 32 R W 0000_0000h 45 3 14 1145 4006_705C Master FIFO Status Register LPI2C1_MFSR 32 R 0000_0000h 45 3 15 1145 4006_7060 Master Transmit Data Register LPI2C1_MTDR 32 W 000...

Page 1131: ...eld returns the major version number for the specification 23 16 MINOR Minor Version Number This read only field returns the minor version number for the specification FEATURE Feature Specification Nu...

Page 1132: ...ransmit FIFO Size The number of words in the master transmit FIFO is 2 MTXFIFO 45 3 3 Master Control Register LPI2Cx_MCR Address Base address 10h offset Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 1...

Page 1133: ...e Reset Reset all internal master logic and registers except the Master Control Register Remains set until cleared by software 0 Master logic is not reset 1 Master logic is reset 0 MEN Master Enable 0...

Page 1134: ...pt to send or receive data without first generating a repeated START condition This can occur if the transmit FIFO underflows when the AUTOSTOP bit is set When this flag is set the LPI2C master will s...

Page 1135: ...reserved and always has the value 0 1 RDF Receive Data Flag The Receive Data Flag is set whenever the number of words in the receive FIFO is greater than RXWATER 0 Receive Data is not ready 1 Receive...

Page 1136: ...nterrupt disabled 1 Interrupt enabled 10 NDIE NACK Detect Interrupt Enable 0 Interrupt disabled 1 Interrupt enabled 9 SDIE STOP Detect Interrupt Enable 0 Interrupt disabled 1 Interrupt enabled 8 EPIE...

Page 1137: ...0 0 0 0 0 0 0 0 0 LPI2Cx_MDER field descriptions Field Description 31 2 Reserved This field is reserved This read only field is reserved and always has the value 0 1 RDDE Receive Data DMA Enable 0 DMA...

Page 1138: ...s the RMF is set 8 CIRFIFO Circular FIFO Enable When enabled the transmit FIFO read pointer is saved to a temporary register The transmit FIFO will be emptied as normal but once the LPI2C master is id...

Page 1139: ...CFG 0 MATCFG W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 TIMECFG IGNACK AUTOSTOP 0 PRESCALE W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LPI2Cx_MCFGR1 field descri...

Page 1140: ...out Configuration 0 Pin Low Timeout Flag will set if SCL is low for longer than the configured timeout 1 Pin Low Timeout Flag will set if either SCL or SDA is low for longer than the configured timeou...

Page 1141: ...is not affected by the PRESCALE configuration and is automatically bypassed in High Speed mode 23 20 Reserved This field is reserved This read only field is reserved and always has the value 0 19 16...

Page 1142: ...This field is reserved This read only field is reserved and always has the value 0 45 3 11 Master Data Match Register LPI2Cx_MDMR Address Base address 40h offset Bit 31 30 29 28 27 26 25 24 23 22 21 2...

Page 1143: ...setup and hold time for a repeated START condition and setup time for a STOP condition The setup time is extended by the time it takes to detect a rising edge on the external SCL pin Ignoring any addi...

Page 1144: ...1 16 SETHOLD Setup Hold Delay Minimum number of cycles minus one that is used by the master as the setup and hold time for a repeated START condition and setup time for a STOP condition The setup time...

Page 1145: ...ta Flag is set whenever the number of words in the transmit FIFO is equal or less than TXWATER Writing a value equal or greater than the FIFO size will be truncated 45 3 15 Master FIFO Status Register...

Page 1146: ...0 0 0 0 0 0 0 0 0 0 0 0 LPI2Cx_MTDR field descriptions Field Description 31 11 Reserved This field is reserved 10 8 CMD Command Data 000 Transmit DATA 7 0 001 Receive DATA 7 0 1 bytes 010 Generate ST...

Page 1147: ...nly field is reserved and always has the value 0 14 RXEMPTY RX Empty 0 Receive FIFO is not empty 1 Receive FIFO is empty 13 8 Reserved This field is reserved This read only field is reserved and alway...

Page 1148: ...9 RRF Reset Receive FIFO 0 No effect 1 Receive Data Register is now empty 8 RTF Reset Transmit FIFO 0 No effect 1 Transmit Data Register is now empty 7 6 Reserved This field is reserved This read onl...

Page 1149: ...28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 BBF SBF 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R SARF GCF AM1F AM0F FEF BEF SDF RSF 0 TAF AVF RDF TDF W w1c w1c...

Page 1150: ...ared by reading the Address Status Register This flag cannot generate an asynchronous wakeup 0 Have not received ADDR1 or ADDR0 ADDR1 range matching address 1 Have received ADDR1 or ADDR0 ADDR1 range...

Page 1151: ...iting the transmit ACK register 0 Transmit ACK NACK is not required 1 Transmit ACK NACK is required 2 AVF Address Valid Flag This flag is cleared by reading the address status register When RXCFG is s...

Page 1152: ...alue 0 15 SARIE SMBus Alert Response Interrupt Enable 0 Interrupt disabled 1 Interrupt enabled 14 GCIE General Call Interrupt Enable 0 Interrupt disabled 1 Interrupt enabled 13 AM1F Address Match 1 In...

Page 1153: ...upt disabled 1 Interrupt enabled 1 RDIE Receive Data Interrupt Enable 0 Interrupt disabled 1 Interrupt enabled 0 TDIE Transmit Data Interrupt Enable 0 Interrupt disabled 1 Interrupt enabled 45 3 21 Sl...

Page 1154: ...nabled 45 3 22 Slave Configuration Register 1 LPI2Cx_SCFGR1 The SCFGR1 should only be written when the I2C Slave is disabled Address Base address 124h offset Bit 31 30 29 28 27 26 25 24 23 22 21 20 19...

Page 1155: ...clear the receive data flag 1 Reading the receive data register when the address valid flag is set will return the address status register and clear the address valid flag Reading the receive data reg...

Page 1156: ...hing occurs following the 9th bit and is therefore compatible with high speed mode 0 Clock stretching disabled 1 Clock stretching enabled 1 RXSTALL RX SCL Stall Enables SCL clock stretching when recei...

Page 1157: ...lter cycle count is not affected by the PRESCALE configuration and is disabled in high speed mode 15 14 Reserved This field is reserved This read only field is reserved and always has the value 0 13 8...

Page 1158: ...ved This read only field is reserved and always has the value 0 45 3 25 Slave Address Status Register LPI2Cx_SASR Address Base address 150h offset Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R...

Page 1159: ...only field is reserved and always has the value 0 0 TXNACK Transmit NACK When NACKSTALL is set must be written once for each matching address byte and each received word Can also be written when LPI2C...

Page 1160: ...14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R SOF RXEMPTY 0 DATA W Reset 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LPI2Cx_SRDR field descriptions Field Description 31 16 Reserved This field is reserved This read only fi...

Page 1161: ...nd data hold time configurations The LPI2C master divides the functional clock by a prescaler and the resulting frequency must be at least eight times faster than the I2C bus bandwidth 45 4 1 2 Extern...

Page 1162: ...slave logic and registers to their default state except for the SCR itself 45 4 1 6 FIFO reset The LPI2C master implements write only control bits that resets the transmit FIFO MCR RTF and receive FIF...

Page 1163: ...e master code must be followed by a STOP or repeated START condition 45 4 2 2 Master Operation Whenever the LPI2C is enabled it monitors the I2C bus to detect when the I2C bus is idle MSR BBF The I2C...

Page 1164: ...wo bytes or against a masked data byte The data match function can also be configured to compare only the first one or two received data words since the last repeated START condition Receive data that...

Page 1165: ...the pin input digital filter setting which are configured separately for SCL and SDA divided by the prescaler since the pin input digital filters are not affected by the prescaler setting The followin...

Page 1166: ...0x0 0x0 0x02 0x05 0x03 0x01 The formula to calculate number of cycles per bit is as follows Baud rate divide CLKLO CLKHI 2 2 PRESCALER ROUNDDOWN 2 FILTSCL 2 PRESCALER This assumes SCL will pull high w...

Page 1167: ...ll up required in the I2C specification The LPI2C master also supports the output only push pull function required for I2C ultra fast mode using the LPI2C_SDA and LPI2C_SCL pins Support for ultra fast...

Page 1168: ...ered and only update during a slave transmit and slave receive transfer respectively The slave address that was received can be configured to be read from either the receive data register for example...

Page 1169: ...L hold time when clock stretching is enabled to increase setup time when sampling SDA externally SCL glitch filter time SDA glitch filter time The LPI2C slave imposes the following restrictions on the...

Page 1170: ...interrupt and LPI2C master transmit receive DMA requests Table 45 5 Master Interrupts and DMA Requests Flag Description Interrupt DMA Request Low Power Wakeup TDF Data can be written to transmit FIFO...

Page 1171: ...er is busy transmitting receiving data N N N BBF LPI2C master is enabled and activity detected on I2C bus but STOP condition has not been detected and bus idle timeout if enabled has not occurred N N...

Page 1172: ...data underrun receive data overrun or address status overrun when RXCFG 1 This flag can only set when clock stretching is disabled Y N Y AM0F Slave detected address match with ADDR0 field Y N N AM1F...

Page 1173: ...dress match It remains asserted until the next slave SCL pin negation 45 4 5 3 Input Trigger The LPI2C input trigger can be selected in place of the LPI2C_HREQ pin to control the start of a LPI2C mast...

Page 1174: ...le the TX Data SCL Stall and RX SCL Stall for clock stretching on SCL Enable Slave mode by set LPI2C0_SCR SEN Usage Guide Kinetis KE1xZ256 Sub Family Reference Manual Rev 3 07 2018 1174 NXP Semiconduc...

Page 1175: ...and VLPS mode provided the clock it is using remains enabled Table 46 1 LPUART Configuration TX FIFO word 10bit RX FIFO word 10bit Single wire mode LPUART0 4 4 Yes LPUART1 4 4 Yes LPUART2 4 4 Yes 46 1...

Page 1176: ...ARTx PCS see PCC chapter for detailed setting Registers Note this example figure also applies similarly to the clocking for LPSPI LPI2C and LPIT ASYNCH MODULE CLOCK only for LPUART not in other module...

Page 1177: ...Z format Programmable baud rates 13 bit modulo divider with configurable oversampling ratio from 4x to 32x Transmit and receive baud rate can operate asynchronous to the bus clock Baud rate can be con...

Page 1178: ...pporting 1 2 4 8 16 32 64 or 128 idle characters Selectable transmitter output and receiver input polarity Hardware flow control support for request to send RTS and clear to send CTS signals Selectabl...

Page 1179: ...XD Transmit data This pin is normally an output but is an input tristated in single wire mode whenever the transmitter is disabled or transmit direction is configured for receive data I O RXD Receive...

Page 1180: ...xD Direction TO TxD Pin Logic Loop Control To Receive Data In To TxD Pin Tx Interrupt Request LOOPS RSRC TIE TC TDRE M PT PE TCIE TE SBK T8 TXDIR Load From LPUARTx_D TXINV BRK13 ASYNCH MODULE CLOCK BA...

Page 1181: ...definition The LPUART includes registers to control baud rate select LPUART options report LPUART status and for transmit receive data Access to an address outside the valid memory map will generate...

Page 1182: ...aud Rate LPUART1_BAUD 32 RW 0F000004h 4006B014h LPUART Status LPUART1_STAT 32 RW 00C00000h 4006B018h LPUART Control LPUART1_CTRL 32 RW 00000000h 4006B01Ch LPUART Data LPUART1_DATA 32 RW 00001000h 4006...

Page 1183: ...This read only field returns the major version number for the module specification 23 16 MINOR Minor Version Number This read only field returns the minor version number for the module specification...

Page 1184: ...t 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 46 3 1 3 3 Fields Field Function 31 16 Reserved 15 8 RXFIFO Receive FIFO Size The number of words in the receive FIFO is 2 RXFIFO 7 0 TXFIFO Transmit FIFO Size The nu...

Page 1185: ...Reserved 1 RST Software Reset Reset all internal logic and registers except the Global Register Remains set until cleared by software 0 Module is not reset 1 Module is reset 0 Reserved 46 3 1 5 LPUAR...

Page 1186: ...erved 1 0 TRGSEL Trigger Select Configures the input trigger usage 00 Input trigger is disabled 01 Input trigger is used instead of RXD pin input 10 Input trigger is used instead of CTS_B pin input 11...

Page 1187: ...7 bit to 9 bit data characters 1 Receiver and transmitter use 10 bit data characters 28 24 OSR Oversampling Ratio This field configures the oversampling ratio for the receiver between 4x 00011 and 32x...

Page 1188: ...a word when a data one followed by data zero transition is detected This bit should only be changed when the receiver is disabled 0 Resynchronization during received data word is supported 1 Resynchro...

Page 1189: ...pin has occurred 29 MSBF MSB First Setting this bit reverses the order of the bits that are transmitted and received on the wire This bit does not affect the polarity of the bits the location of the...

Page 1190: ...detects the beginning of a valid start bit and RAF is cleared automatically when the receiver detects an idle line 0 LPUART receiver idle waiting for a start bit 1 LPUART receiver active RXD input no...

Page 1191: ...was detected 19 OR Receiver Overrun Flag OR is set when software fails to prevent the receive data register from overflowing with data The OR bit is set immediately after the stop bit has been comple...

Page 1192: ...trol CTRL 46 3 1 8 1 Address Register Offset CTRL Base address 18h offset 46 3 1 8 2 Function This read write register controls various optional features of the LPUART system This register should only...

Page 1193: ...character if any before the receiver starts receiving data from the TXD pin 0 TXD pin is an input in single wire mode 1 TXD pin is an output in single wire mode 28 TXINV Transmit Data Inversion Setti...

Page 1194: ...to place the LPUART receiver in a standby state RWU automatically clears when an RWU event occurs that is an IDLE event when CTRL WAKE is clear or an address match when CTRL WAKE is set with STAT RWUI...

Page 1195: ...he RSRC field determines the source for the receiver shift register input 0 Provided LOOPS is set RSRC is cleared selects internal loop back mode and the LPUART does not use the RXD pin 1 Single wire...

Page 1196: ...even or odd parity Odd parity means the total number of 1s in the data character including the parity bit is odd Even parity means the total number of 1s in the data character including the parity bi...

Page 1197: ...nsmitted instead of the contents in DATA T9 T0 T9 is used to indicate a break character when 0 and a idle character when 1 he contents of DATA T8 T0 should be zero 0 The dataword was received without...

Page 1198: ...er 5 4 R4T4 R4T4 Read receive data buffer 4 or write transmit data buffer 4 3 R3T3 R3T3 Read receive data buffer 3 or write transmit data buffer 3 2 R2T2 R2T2 Read receive data buffer 2 or write trans...

Page 1199: ...gister when the associated BAUD MAEN bit is clear 15 10 Reserved 9 0 MA1 Match Address 1 The MA1 and MA2 registers are compared to input data addresses when the most significant bit is set and the ass...

Page 1200: ...ength These can be configured by selecting the appropriate oversample ratio and pulse width 00 1 OSR 01 2 OSR 10 3 OSR 11 4 OSR 15 8 RTSWATER Receive RTS Configuration Configures the point at which th...

Page 1201: ...ter is placed into an empty transmitter data buffer RTS asserts one bit time before the start bit is transmitted RTS deasserts one bit time after all characters in the transmitter data buffer and shif...

Page 1202: ...uffer Overflow Flag Indicates that more data has been written to the transmit buffer than it can hold This field will assert regardless of the value of TXOFE However an interrupt will be issued to the...

Page 1203: ...9 TXOFE Transmit FIFO Overflow Interrupt Enable When this field is set the TXOF flag generates an interrupt to the host 0 TXOF flag does not generate an interrupt to the host 1 TXOF flag generates an...

Page 1204: ...datawords 010 Receive FIFO Buffer depth 8 datawords 011 Receive FIFO Buffer depth 16 datawords 100 Receive FIFO Buffer depth 32 datawords 101 Receive FIFO Buffer depth 64 datawords 110 Receive FIFO B...

Page 1205: ...r of datawords in the transmit FIFO buffer is equal to or less than the value in this register field an interrupt or a DMA request is generated For proper operation the value in TXWATER must be set to...

Page 1206: ...data is available in the transmit data buffer Programs store data into the transmit data buffer by writing to the LPUART data register The central element of the LPUART transmitter is the transmit sh...

Page 1207: ...rs A break character can also be transmitted by writing to the LPUART_DATA register with bit 13 set and the data bits clear This supports transmitting the break character as part of the normal data st...

Page 1208: ...h characters remaining in the receiver data buffer the character in the shift register is sent and TXD remains in the mark state until CTS_B is reasserted If the clear to send operation is disabled th...

Page 1209: ...n be matched to the polarity of the transceiver s driver enable signal TRANSMITTER UART RECEIVER DRIVER RS 485 TRANSCEIVER RECEIVER TXD RTS_B RXD DI DE RO RE_B Y Z A B Figure 46 4 Transceiver driver e...

Page 1210: ...ART receiver supports a configurable oversampling rate of between 4 and 32 of the baud rate clock for sampling The receiver starts by taking logic level samples at the oversampling rate times the baud...

Page 1211: ...eiver to ignore the characters in a message intended for a different receiver During receiver wakeup all receivers evaluate the first character s of each message and as soon as they determine the mess...

Page 1212: ...t data mode and the LPUART_BAUD SBNS bit selects 1 bit or 2 bit stop bit number that determines how many bit times of idle are needed to constitute a full character time 9 to 13 bit times because of t...

Page 1213: ...matches MATCH MA2 when BAUD MAEN2 is set 46 4 3 2 4 Address Match operation Address match operation is enabled when the LPUART_BAUD MAEN1 or LPUART_BAUD MAEN2 bit is set and LPUART_BAUD MATCFG is equa...

Page 1214: ...f both the LPUART_BAUD MAEN1 and LPUART_BAUD MAEN2 bits are negated the receiver operates normally and all data received is transferred to the receive data buffer Idle match operation functions in the...

Page 1215: ...asserts RTS_B when the number of characters in the receiver data register is not full and has not detected a start bit that will cause the receiver data register to be full It is not affected if STAT...

Page 1216: ...If the next bit is a 0 which arrives late then a low bit is detected according to Low bit detection The value sent to the receiver is changed from 1 to a 0 Then if a noise pulse occurs outside the re...

Page 1217: ...markers 46 4 4 2 Idle length An idle character is a character where the start bit all data bits and stop bits are in the mark postion The CTRL ILT register can be configured to start detecting an idl...

Page 1218: ...an IR LED and receiving narrow pulses and transforming them to serial bits which are sent to the LPUART The IrDA physical layer specification defines a half duplex infrared communication link for exch...

Page 1219: ...generate hardware interrupt requests Transmit data register empty LPUART_STAT TDRE indicates when there is room in the transmit data buffer to write another transmit character to LPUART_DATA If the t...

Page 1220: ...se flags are not set in overrun cases If LPUART_STAT RDRF was already set when a new character is ready to be transferred from the receive shifter to the receive data buffer the overrun LPUART_STAT OR...

Page 1221: ...nformation The FlexIO blocks are clocked from a single FlexIO clock that can be selected from OSCCLK SCGIRCLK SCGFIRCLK or SCGFCLK The selected source is controlled by the PCC_FLEXIO register in the P...

Page 1222: ...module BUS_CLK Peripheral Interface Clock PCC_LPUARTx PCS see PCC chapter for detailed setting Registers Note this example figure also applies similarly to the clocking for LPSPI LPI2C and LPIT ASYNCH...

Page 1223: ...L 4 bit field to use for starting the counter and or reloading the counter The trigger signal is from the FlexIO module itself which is called internal triggers or from other modules which is called e...

Page 1224: ...he FlexIO module is capable of supporting a wide range of protocols including but not limited to UART I2C SPI I2S PWM Waveform generation The following key features are provided Array of 32 bit shift...

Page 1225: ...xIO module supports the chip modes described in the following table Table 47 2 Chip modes supported by the FlexIO module Chip mode FlexIO Operation Run Normal operation Stop Wait Can continue operatin...

Page 1226: ...05_A014 Shifter Error Register FLEXIO_SHIFTERR 32 w1c 0000_0000h 47 3 6 1232 4005_A018 Timer Status Register FLEXIO_TIMSTAT 32 w1c 0000_0000h 47 3 7 1232 4005_A020 Shifter Status Interrupt Enable FLEX...

Page 1227: ...er FLEXIO_SHIFTBUFBIS3 32 R W 0000_0000h 47 3 15 1239 4005_A300 Shifter Buffer N Byte Swapped Register FLEXIO_SHIFTBUFBYS0 32 R W 0000_0000h 47 3 16 1239 4005_A304 Shifter Buffer N Byte Swapped Regist...

Page 1228: ...32 R W 0000_0000h 47 3 20 1244 4005_A50C Timer Compare N Register FLEXIO_TIMCMP3 32 R W 0000_0000h 47 3 20 1244 47 3 1 Version ID Register FLEXIO_VERID Address 4005_A000h base 0h offset 4005_A000h Bit...

Page 1229: ...mplemented 23 16 PIN Pin Number Number of Pins implemented 15 8 TIMER Timer Number Number of Timers implemented SHIFTER Shifter Number Number of Shifters implemented 47 3 3 FlexIO Control Register FLE...

Page 1230: ...gister accesses to FlexIO 1 SWRST Software Reset The FlexIO Control Register is not affected by the software reset all other logic in the FlexIO is affected by the software reset and register accesses...

Page 1231: ...urs For SMOD Receive the status flag is set when SHIFTBUF has been loaded with data from Shifter SHIFTBUF is full and the status flag is cleared when SHIFTBUF register is read For SMOD Transmit the st...

Page 1232: ...For SMOD Transmit indicates Shifter was ready to load new data from SHIFTBUF before new data had been written into SHIFTBUF SHIFTBUF Underrun For SMOD Match Store indicates a match event occured befo...

Page 1233: ...hen the 16 bit counter equals zero and decrements this also causes the counter to reload with the value in the compare register 0 Timer Status Flag is clear 1 Timer Status Flag is set 47 3 8 Shifter S...

Page 1234: ...bled 1 Shifter Error Flag interrupt enabled 47 3 10 Timer Interrupt Enable Register FLEXIO_TIMIEN Address 4005_A000h base 28h offset 4005_A028h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1...

Page 1235: ...hifter Status DMA Enable Enables DMA request generation when corresponding SSF is set 0 Shifter Status Flag DMA request is disabled 1 Shifter Status Flag DMA request is enabled 47 3 12 Shifter Control...

Page 1236: ...This read only field is reserved and always has the value 0 10 8 PINSEL Shifter Pin Select Selects which pin is used by the Shifter input or output 7 PINPOL Shifter Pin Polarity 0 Pin is active high...

Page 1237: ...hifter N 1 Output 7 Reserved This field is reserved This read only field is reserved and always has the value 0 6 Reserved This field is reserved This read only field is reserved and always has the va...

Page 1238: ...4 Shifter Buffer N Register FLEXIO_SHIFTBUFn Address 4005_A000h base 200h offset 4d i where i 0d to 3d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R SHIFT...

Page 1239: ...return SHIFTBUF 0 31 47 3 16 Shifter Buffer N Byte Swapped Register FLEXIO_SHIFTBUFBYSn Address 4005_A000h base 300h offset 4d i where i 0d to 3d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15...

Page 1240: ...FTBUF 0 7 47 3 18 Timer Control N Register FLEXIO_TIMCTLn Address 4005_A000h base 400h offset 4d i where i 0d to 3d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 TRGSEL TRGPOL TRGSRC 0 PINCF...

Page 1241: ...This read only field is reserved and always has the value 0 10 8 PINSEL Timer Pin Select Selects which pin is used by the Timer input or output 7 PINPOL Timer Pin Polarity 0 Pin is active high 1 Pin i...

Page 1242: ...only field is reserved and always has the value 0 25 24 TIMOUT Timer Output Configures the initial state of the Timer Output and whether it is affected by the Timer reset 00 Timer output is logic one...

Page 1243: ...Timer Disable Configures the condition that causes the Timer to be disabled and stop decrementing 000 Timer never disabled 001 Timer disabled on Timer N 1 disable 010 Timer disabled on Timer compare...

Page 1244: ...as the value 0 47 3 20 Timer Compare N Register FLEXIO_TIMCMPn Address 4005_A000h base 500h offset 4d i where i 0d to 3d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5...

Page 1245: ...re_data timer_shift_pos S FXIO_D0 S FXIO_Dn S synchronizer PINSEL SHIFTERi 1 out INSRC PINPOL PINPOL SHIFTERi out FXIO_D0 FXIO_Dn timer_shift_neg TIMPOL PINSEL PINCFG Figure 47 2 Shifter Microarchitec...

Page 1246: ...ll clear when the data has been read from the SHIFTBUF register The Shifter Error Flag SHIFTERR SEF and any enabled interrupts will set when an attempt to store data into a full SHIFTBUF register occu...

Page 1247: ...oading shifting and storing of the shift registers the counters load the contents of the compare register and decrement down to zero on the FlexIO clock They can perform generic timer functions such a...

Page 1248: ...clock after the timer starts decrementing If there is no falling edge on the shift clock before the first rising edge for example when TIMOUT 1 a shifter that is configured to shift on falling edge a...

Page 1249: ...finish A timer enable condition can be detected in the same cycle as a timer disable condition if timer stop bit is disabled or on the first rising edge of the shift clock after the disable condition...

Page 1250: ...Shifter Data Input the following synchronization delays occur 1 0 5 1 5 FlexIO clock cycles for external pin 2 1 FlexIO clock cycle for an internally driven pin For timing considerations such as outp...

Page 1251: ...g as inverted internal trigger source Can support CTS by configuring PINSEL 0x1 for Pin 1 and PINPOL 0x1 SHIFTBUFn Data to transmit Transmit data can be written to SHIFTBUF 7 0 to initiate an 8 bit tr...

Page 1252: ...quest Can support MSB first transfer by reading from SHIFTBUFBIS 7 0 register instead The UART Receiver with RTS configuration uses a 2nd Timer to generate the RTS output The RTS will assert when the...

Page 1253: ...rs and four Pins Either CPHA 0 or CPHA 1 can be supported and transfers can be supported using the DMA controller For CPHA 1 the select can remain asserted for multiple transfers and the timer status...

Page 1254: ...ransmit data can be written to SHIFTBUF use the Shifter Status Flag to indicate when data can be written using interrupt or DMA request Can support MSB first transfer by writing to SHIFTBUFBBS registe...

Page 1255: ...request Can support MSB first transfer by writing to SHIFTBUFBBS register instead SHIFTBUF n 1 Data to receive Received data can be read from SHIFTBUFBYS use the Shifter Status Flag to indicate when d...

Page 1256: ...t transfer by writing to SHIFTBUFBBS register instead SHIFTBUF n 1 Data to receive Received data can be read from SHIFTBUFBYS use the Shifter Status Flag to indicate when data can be read using interr...

Page 1257: ...re enabling SCL generation Data transfers can be supported using the DMA controller and the shifter error flag will set on transmit underrun or receive overflow The first timer generates the bit clock...

Page 1258: ...bled logic 0 and stop bit enabled logic 1 SHIFTCTLn 0x0101_0082 Configure transmit using Timer 1 on rising edge of clock with inverted output enable open drain output on Pin 0 SHIFTCFG n 1 0x0000_0020...

Page 1259: ...e of the FlexIO clock frequency and the initial frame sync assertion occurs at the same time as the first bit clock edge The timer uses the start bit to ensure the frame sync is generated one clock cy...

Page 1260: ...er by writing to SHIFTBUF register instead SHIFTBUF n 1 Data to receive Received data can be read from SHIFTBUFBIS use the Shifter Status Flag to indicate when data can be read using interrupt or DMA...

Page 1261: ...n 1 0x0000_003F Configure 32 bit transfers Set TIMCMP 15 0 number of bits x 2 1 TIMCFG n 1 0x0020_3500 Configure enable on pin rising edge with trigger high and disable on compare with trigger low in...

Page 1262: ...ing Interrupt DMA Method Buffer Shifter UART Receive Trigger RX Pin 31 30 29 28 3 2 1 0 31 30 29 28 3 2 1 0 Timer Shift and Store Control FlexIO Clock Reading Buffer Using Polling Interrupt DMA Method...

Page 1263: ...d Disablement MISO Pin SCK Pin Trigger Timer Output Timer Output FlexIO Clock Load and Shift Control Buffer Shifter Buffer Shifter Reading Buffer Using Polling Interrupt DMA Method Writing Buffer Usin...

Page 1264: ...I Pin SCK Pin Decrement Source Shift and Store Control Load and Shift Control Reading Buffer Using Polling Interrupt DMA Method Writing Buffer Using Polling Interrupt DMA Method Buffer Shifter Buffer...

Page 1265: ...er Timer Output FlexIO Clock Shift and Store Control Load and Shift Control Reading Buffer Using Polling Interrupt DMA Method Writing Buffer Using Polling Interrupt DMA Method Buffer Shifter Buffer Sh...

Page 1266: ...put FS Pin Enablement FlexIO Clock Shift and Store Control Load and Shift Control Buffer Shifter Buffer Shifter Reading Buffer Using Polling Interrupt DMA Method Writing Buffer Using Polling Interrupt...

Page 1267: ...ment FS Pin Shift and Store Control Load and Shift Control Buffer Shifter Buffer Shifter Reading Buffer Using Polling Interrupt DMA Method Writing Buffer Using Polling Interrupt DMA Method RX_DATA Pin...

Page 1268: ...Usage Guide Kinetis KE1xZ256 Sub Family Reference Manual Rev 3 07 2018 1268 NXP Semiconductors...

Page 1269: ...nnel can be enabled to be the wakeup source TS I hardware trigger is from the TRGMUX Table 48 1 TSI module functionality in MCU operation modes MCU operation mode TSI clock sources TSI operation mode...

Page 1270: ...SCG module SCG DIVSLOW TSI module BUS_CLK Peripheral Interface Clock Registers Main Clock internal 48 1 3 Inter connectivity Information The TSI inter connectivity is shown in the following diagram Ch...

Page 1271: ...mode to achieve low power high sensitivity and advanced EMC robustness It supports both of self cap and mutual cap sensors In self cap mode the TSI requires only one pin for each touch sensor In mutu...

Page 1272: ...following operation modes Table 48 2 Operating modes Mode Description Stop and low power stop TSI module is fully functional in all of the stop modes as long as TSI_GENCS STPE is set The channel speci...

Page 1273: ...p sensing Name Port Direction Function Reset state TSI 24 0 TSI I O TSI sensing pins or GPIO pins I O Table 48 4 TSI signal description mutual cap sensing Name Port Direction Function Reset state TSI...

Page 1274: ...tion This section describes the memory map and control status registers for the TSI module TSI memory map Absolute address hex Register name Width in bits Access Reset value Section page 4004_5000 TSI...

Page 1275: ...e 0h offset 4004_5000h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R OUTRGF 0 ESO R 0 DVOLT 0 W w1c Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R TSI_ANA_TE...

Page 1276: ...dvolt 2 0V 18 16 Reserved This field is reserved This read only field is reserved and always has the value 0 15 13 TSI_ANA_TEST TSI_ANA_TEST These bits can only be accessed when in test mode 12 RUN_C...

Page 1277: ...e 1 when this flag is set to clear it 0 Scan not complete 1 Scan complete 1 Reserved This field is reserved This read only field is reserved and always has the value 0 0 EOSDMEO End of Scan DMA Transf...

Page 1278: ...ode TSI_GENCS STM 0 the scan starts immediately when TSI_DATA SWTS bit is written by 1 00000 For self cap mode Channel 0 00001 For self cap mode Channel 1 00010 For self cap mode Channel 2 00011 For s...

Page 1279: ...tware Trigger Start This write only bit is a software start trigger When STM bit is clear write 1 to this bit will start a scan The electrode channel to be scanned is determined by TSI_DATA TSICH bits...

Page 1280: ...0 SETCLK 0 MODE S_NOISE W Reset 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 TSI_MODE field descriptions Field Description 31 Reserved This field is reserved This read only field is reserved and always has the va...

Page 1281: ...XIN S_XIN Input current multiple 0 1 8 1 1 4 17 15 Reserved This field is reserved This read only field is reserved and always has the value 0 14 12 S_XCH S_XCH Charge Discharge current multiple 000 1...

Page 1282: ...4004_5000h base 10h offset 4004_5010h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R M_PRE_CURRENT 0 Reserved 0 M_TX_USED W Reset 0 1 1 0 0 0 0 0 0 0 1 1 1 1 1 1 Bit 15 14 13 12 11 10 9 8 7 6...

Page 1283: ...ans used for mutual cap value 0 means used for GPIO 15 13 M_PRE_RES M_PRE_RES choose the resistor used in pre charge default 4k 000 1k 001 2k 010 3k 011 4k 100 5k 101 6k 110 7k 111 8k 12 Reserved This...

Page 1284: ...11 select channel 3 as tx3 100 select channel 4 as tx4 101 select channel 5 as tx5 110 NA 111 NA 3 Reserved This field is reserved This read only field is reserved and always has the value 0 M_SEL_RX...

Page 1285: ...TSI_MUL1 field descriptions Field Description 31 24 Reserved This field is reserved This read only field is reserved and always has the value 0 23 19 M_SEN_BOOST M_SEN_BOOST Choose the sensitivity boo...

Page 1286: ...8 M_TRIM2 M_TRIM2 M_TRIM2 7 0 is for trim use For M_TRIM2 0 value 0 choose Vref as source of Vp Vm Vmid value 1 choose Vpre in mutual AFE as source of Vp Vm Vmid When this bit is set to 1 it will cho...

Page 1287: ...1 01 m 2 10 m 3 11 m 4 2 1 M_NMIRROR M_NMIRROR NMOS current mirror default m 4 00 m 1 01 m 2 10 m 3 11 m 4 0 M_NMIR_CTRL M_NMIR_CTRL NMOS mirror control signal default enable 0 Enable NMOS mirror 1 D...

Page 1288: ...00h base 18h offset 4004_5018h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 CUTOFF 0 ORDER DECIMATION W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 Register definition Kinetis KE1xZ256 Sub Family...

Page 1289: ...field is reserved and always has the value 0 27 24 CUTOFF CUTOFF The value of shifting out lower bits of counter equal to divide the result by div default div 0 0000 div 1 0001 div 2 0010 div 4 0011 d...

Page 1290: ...DATA TSICNT bits is the counter value of 13 scan periods 01101 The TSI_DATA TSICNT bits is the counter value of 14 scan periods 01110 The TSI_DATA TSICNT bits is the counter value of 15 scan periods 0...

Page 1291: ...t in TSI_DATA TSICNT has an overflow occurrence in the last scan process Note this bit has no default value please force it to 0 or deposit it if necessary 0 The counter result has no overflow occurre...

Page 1292: ...d 0000 NC 0001 NC 0010 The length of the PRBS is 2 0011 The length of the PRBS is 3 0100 The length of the PRBS is 4 0101 The length of the PRBS is 5 0110 The length of the PRBS is 6 0111 The length o...

Page 1293: ...t 0 s period will be 12 clock cycles of system clock 1100 The SSC output bit 0 s period will be 13 clock cycles of system clock 1101 The SSC output bit 0 s period will be 14 clock cycles of system clo...

Page 1294: ...ister 0 TSI_SSC1 Address 4004_5000h base 20h offset 4004_5020h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R PRBS_WEIGHT_HI PRBS_WEIGHT_LO PRBS_SEED_HI PR...

Page 1295: ...period will be 3 TSI_SSC0 BASE_ NOCHARGE_NUM clock cycles of system clock 0011 The SSC output bit 1 s min period will be 4 TSI_SSC0 BASE_ NOCHARGE_NUM clock cycles of system clock 0100 The SSC output...

Page 1296: ...p down counter is 1 010 The added value for up down counter is 2 011 The added value for up down counter is 3 100 The added value for up down counter is 4 101 The added value for up down counter is 5...

Page 1297: ...0pF as usual Cs Touch generated self capacitance 0 3pF 2pF as usual Sensitivity of sensor Cs Cs 1 10 as usual Intrinsic performance depends on electrode pattern design thickness dielectric of overlay...

Page 1298: ...sor Cm Cm 1 20 as usual Intrinsic performance depends on electrode pattern design thickness dielectric of overlay and PCB routing 48 5 2 Brief timing and Operation of TSI TSI works by switching integr...

Page 1299: ...p mutual cap value and generates voltage steps on integration capacitor The step voltage depends on touch sensor and IP configuration Once the step voltage VCI reach threshold Vp of comparator the int...

Page 1300: ...analog power supply voltage Typical 3 3V S_XIN S_XCH is parameter of analog front end which can be configured by S_XIN 2 0 S_XCH 2 0 Fsw is the switching frequency which is controlled by SSC Spread S...

Page 1301: ...wer supply voltage Typical 1 2V During noise cancellation mode vdd3v and vddlv are dual sample voltages Analog front end samples twice which includes charging phase sampling vdd3v and discharging phas...

Page 1302: ...90pF Vp Vm dual reference voltage which can be configured by DVOLT 1 0 Fsw is the switching frequency which is controlled by SSC Spread Spectrum Clocking block Tsw is the switching period and Tsw 1 F...

Page 1303: ...s The TSI_GENCS TSIEN bit must be set to enable the TSI module in run and wait mode When TSI_GENCS STPE bit is set it allows the TSI module to work in low power mode 48 5 6 Software and hardware trigg...

Page 1304: ...ten emission energy In addition the frequency of switching clock can be configured by TSI_SSC0 TSI_SSC1 and TSI_SSC2 Refer to chapter Spread spectrum clocking for details The clock source of SSC is fr...

Page 1305: ...ference voltages are configurable upon the setting of TSI_GENCS DVOLT The following table shows the all the delta voltage configurations Table 48 5 Delta voltage configuration DVOLT Vp V Vm V V V 00 0...

Page 1306: ...FFFF is treated as an extreme case the out of range will not happen Also in noise detection mode the out of range will not assert either 48 5 12 Wake up MCU from low power modes In low power modes onc...

Page 1307: ...cy noises With this SSC the noises that frequency is nearing sampling frequency can be spanned to a wider frequency range instead of a single peak frequency noise and only parts of the noise is overla...

Page 1308: ...HARGE_NUM Figure 48 9 Spread spectrum clocking timing The upper figure is presenting the timing of input system clock and the SSC output bit t1 controlled by component 3 and TSI_SSC0 BASE_NOCHARGE_NUM...

Page 1309: ...errupt occurs read the TSI status register to determine the exact interrupt source 48 6 2 How to use TSI module There are several steps as below Initiate TSI module by configuring registers Start TSI...

Page 1310: ...cap mode one touch key is connected to one TSI channel which is measured at each TSI scan round The following figure shows the software flowchart of TSI scan example in Self cap mode Usage Guide Kinet...

Page 1311: ...nnected to 2 TSI channels i e the transmitter and the receiver channel respectively The figure below shows the software flowchart of TSI scan example in Mutual cap mode Chapter 48 Touch Sensing Input...

Page 1312: ...h key is touched by finger the TSI scan result TSI_DATA TSICNT changes a lot By comparing the changed value the touch event can be determined The following figure shows an example of detecting a touch...

Page 1313: ...cess NOTE For touch electrode hardware design guideline please refer to AN3863 Designing Touch Sensing Electrodes Chapter 48 Touch Sensing Input TSI Kinetis KE1xZ256 Sub Family Reference Manual Rev 3...

Page 1314: ...Usage Guide Kinetis KE1xZ256 Sub Family Reference Manual Rev 3 07 2018 1314 NXP Semiconductors...

Page 1315: ...1 Revision History Rev No Date Substantial Changes 2 09 2016 Initial public release 3 07 2018 Some major updates after the market launch version rev2 see the Appendix Change Summary for This Revision...

Page 1316: ...Kinetis KE1xZ256 Sub Family Reference Manual Rev 3 07 2018 1316 NXP Semiconductors...

Page 1317: ...oduction chapter changes No substantial content changes B 3 Core Overview chapter changes No substantial content changes B 4 Interrupts chapter changes No substantial content changes B 5 SIM chapter c...

Page 1318: ...changes B 9 Crossbar switch module changes No substantial content changes B 10 AIPS Lite module changes No substantial content changes B 11 TRGMUX chapter changes No substantial content changes B 12 D...

Page 1319: ...Interfaces chapter for amount of flash memory Cosmetic changes Update EEPROM implementation description to include impact of VLP mode B 17 Clock Distribution chapter changes Updated the section High L...

Page 1320: ...Modes of Operation Table is Visible This table outlines the SCG clock source conditions that should be met for each mode of operation Re worded slightly the information regarding the valid reset value...

Page 1321: ...anagement chapter B 25 System Mode Controller changes SMC No substantial content changes B 26 PMC changes No substantial content changes B 27 Security chapter changes No substantial content changes B...

Page 1322: ...ges B 33 Signal Multiplexing and Pin Assignment chapter changes No substantial content changes B 34 Port Control and Interrupts PORT changes No substantial content changes B 35 GPIO changes No substan...

Page 1323: ...3A 3B section Deleted the redundant text FILT_PER in the Comparator module block diagram figure and other figures under the CMP functional modes section B 38 PDB changes To Status and Control Register...

Page 1324: ...bstantial content changes B 47 FlexIO changes No substantial content changes B 48 TSI changes Added a note in the External signal description section B 49 Other major changes throughout the document M...

Page 1325: ...no liability for any vulnerability that is discovered Customers should implement appropriate design and operating safeguards to minimize the risks associated with their applications and products NXP t...

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