NXP Semiconductors Kinetis KE1xZ256, Reference Manual

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MMDVSQ_CSR field descriptions (continued)
Field Description
hardware automatically clears the indicator. This bit can be used to poll the DVSQ’s execution status. The
combined CSR[BUSY, DIV, SQRT] indicators provide an encoded module status:
• If 0b001, then MMDVSQ is idle and the last calculation was a square root
• If 0b010, then MMDVSQ is idle and the last calculation was a divide
• If 0b101, then MMDVSQ is busy processing a square root calculation
• If 0b110, then MMDVSQ is busy processing a divide calculation
The remaining encodings of CSR[BUSY, DIV, SQRT] are reserved.
0 MMDVSQ is idle
1 MMDVSQ is busy performing a divide or square root calculation
30
DIV
DIVIDE
Current or last operation was a divide. This read-only indicator bit signals if the current or last operation
performed by the MMDVSQ was a divide.
0 Current or last MMDVSQ operation was not a divide
1 Current or last MMDVSQ operation was a divide
29
SQRT
SQUARE ROOT
Current or last operation was a square root. This read-only indicator bit signals if the current or last
operation performed by the MMDVSQ was a square root.
0 Current or last MMDVSQ operation was not a square root
1 Current or last MMDVSQ operation was a square root
28–6
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
5
DFS
Disable Fast Start
The MMDVSQ supports 2 mechanisms for initiating a divide operation. The default mechanism is a “fast
start” where a write to the DSOR register begins the divide. Alternatively, the start mechanism can begin
after a write to the CSR register with CSR[SRT] set. The CSR[DFS] indicator selects the divide start
mechanism.
0 A divide operation is initiated by a write to the DSOR register
1 A divide operation is initiated by a write to the CSR register with CSR[SRT] = 1
4
DZ
Divide-by-Zero
This read-only status indicator signals the last divide operation had a zero divisor, that is, DSOR =
0x0000_0000. For this case, RES is set to 0x0000_0000 and this indicator bit set. After a divide-by-zero
operation, a read of the RES register returns either the zero result, or, if CSR[DZE] = 1, terminates the
read with an error. The CSR[DZ] indicator is cleared by the hardware at the beginning of each operation.
0 The last divide operation had a non-zero divisor, that is, DSOR != 0
1 The last divide operation had a zero divisor, that is, DSOR = 0
3
DZE
Divide-by-Zero-Enable
This indicator configures the MMDVSQ’s response to divide-by-zero calculations. If both CSR[DZ] and
CSR[DZE] are set, then a subsequent read of the RES register is error terminated to signal the processor
of the attempted divide-by-zero.
Table continues on the next page...
Chapter 6 Memory-Mapped Divide and Square Root (MMDVSQ)
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
NXP Semiconductors 87