NXP Semiconductors Kinetis KE1xZ256, Reference Manual

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38.4.10 Pulse-Out n Delay register (PDBx_POnDLY)
Note: This register is internally buffered, and any values written to the register are
written to its internal buffer instead; in other words, the internal device bus does not write
directly to this register. The value in this register's internal buffer is loaded into this
register only after "1" is written to the SC[LDOK] bit.
Address: 4003_6000h base + 194h (4d × i), where i=0d to 1d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
DLY1 DLY2
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PDBx_POnDLY field descriptions
Field Description
31–16
DLY1
PDB Pulse-Out Delay 1
Specifies the delay 1 value for the PDB Pulse-Out. Pulse-Out goes high when the PDB counter is equal to
the DLY1. Reading this field returns the value of internal register that is effective for the current PDB cycle.
DLY2 PDB Pulse-Out Delay 2
Specifies the delay 2 value for the PDB Pulse-Out. Pulse-Out goes low when the PDB counter is equal to
the DLY2. Reading this field returns the value of internal register that is effective for the current PDB cycle.
38.5 Functional description
38.5.1 PDB pre-trigger and trigger outputs
The PDB contains a counter whose output is compared to several different digital values.
If the PDB is enabled, then a trigger input event will reset the counter and make it start to
count. A trigger input event is defined as a rising edge being detected on a selected
trigger input source, or if a software trigger is selected and the Software Trigger bit
(SC[SWTRIG]) is written with 1. For each channel, a delay m determines the time
between assertion of the trigger input event to the time at which changes in the pre-
trigger m output signal are started. The time is defined as:
Chapter 38 Programmable Delay Block (PDB)
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
NXP Semiconductors 837