NXP Semiconductors Kinetis KE1xZ256, Reference Manual

Page: 400 / 1325

SCG_LPFLLCFG field descriptions (continued)
Field Description
00 LPFLL is trimmed to 48 MHz
01
LPFLL is trimmed to 72 MHz
10
Reserved
11
Reserved
18.3.21 Low Power FLL Trim Configuration Register
(SCG_LPFLLTCFG)
The LPFLLTCFG register cannot be changed when LPFLL tuning is enabled. When the
LPFLL tuning is enabled, writes to this register are ignored, and there is no transfer error.
Address: 4006_4000h base + 50Ch offset = 4006_450Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
LOCKW2LSB
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
TRIMDIV
0
TRIMSRC
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SCG_LPFLLTCFG field descriptions
Field Description
31–17
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
16
LOCKW2LSB
Lock LPFLL with 2 LSBS
This bitfield is used to control the condition to set LPFLLTRMLOCK: difference between LPFLL actual
clock and target clock (48 MHz, 72 MHz) is within 0.8% or 0.4%;
0 LPFLL locks within 1LSB (0.4%)
1 LPFLL locks within 2LSB (0.8%)
15–13
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
12–8
TRIMDIV
LPFLL Trim Predivide
Table continues on the next page...
Memory Map/Register Definition
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
400 NXP Semiconductors