NXP Semiconductors Kinetis KE1xZ256, Reference Manual

Page: 1155 / 1325

LPI2Cx_SCFGR1 field descriptions (continued)
Field Description
Configures the condition that will cause an address to match.
000 Address match 0 (7-bit).
001 Address match 0 (10-bit).
010 Address match 0 (7-bit) or Address match 1 (7-bit).
011 Address match 0 (10-bit) or Address match 1 (10-bit).
100 Address match 0 (7-bit) or Address match 1 (10-bit).
101 Address match 0 (10-bit) or Address match 1 (7-bit).
110 From Address match 0 (7-bit) to Address match 1 (7-bit).
111 From Address match 0 (10-bit) to Address match 1 (10-bit).
15–14
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
13
HSMEN
High Speed Mode Enable
Enables detection of the High-speed Mode master code of slave address 0000_1XX, but does not cause
an address match on this code. When set and any Hs-mode master code is detected, the FILTEN and
ACKSTALL bits are ignored until the next STOP condition is detected.
0 Disables detection of Hs-mode master code.
1 Enables detection of Hs-mode master code.
12
IGNACK
Ignore NACK
When set, the LPI2C slave will continue transfers after a NACK is detected. This bit is required to be set in
Ultra-Fast Mode.
0 Slave will end transfer when NACK detected.
1 Slave will not end transfer when NACK detected.
11
RXCFG
Receive Data Configuration
0 Reading the receive data register will return receive data and clear the receive data flag.
1 Reading the receive data register when the address valid flag is set will return the address status
register and clear the address valid flag. Reading the receive data register when the address valid flag
is clear will return receive data and clear the receive data flag.
10
TXCFG
Transmit Flag Configuration
The transmit data flag will always assert before a NACK is detected at the end of a slave-transmit transfer.
This can cause an extra word to be written to the transmit data FIFO.
When TXCFG=0, the transmit data register is automatically emptied when a slave-transmit transfer is
detected. This cause the transmit data flag to assert whenever a slave-transmit transfer is detected and
negate at the end of the slave-transmit transfer.
When TXCFG=1, the transmit data flag will assert whenver the transit data register is empty and negate
when the transmit data register is full. This allows the transmit data register to be filled before a slave-
transmit transfer is detected, but can cause the transmit data register to be written before a NACK is
detected on the last byte of a slave transmit transfer.
0 Transmit Data Flag will only assert during a slave-transmit transfer when the transmit data register is
empty.
1 Transmit Data Flag will assert whenever the transmit data register is empty.
9
SAEN
SMBus Alert Enable
Table continues on the next page...
Chapter 45 Low Power Inter-Integrated Circuit (LPI2C)
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
NXP Semiconductors 1155