NXP Semiconductors KE1xF Series, Reference Manual, Page: 91 / 1483

6.2.4 Interrupt Status and Control Register (MCM_ISCR)
The MCM_ISCR register defines the configuration and reports status for a number of
core-related interrupt exception conditions. It includes the enable and status bits
associated with the core’s floating-point exceptions, and bus errors associated with the
core’s cache write buffer. The individual event indicators are first qualified with their
exception enables and then logically summed to form an interrupt request sent to the
core’s NVIC.
Bits 15-8 are read-only indicator flags based on the processor’s FPSCR register.
Attempted writes to these bits are ignored. Once set, the flags remain asserted until
software clears the corresponding FPSCR bit.
Address: E008_0000h base + 10h offset = E008_0010h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
FIDCE
0
FIXCE
FUFCE FOFCE FDZCE
FIOCE
0
CWBEE
0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
FIDC
0
FIXC
FUFC FOFC FDZC
FIOC
0
CWBER
0
W
w1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MCM_ISCR field descriptions
Field Description
31
FIDCE
FPU input denormal interrupt enable
Table continues on the next page...
Chapter 6 Miscellaneous Control Module (MCM)
Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019
NXP Semiconductors 91