NXP Semiconductors KE1xF Series, Reference Manual, Page: 93 / 1483

MCM_ISCR field descriptions (continued)
Field Description
0 No interrupt
1 Interrupt occurred
11
FUFC
FPU underflow interrupt status
This read-only bit is a copy of the core’s FPSCR[UFC] bit and signals an underflow has been detected in
the processor’s FPU. Once set, this bit remains set until software clears the FPSCR[UFC] bit.
0 No interrupt
1 Interrupt occurred
10
FOFC
FPU overflow interrupt status
This read-only bit is a copy of the core’s FPSCR[OFC] bit and signals an overflow has been detected in
the processor’s FPU. Once set, this bit remains set until software clears the FPSCR[OFC] bit.
0 No interrupt
1 Interrupt occurred
9
FDZC
FPU divide-by-zero interrupt status
This read-only bit is a copy of the core’s FPSCR[DZC] bit and signals a divide by zero has been detected
in the processor’s FPU. Once set, this bit remains set until software clears the FPSCR[DZC] bit.
0 No interrupt
1 Interrupt occurred
8
FIOC
FPU invalid operation interrupt status
This read-only bit is a copy of the core’s FPSCR[IOC] bit and signals an illegal operation has been
detected in the processor’s FPU. Once set, this bit remains set until software clears the FPSCR[IOC] bit.
0 No interrupt
1 Interrupt occurred
7–5
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
4
CWBER
Cache write buffer error status
Signals a data transfer from the core’s cache write buffer was terminated with a bus error. This bit only
sets when the corresponding enable bit (CWBEE) is set. The corresponding core fault address, attributes
and write data are typically retrieved from the FADR, FATR, and FDR registers during the interrupt service
routine before clearing the CWBER flag.
0 No error
1 Error occurred
Reserved This field is reserved.
This read-only field is reserved and always has the value 0.
Chapter 6 Miscellaneous Control Module (MCM)
Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019
NXP Semiconductors 93