NXP Semiconductors KE1xF Series, Reference Manual, Page: 92 / 1483

MCM_ISCR field descriptions (continued)
Field Description
0 Disable interrupt
1 Enable interrupt
30–29
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
28
FIXCE
FPU inexact interrupt enable
0 Disable interrupt
1 Enable interrupt
27
FUFCE
FPU underflow interrupt enable
0 Disable interrupt
1 Enable interrupt
26
FOFCE
FPU overflow interrupt enable
0 Disable interrupt
1 Enable interrupt
25
FDZCE
FPU divide-by-zero interrupt enable
0 Disable interrupt
1 Enable interrupt
24
FIOCE
FPU invalid operation interrupt enable
0 Disable interrupt
1 Enable interrupt
23–21
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
20
CWBEE
Cache write buffer error enable
Enables the generation of an interrupt in response to a bus error termination reported on a system bus
transfer initiated from the cache’s write buffer.
0 Disable error interrupt
1 Enable error interrupt
19–16
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
15
FIDC
FPU input denormal interrupt status
This read-only bit is a copy of the core’s FPSCR[IDC] bit and signals input denormalized number has been
detected in the processor’s FPU. Once set, this bit remains set until software clears the FPSCR[IDC] bit.
0 No interrupt
1 Interrupt occurred
14–13
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
12
FIXC
FPU inexact interrupt status
This read-only bit is a copy of the core’s FPSCR[IXC] bit and signals an inexact number has been
detected in the processor’s FPU. Once set, this bit remains set until software clears the FPSCR[IXC] bit.
Table continues on the next page...
Memory map/register descriptions
Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019
92 NXP Semiconductors