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NXP Semiconductors freescale MC92604, User Manual

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Connector Signals

MC92604 Dual GEt Design Verification Board User’s Guide, Rev. 1

A-8

Freescale Semiconductor

A.5

SFP_CTRL Connector

The control signals for the small form-factor pluggable (SFP) socket are available on the 2 row by 8, 
SFP_CTRL (PG12) connector as listed in 

Table A-9

. These are standard signals for the multiple source 

agreement (MSA) fiber optic modules. The TX_DISABLE pin must be low for the module to operate.

Table A-9. SFP_CTRL Connector 

Connector

Pin

SFP Module

Pin

Input Signal

Name

Description

1

N/C

—

—

3

N/C

—

—

5

N/C

—

—

7

6

MOD_DEF_0

Module definition 0

9

5

MOD_DEF_1

Module definition 1

11

4

MOD_DEF_2

Module definition 2

13

7

RATE_SELECT

Rate select. Not connected in most SFPs.

15

3

TX_DISABLE

SFP transmitter disable

Summary of Contents for freescale MC92604

Page 1: ...MC92604 Dual GEt Design Verification Board User s Guide MC92604DVBUG Rev 1 06 2005...

Page 2: ...Blank...

Page 3: ...B Package Contents 2 1 2 3 Hardware Preparation 2 2 2 3 1 Setting the Power Supply and Voltage Regulators 2 3 2 3 2 Setting the Voltage Regulators 2 3 2 4 Reference Clock Source 2 3 2 4 1 Using the On...

Page 4: ...3 Quick Setup BERC Test Procedure 3 9 Chapter 4 Test Setups 4 1 Serial Link Verification Using a Serial Bit Error Rate Tester BERT 4 1 4 1 1 Test Setup for Full Speed Mode 4 2 4 1 2 Test Setup for Hal...

Page 5: ...ion Board User s Guide Rev 1 Freescale Semiconductor v Paragraph Page Number Title Number Appendix C Prescaler for Jitter Measurement C 1 Divide by xx Prescaler Description C 1 C 2 Prescaler Component...

Page 6: ...MC92604 Dual GEt Design Verification Board User s Guide Rev 1 vi Freescale Semiconductor blank...

Page 7: ...ck any or all features functions of the MC92604 GEt device The two parallel data input ports and all configuration control signal pins are accessed through common 2 10 0 100 male connectors headers Th...

Page 8: ...mpedance of representative board traces Connectors provided for JTAG and MDIO ports SFP socket provided for MSA compliant fiber modules IEEE Std 1394b bilingual socket provided for standard cable link...

Page 9: ...td 802 3 2002 Part 3 Carrier sense multiple access with collision detection CSMA CD access method and physical layer specifications Table 1 2 Acronyms and Abbreviated Terms Term Meaning 1 High logic l...

Page 10: ...s JTAG Control RECV_B RECV_A XMIT_A XMIT_B MDIO 2 10 0 100 SW1 Connectors CLK_IN RLINK_A RLINK_B XLINK_A XLINK_B TST1 TST2 TST5 TST6 TST3 TST7 TST4 TST8 0 100 Connector VDDQ GND R22V1 R12V 3 3 V TPA G...

Page 11: ...rs LA1 LA2 provide access to the parallel outputs 2 x 8 0 100 connectors PG12 and PG14 provide access to the SFP connector and VDD ground planes respectively SMA connectors SMA1 SMA8 Serial transmit a...

Page 12: ...General Information MC92604 Dual GEt Design Verification Board User s Guide Rev 1 1 6 Freescale Semiconductor...

Page 13: ...ng carton Refer to the packing list and verify that all items are present Save the packing material for storing and reshipping of the equipment 2 2 MC92604DVB Package Contents Table 2 1 describes the...

Page 14: ...tors Crystal Oscillator Clock Buffers DIP Switch 50 Vertical Test Traces 2 10 Connectors 2 8 Connector 3 3 V Power Connection 2 20 Connectors 2 8 Connector 2 10 Connectors Serial Differential SMA Conn...

Page 15: ...ry This voltage level is determined by the desired logic interface The supply can be adjusted using the R22V1 potentiometer from a nominal 2 5 to 3 3 V The 3 3 V 1 8 V and VDDQ supplies are accessible...

Page 16: ...h types of crystal oscillators are available from external vendors in a variety of frequencies The DVB may be shipped with either the Y1 or the Y2 oscillator installed When using the Y2 oscillator the...

Page 17: ...ended 3 3 V LVTTL CMOS level shift These CMOS outputs are series terminated on the board then connect to the SMA connectors labeled 3 3V_CLK_OUT1 3 3V_CLK_OUT2 3 3V_CLK_OUT3 and 3 3V_CLK_OUT4 All of t...

Page 18: ...components 2 5 1 Parallel Inputs and Outputs The MC92604 parallel I O is supplied by the VDDQ voltage regulator set for 2 5 or 3 3 V and has a rail to rail signal swing The MC92604DVB is shipped with...

Page 19: ...Connector Signals Note that all even number pins are connected to ground Figure 2 5 2 20 0 100 Output Connector Number Scheme Top View For information regarding the MC92604 outputs refer to the MC926...

Page 20: ...with standard patch cords Note that there is a slight impedance mismatch as the 1394 cables are 110 differential 2 7 Special Test Connection The MC92604DVB also contains an oscilloscope PCB test socke...

Page 21: ...d Details of testing in specific systems is left to the user For more information regarding the MC92604 feature set refer to the MC92604 Dual Gigabit Ethernet Transceiver Reference Guide 3 1 Recommend...

Page 22: ...nd SMA 50 feed through terminations 5 16 torque wrench fits SMA 2 9 and 3 5 mm connectors Bias T networks Power splitters BNC to SMA adapters SMA female to SMA female adapters SMA male to SMA male ada...

Page 23: ...it PN generator uses the following polynomial Stimulus from this generator may also be used for further system testing Refer to the MC92604 Dual Gigabit Ethernet Transceiver Reference Guide for more i...

Page 24: ...sted pins are not connected All the signal pins on the five connectors CNTRL_SIG_0 CNTRL_SIG_1 CNTRL_SIG_2 JTAG and MDIO have 10K pullup resistors to VDDQ By making no connection N C to any of these p...

Page 25: ...D 19 GND N C 19 GND N C 19 GND N C A_XMIT A_XCLK JTAG 1 XMIT_A_0 GND 1 GTX_CLK_0 N C 1 N C 3 XMIT_A_1 GND 3 N C 3 N C 5 XMIT_A_2 GND 5 XCVR_A_DISABLE GND 5 N C 7 XMIT_A_3 GND 7 N C 7 N C 9 XMIT_A_4 GN...

Page 26: ...ltage levels 3 Verify that the reference clock frequency at CLK_OUT1 is 125 MHz period 8 0 ns 4 Observe XMIT_x_P or XMIT_x_N output Since the chip is in reset the transmitter should show a constant ou...

Page 27: ...Laboratory Equipment and Quick Setup Evaluation MC92604 Dual GEt Design Verification Board User s Guide Rev 1 Freescale Semiconductor 3 7 Figure 3 2 MC92604 Data Eye Using Recommended Test Setup...

Page 28: ...Guide 3 2 2 1 Equipment Setup Connect the MC92604DVB as shown in Figure 3 3 connecting the transmitter outputs of the link under test XLINK_x_P N to the receiver under test RLINK_x_P N Figure 3 3 Bit...

Page 29: ...recovered clock is observable on RECV_x_RCLK See Figure 3 4 for an example of a receiver startup and error detection sequence 7 Once the receiver has initially locked all receiver data bits RECV_x_ 7...

Page 30: ...eceiver Startup and Error Detection Sequence BIST Counted 3 PN Mismatches Running Don t Care Don t Care Don t Care Don t Care Valid Comma Detected RECV_x_RCLK RECVx_ERR RECV_x_DV RECV_x_COMMA RESET RE...

Page 31: ...Tester BERT This test setup is used to observe the rate at which the MC92604 produces errors given either pseudo random PRBS patterns or user defined pattern sets generated by the serial bit error rat...

Page 32: ...ol bits are set as follows REPE 1 TBIE 1 All other control bits are set to 0 except RESET which is initially set to 0 then transitioned to 1 to start the MC92604 Figure 4 1 Full Speed Serial Link Test...

Page 33: ...e serial link test setup using HSE and a divide by 10 prescaler The control bits are set as follows HSE 1 REPE 1 TBIE 1 All other control bits are set to 0 except RESET which is initially set to 0 the...

Page 34: ...jittered source The amplitude of modulation is then translated into jitter in units of peak to peak unit intervals UIp p Different synthesized sweepers have different characteristics at different fre...

Page 35: ...h is initially set to 0 then transitioned to 1 to start the MC92604 The XMIT data bits are set as follows XMIT_x_ENABLE 1 XMIT_x_ 7 0 0xB5 XMIT_x_CLK jumpered to GTX_CLK This data pattern appears as a...

Page 36: ...rial data stream can be set to either PRBS or user defined data The control bits are set as follows REPE 1 TBIE 1 All other control inputs are set to 0 Figure 4 5 Reference Clock Jitter Tolerance Test...

Page 37: ...be set to either PRBS or user defined data The control bits are set as follows REPE 1 TBIE 1 All other control inputs are set to 0 Figure 4 6 Data Jitter Tolerance Test Setup RF Source 70000 Mainfram...

Page 38: ...Test Setups MC92604 Dual GEt Design Verification Board User s Guide Rev 1 4 8 Freescale Semiconductor...

Page 39: ...d will need to be jumpered to VDDQ for a logic 1 If the signal input is required to be low a shorting jumper may be installed The signal name description and the MC92604 device ball pin number are lis...

Page 40: ...s 13 M10 RECV_REF_A Use receiver A as primary clock output 15 C13 XMIT_REF_A Use transmit A as primary clock input 17 M9 ENABLE_AN Enable auto negotiate if in GMII mode 19 N C GND Ground connection Ta...

Page 41: ...B_XMIT PG8 PG10 connectors Table A 4 A_XMIT and B_XMIT Connectors Connector Pin No MC92604 Ball No Input Signal Name Description A_XMIT Channel A B_XMIT Channel B 1 N6 B3 XMIT_x_0 Transmitter x data...

Page 42: ...ved respectively NOTE If an external clock source is used it must be the same frequency as that of the REF_ CLK to the MC92604 chip The user can utilize the 3 3_CLK_OUTn clocks provided on the DVB as...

Page 43: ...gnal Name Description A_RECV Channel A B_RECV Channel B 1 N C N C 3 L2 D1 RECV_x_RCLK XCVR_ x receive data clock 5 N C N C 7 L2 D1 RECV_x_RCLK XCVR_ x receive data clock 9 K3 C2 RECV_x_RCLK XCVR_ x re...

Page 44: ...f the following ways TRST be driven by a TAP controller that provides a reset after power up Connect TRST to RESET Terminate TRST with a 1 K resistor or hardwire to ground The DVB has a 10K pullup on...

Page 45: ...ed low See Chapter 4 in the MC92604 Dual Gigabit Ethernet Transceiver Reference Guide for details There are no other connection requirements to the MDIO connector Table A 8 MDIO Connector Connector Pi...

Page 46: ...d in Table A 9 These are standard signals for the multiple source agreement MSA fiber optic modules The TX_DISABLE pin must be low for the module to operate Table A 9 SFP_CTRL Connector Connector Pin...

Page 47: ...0805 chip capacitor 5 7 C73 79 0 05 F CAP0805 0 05 F 0805 chip capacitor 6 8 C9 10 C14 C20 C65 C69 C71 72 0 1 F CAP0805 0 1 F 0805 chip capacitor 7 15 C1 C18 19 C24 C27 C30 33 C54 57 C303 304 1 F CAP1...

Page 48: ...low 1 blue 1 green 23 8 R5 6 R62 63 R70 71 R74 75 82 RES0603 82 0603 chip resistor 24 7 R25 26 R36 39 R42 0 RES0805 0 0805 chip resistor 25 1 R24 100 RES0805 100 0805 chip resistor 26 60 R1 R7 9 R14 1...

Page 49: ...D1 3 D6 14 D16 D22 30 D32 N A Dialight 597 5311 402 Green SM LED 38 2 D15 D31 N A Dialight 597 5111 402 Red SM LED 39 2 D17 D33 N A Dialight 597 5411 402 Yellow SM LED 40 3 R12V R22V R22V1 500 3214W...

Page 50: ...Parts List MC92604 Dual GEt Design Verification Board User s Guide Rev 1 B 4 Freescale Semiconductor...

Page 51: ...agram The input to the prescaler can be either through a divide by 2 or directly into the 5 bit programmable counter The bank 1 and bank 2 DIP switches can be used to select a variety of prescaler val...

Page 52: ...00ELT23 On Semiconductor Newark Dual differential PECL to TTL translator with separate inputs MC100ELT21 On Semiconductor Newark Single differential PECL to TTL translator Alternative to above part MC...

Page 53: ...cation Board User s Guide MC92604DVBUM Table D 1 provides a revision history for this document Table D 1 MC92604DVB Revision History Rev No Date Substantive Change s Rev 0 3 2004 Initial release Rev1...

Page 54: ...Revision History MC92604 Dual GEt Design Verification Board User s Guide Rev 1 D 2 Freescale Semiconductor...

Page 55: ...Back Cover...

Page 56: ...particular purpose nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including with...

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