Hardware Preparation and Installation
MC92604 Dual GEt Design Verification Board User’s Guide, Rev. 1
2-8
Freescale Semiconductor
During all testing, the serial transmitter outputs should be terminated with 50
Ω
. This can be done by
connecting the serial transmitter outputs to serial receiver inputs, to any laboratory equipment with 50-
Ω
input impedance through in-line AC coupling, or by terminating the outputs with 50-
Ω
SMA terminations.
2.6
Special Application Connections
There are two sets of special connectors provided for application interface evaluation. A Gigabit Ethernet
SFP socket is provided with SMA connections to connect to the MC92604DVB serial links and then
perform evaluation testing with a fiber optic interface. The user must supply the SFP module. It is not
provided with the MC92604DVB. The SFP socket has it’s own control interface connector, SFP_CTRL.
The mapping of this 2
×
8, 0.100” connector is listed in
Appendix A, “Connector Signals
”
Likewise, a IEEE Std 1394B socket (bilingual version) is provided with SMA connections to connect to
the MC92604 serial links and perform testing with standard patch cords. (Note that there is a slight
impedance mismatch, as the 1394 cables are 110-
Ω
differential.)
2.7
Special Test Connection
The MC92604DVB also contains an oscilloscope PCB test socket, labeled TPA. When the MC92604 is
configured in a PLL factory test mode, this test socket enables special access to the PLL.
NOTE
This test mode is for factory testing purposes only. There are no system
applications for this mode and test socket TPA should remain unconnected
at all times.
2.8
Test Traces
The MCS92610DVB design verification board has both vertical and horizontal 50-
Ω
test traces:
•
Vertical: TST1–TST5 and TST2–TST6 are 11.82 inches long.
•
Horizontal: TST3–TST7 and TST4–TST8 are 9.86 inches long.
These traces can be used to determine the impedance of the board using TDR measurement techniques.
NOTE
These test traces cannot be used as differential pairs. When doing TDR
measurements, observe the difference in propagation delays. This is due to
one trace being on the surface (top or bottom) layer and the other being on
an embedded signal layer.
For the verticle pair, the TST1–TST5 trace is on the bottom surface layer
(10) and TST2–TST6 is on an embedded signal layer (6). The horizontal test
traces have TST3–TST7 located on embedded signal layer (8) and
TST4–TST8 on the top surface layer (1).
