NXP Semiconductors freescale MC92604, User Manual

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Connector Signals
MC92604 Dual GEt Design Verification Board User’s Guide, Rev. 1
Freescale Semiconductor A-5
A.2 Output: 2
×
20 (0.100") Connectors
The MC92604 receiver parallel data outputs are connected to 2
×
20, 0.100" connectors. A mapping of
these signals are contained in Table A-6 .
Table A-6 lists the signals for the A_RECV (LA1) and B_RECV (LA2) connectors. Note that the receive
data clock, RECV_ x _RCLK, is brought out to two connector pins. Care should be exercised when
connecting to both these pins not to exceed the drive capacity of the chip output. Refer to the MC92604
Dual Gigabit Ethernet Transceiver Reference Guide , for more details.
Table A-6. A_RECV and B_RECV Connectors
Connector
Pin No.
MC92604 Ball No.
Output Signal
Name
Description
A_RECV,
(Channel A)
B_RECV,
(Channel B)
1 N/C N/C — —
3 L2 D1 RECV_ x _RCLK XCVR_ x , receive data clock
5 N/C N/C — —
7 L2 D1 RECV_ x _RCLK XCVR_ x , receive data clock
9 K3 C2 RECV_ x _RCLK XCVR_ x , receive data clock_complement
11 N/C N/C GND Ground connection
13 N/C A10 GND (on channel A)
For channel B this pin is TDO (JTAG, test data out)
15 M2 B1 RECV_ x _K Receiver x , K detect status
17 M1 D3 RECV_ x _COMMA Receiver x, COMMA detect status
19 M3 B2 RECV_ x _ERR (bit 9) Receiver x, error detect (bit 9 in 10-bit mode)
21 L3 C1 RECV_ x _DV (bit 8) Receiver x, data valid status (bit 8 in 10-bit mode)
23 L1 D2 RECV_ x _7 Receiver x , data bit 7
25 K2 E1 RECV_ x _6 Receiver x , data bit 6
27 K1 E2 RECV_ x _5 Receiver x , data bit 5
29 J1 F1 RECV_ x _4 Receiver x , data bit 4
31 J2 F2 RECV_ x _3 Receiver x , data bit 3
33 J3 G1 RECV_ x _2 Receiver x , data bit 2
35 H1 G2 RECV_ x _1 Receiver x , data bit 1
37 H2 H3 RECV_ x _0 Receiver x , data bit 0
39 N/C N/C — —