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NXP Semiconductors

UM11734

Hardware user manual for FRDM665SPIEVB

4.3 Block diagram

aaa-044811

REQUEST

SPI

VDDIO

CFG0, CFG1

ID0_STB_OD, ID1, ID2, ID3

DIP switch

3V3LDO

J13

J8

SW1

J1

D8

RESPONSE

SPI

TPL

PORT 0

LDO

MC33665A

POWER MANAGEMENT

GPIO, CONFIG AND

STATUS PINS

PO

R

T

0

R

EQ

S

PI

R

ES

S

PI

TPL

PORT 1

P

O

R

T

1

TPL

PORT 2

P

O

R

T

2

TPL

PORT 3

reset

switch

PO

R

T

3

VBAT

KL30/

12 V/T30

VDD5V

VREG

VDDC/VDDD

VDD5V

VREG
VREG

EXT5V

5V_S32K

VIO_S32K

external interface

for GPIO and

status signals

Figure 1. FRDM665SPIEVB block diagram

4.4 Board description

The FRDM665SPIEVB allows the user to prototype and test all functions of the

MC33665A gateway router.
It can be stacked directly on the S32K344EVB. Different modes of SPI communication

can be established with MC33665A from K1 to K6 connectors. The FRDM665SPIEVB

can be supplied with 12 V at J6 connector or it can be powered directly from

S32K344EVB or EXT5V at J11. VDDC and VDDD can be selected by bridging one of the

positons in jumper J8 (

Table 7

) to select the 5 V. Bridging options jumper at J13 (

Table 8

)

makes it possible to select the VIO voltage of 3.3 V or 5 V or VIO of S32K344EVB.

S32K344EVB can be supplied with USB connection when connected to a PC.
SPI interface to external controller boards can be done with J7 for REQ SPI and J16 for

RSP SPI. Ensure the VIO of external controller board is the same as the VIO selected

with jumper J13. Single SPI or dual SPI modes can be selected by using jumpers at J14.

Populating all jumpers at J14 enables single SPI mode and depopulates jumpers at J14

for dual SPI mode. SW2 DIP switch can be used to select the CFG and ID configuration

for MC33665A. BCC devices can be connected to daisy chain ports 0 to 3 via connectors

J5, J12, J17, and J18.
Connector J1 gives the option to access the GPIO and I

2

C-bus pins of MC33665A.

Contact the NXP engineering team for using TPL autowake function in

FRDM665SPIEVB.

UM11734

All information provided in this document is subject to legal disclaimers.

© 2022 NXP B.V. All rights reserved.

User manual

Rev. 1 — 25 July 2022

6 / 16

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Summary of Contents for FRDM665SPIEVB

Page 1: ...manual for FRDM665SPIEVB Rev 1 25 July 2022 User manual Document information Information Content Keywords MC33665A SPI BMS gateway IC Abstract User manual for starting work with MC33665A SPI EVB Down...

Page 2: ...ev Date Description 1 20220725 initial version Revision history UM11734 All information provided in this document is subject to legal disclaimers 2022 NXP B V All rights reserved User manual Rev 1 25...

Page 3: ...circuit board layout and heat sinking design as well as attention to supply filtering transient suppression and I O signal quality The product provided may not be complete in terms of required design...

Page 4: ...metrics ordering information and a Getting Started tab The Getting Started tab provides quick reference information applicable to using the FRDM665SPIEVB evaluation board including the downloadable as...

Page 5: ...an be established with four different ports 4 2 Board features The main features of FRDM665SPIEVB are Request SPI Response SPI Onboard transformer isolation for TPL communication to BCC devices Config...

Page 6: ...he 5 V Bridging options jumper at J13 Table 8 makes it possible to select the VIO voltage of 3 3 V or 5 V or VIO of S32K344EVB S32K344EVB can be supplied with USB connection when connected to a PC SPI...

Page 7: ...en X X X D15 green X X X D16 red X Table 1 Power status LEDs 4 5 Connectors FRDM665SPIEVB has multiple connectors for interfacing to MCU internal GPIO and external BCC devices UM11734 All information...

Page 8: ...PIO3 or INT3 for MC33665A 5 GPIO4 interface to GPIO4 or I 2 C bus in MC33665A 6 GPIO5 interface to GPIO5 or I 2 C bus in MC33665A 7 GPIO6 interface to GPIO6 or SYNC in MC33665A 8 GPIO7 interface to GP...

Page 9: ...und Table 4 Response SPI J16 Pin number Connection Description 1 SPI_REQ_CS chip select for request SPI 2 GND ground 3 SPI_REQ_SCK clock interface for request SPI 4 GND ground 5 SPI_REQ_SIN response T...

Page 10: ...de 3 4 SCLK_RSP bridge SCLK_RSP with SCLK_REQ for single SPI mode 5 6 CSN_RSP bridge CSN_RSP with CSN_REQ for single SPI mode Table 9 Single SPI jumper J14 Pin number Connection Description 1 HOLD int...

Page 11: ...o MC33665A 13 SDAT_REQ_RXD request RXD signal to MC33665A 15 CSN_REQ request CSN to MC33665A Other not connected Table 13 S32K344EVB connector K4 Pin number Connection Description 12 VSS ground Other...

Page 12: ...FRDM665SPIEVB can be interfaced with external microcontroller boards for SPI and GPIO interface of MC33665A Connect 12 V at J6 or external 5 V to J11 interface Select the 5 V to MC33665A with jumper J...

Page 13: ...valuation and development board for general purpose MCU S32K344 BATT TPLCABLE20 TPL two wire twisted 20 cm long cable BATT TPLCABLE50 TPL two wire twisted 50 cm long cable BATT 14CTCABLE25 cell termin...

Page 14: ...onditions with regard to the purchase of NXP Semiconductors products by customer Export control This document as well as the item s described herein may be subject to export control regulations Export...

Page 15: ...ories 13 Figures Fig 1 FRDM665SPIEVB block diagram 6 Fig 2 SPI EVB description 7 Fig 3 FRDM665SPIEVB connectors 8 Fig 4 Board interface connections 12 Fig 5 External board interface 13 UM11734 All inf...

Page 16: ...lease be aware that important notices concerning this document and the product s described herein have been included in section Legal information 2022 NXP B V All rights reserved For more information...

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