Autobias functionality
A3M38SL039 Airfast Power Amplifier Module with Autobias Control, Rev. 0, September 2022
Data Sheet: Technical Data
11
/
33
Power Down Sequence
1. V
DP1
,V
DP2
,V
DC1
,V
DC2
power down
2. SPI/I
2
C interface deactivated
3. V
CC
_+5V: 5 V power down
Note: All digital interfaces (SDA, SCLK, CS_B,Tx_EN) are 1.8 V logic.
5 Autobias functionality
5.1 General overview
After power up, the integrated bias controller develops and applies a thermally compensated quiescent bias voltage to the gate
of each of the four RF transistors contained within the power amplifier module (PAM) based on the preset OTP values. See
Section 3.1 for more information on the OTP memory. This achieves optimal RF performance over the full temperature range.
The standard SPI or I
2
C interface can be used to read the temperature sensor and overwrite preset DAC values. The device
can be used without the programming interface. The thermal compensation circuit is analog and not programmable; however,
the preset DAC values can be overwritten to provide an alternate thermal compensation scheme via the SPI or I
2
C interface.
This section describes the operation and programming of the bias controller.
5.2 Operational overview
shows a detailed view of the carrier side (Group A) autobias controller. The peaking side (Group B) controller is a
duplicate of the carrier; however, the RF transistor peripheries and quiescent operating points will be different as required by
the Doherty operation. The module contains four RF LDMOS field-effect transistors (FET) consisting of a driver and final for
the carrier amplifier (on a single IC die) and a driver and final for the peaking amplifier (on a single IC die). Each IC die also
contains a small periphery reference FET that is designed to match the properties of the larger RF transistors with regard to
part-to-part process and temperature-dependent variations. The bias controller interfaces with each of the RF FETs and
provides flexibility to control the biasing of each transistor independently.
The bias controller operates by establishing a known current through the reference FET typically in the range of 1
−
2 mA per
reference FET. This in turn establishes a gate-source operating voltage by sensing the voltage drop across an integrated, high
tolerance resistor placed between V
CC
(5 V) and the reference device drain terminal. The bias controller V
CC
_+5V pin should
be operated from a 5 V supply with tolerance of ±5%. The reference voltage across the precision resistor R1 is compared to a
voltage programmed in the bias controller (A_Sense_DAC and B_Sense_DAC), thereby providing fine incremental adjustment
to the default bias current of the reference FET. Because the reference FET and RF FET are manufactured on the same die in
close proximity, they exhibit similar process and temperature dependencies.
