A
A
B
B
C
C
D
D
E
E
4
4
3
3
2
2
1
1
Parallel JTAG Interface
KEY
JTAG Connector
On-Board
Host Target Interface
Disable
PO
R
T
_D
E
P
O
RT
_V
CC
DSCO De
si
gn
PARALLEL JTAG HOST TARGET INT
E
R
F
ACE AND JTAG CONNECTOR
MC56F8367EVM.DSN
1.0
11
14
Thurs
day
, Septem
ber 02, 2004
B
D
ig
ital Signal Controller Operation
2100 Eas
t Elliot R
oad
Tem
pe, Ariz
ona 85284
Tit
le
D
ocument
Date
:
Size
D
es
igner:
S
he
et
o
f
Rev.
Numbe
r
(512) 895-7215 FAX: (480) 413-2510
/J
_R
ESET
P_
R
ESET
/J
_T
R
S
T
/J
_R
ESET
TD
O
P_
R
ESET
TMS
TC
K
/J
_T
R
S
T
P
O
RT
_T
DO
PO
R
T
_T
M
S
/P
OR
T_TR
S
T
P
O
RT
_T
CK
P
O
RT
_T
DI
P
O
RT
_CONNE
CT
PO
R
T
_R
ESET
P
O
RT
_I
DE
NT
/J
_R
ESET
/J
_T
R
S
T
/D
E
P_
D
E
/J
_T
R
S
T
PW
R
/D
E
TD
I
PW
R
TD
O
P_
D
E
/CCE
N
PO
R
T
_PU
P
O
RT
_CONNE
CT
PO
R
T
_PU
TD
I
TD
O
TC
K
TMS
/R
ESET
/T
R
S
T
/PO
R
+3
.3
V
+3
.3
V
+3
.3
V
+3
.3
V
+Vs
el
+Vs
el
+5
.0
V
+3
.3
V
R51
51 Ohm
R48
5.
1K
R42
5.
1K
J3
1
3
5
7
9
11
13
2
4
6
8
10
12
14
R23
47K
R24
47K
JG
3
1
2
P1
1
3
2
15
14
16
4
17
5
18
6
19
7
20
8
21
9
22
10
23
11
24
12
25
13
R50
51 Ohm
Q1 2N2222A
U7A
74A
C00
1
2
3
U7D
74A
C00
12
13
11
U7B
74A
C00
4
5
6
U7C
74A
C00
9
10
8
R47
5.
1K
R27
47K
R25
47K
R26
47K
R46
5.
1K
R44
5.
1K
R45
5.
1K
R43
5.
1K
U8
M
C
74HC244DW
18
16
14
12
9
7
5
3
19
1
2
4
6
8
11
13
15
17
20
10
1Y
1
1Y
2
1Y
3
1Y
4
2Y
1
2Y
2
2Y
3
2Y
4
2G
1G
1A
1
1A
2
1A
3
1A
4
2A
1
2A
2
2A
3
2A
4
VC
C
GND
U9
M
C
74LCX
244DW
18
16
14
12
9
7
5
3
19
1
2
4
6
8
11
13
15
17
20
10
1Y
1
1Y
2
1Y
3
1Y
4
2Y
1
2Y
2
2Y
3
2Y
4
2G
1G
1A
1
1A
2
1A
3
1A
4
2A
1
2A
2
2A
3
2A
4
VC
C
GND
R76
0 Ohm
R73
0 Ohm
R74
0 Ohm
R77
0 Ohm
R75
0 Ohm
1
1
R95
1K
DNP
R94
1K
JG
19
1
2
3
MC56F8367EVM User Manual, Rev. 2
Appendix A-12
Freescale Semiconductor
Preliminary
Figure
A-11. Parallel JTAG Ho
st Ta
rget Interface and
JTAG Conn
ecto
r