Novametrix Medical Systems MARS PO2 TECH 2001, Service Manual

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Section 4
Theory of Operation 2775 Main Board
16
Model 2001 Service Manual Rev. 01
operate while the CAL line is high. On the falling edge of the CAL signal, the ADC will initiate a
calibration cycle determined by the state of the SC1 and SC2 inputs.
The high at SC1 and the low at SC2 cause the Data Sampling Controller, IC42, to set INSIG*
high and reset SIGND* to a logic low. The high INSIG* opens the switch at IC41 pin8 so that
IC41 pins 6 and 7 are no longer connected- disconnecting the returning photodiode signal from
the rest of the circuitry. The low SIGND* signal closes the switch at IC41 pin 9 and as a result,
the input to the C90-R59 high pass filter (and thus the entire ADC input circuitry) is brought to
ground potential.
The CAL line (which went high at power up) is reset low and ADCs IC34 and IC37 begin their
calibration cycles. Because the analog input circuitry is grounded via SIGND*, only circuit offset
voltages can be present at the AIN (pin 9) input. The calibration cycle sets the ADC “zero” point
to equal this voltage, thus compensating for any circuitry offsets. The ADC then sets its “full
scale” point to equal the voltage at its VREF (pin 10) input. This completes the calibration cycle.
The ADC can now start sampling its input and converting it to a 20-bit digital word. The
processor resets SC1 to a logic low, causing IC41 pin 9 to open and IC41 pin 8 to close. The
photodiode signal can now reach the ADCs.
20-Bit Analog-to-Digital Conversion
See sheet 2 of 4 on schematic.
Data from the Red and Infrared channels is sampled by the 20-bit measurement ADCs, IC34
and IC37 respectively. The analog input at pin 9 is converted to a digital representation with 20-
bit resolution based on the input magnitude.
The CS5503 A/D converter continuously samples its input, converts the value to a digital word,
puts the word in its output buffer (overwriting previous buffer contents), then repeats the
process by again sampling its input. The frequency of the sample/convert/overwrite-buffer
sequence is based on the 3.2768 MHz clock signal at the ADC pin 3 (CLKSEQ) input.
The microprocessor starts a read cycle of the Infrared channel by bringing IC37 pin 16 (Chip
Select Channel 1) low. A Red channel read starts when IC34 pin 16 (Chip Select Channel 2) is
brought low.
On the falling edge of the ADC’s CS*, the output word’s MSB (most significant bit) appears at
the pin-20 SDATA (Serial Data) output. The SDATA line connects directly to the
microprocessor’s serial input (RXS) pin. The remaining bits (in descending order) are output
from SDATA with subsequent falling edges of the Serial Clock (SCLK) input at pin 19. The
SDATA output automatically goes to a 3-state (high impedance) condition after completing a
word transmission, thus freeing the data line for other uses (i.e., the other ADC channel).
The Serial Clock speed is controlled through the digital board PEEL IC18. This clock rate is
significantly slower than the ADC sampling rate. As a result, the ADC rewrites its output buffer
with new information at a faster rate than the data can be read from the buffer. No conflict
occurs, however, because while CS* is low (during the read cycle), the ADC does not update
its output buffer (the current word is not overwritten). After the processor receives the entire
word, it allows the converter’s CS* to return high, and the ADC resumes its sample/convert/
overwrite-buffer cycle.