Baseband Troubleshooting Instructions
CCS Technical Documentation
Page 10
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Nokia Corporation
Issue 1 10/02
J413
DBUSCLK
DBUS clock,
see Figure 26, “J413: DBUSCLK, UEM (D200 pin D10) ->
UPP (D400 pin K3),” on page 24
UEM (D200) -> UPP (D400)
J414
DBUSDA
DBUS data,
see Figure 27, “J414: DBUSDA, UEM (D200 pin A11) <->
UPP (D400 pin L3),” on page 25
UEM (D200) <-> UPP (D400)
J415
DBUSENX1
DBUS enable,
see Figure 28, “J415: DBUSENX1, UEM (D200 pin B10) ->
UPP (D400 pin J3),” on page 25
UEM (D200) -> UPP (D400)
J416
EXTWRX
FLASH write enable,
see Figure 29, “J416: EXTWRX (during flashing), UPP
(D400 pin N9) -> FLASH (D450 pin A6),” on page 26
(during flashing)
UPP (D400) -> FLASH (D450)
J417
EXTRDX
FLASH read enable,
see Figure 30, “J417: EXTRDX, UPP (D400 pin L7) ->
FLASH (D450 pin C10),” on page 26
UPP (D400) -> FLASH (D450)
J418
FLS2CSX
UPP (D400) -> TESTPOINT
J419
FLSCLK
FLASH clock,
see Figure 31, “J419: FLSCLK, UPP (D400 pin N12) ->
FLASH (D450 pin A4),” on page 27
UPP (D400) -> FLASH (D450)
J420
FLSCSX
FLASH chip enable,
see Figure 32, “J420: FLSCSX, UPP (D400 pin N6) ->
FLASH (D450 pin B9),” on page 27
UPP (D400) -> FLASH (D450)
J470
VBAT
Battery voltage
J471
GENTEST0/
STITxD
OSTRICH transmitted data
UPP (D400) -> TESTPOINT
J472
GENTEST1/
STISClk
OSTRICH clock
UPP (D400) -> TESTPOINT
J473
STIRxD
OSTRICH received data
UPP (D400) -> TESTPOINT
J474
GND
Ground point
J480
JTMS
UPP (D400) -> TESTPOINT
J481
JTRst
UPP (D400) -> TESTPOINT
J482
JTDI
UPP (D400) -> TESTPOINT
J483
VCC
Supply voltage from 1.8 V VIO regulator
J484
JTDO
UPP (D400) -> TESTPOINT
J485
JTClk_ret
UPP (D400) -> TESTPOINT
J486
JTClk
UPP (D400) -> TESTPOINT
J487
EMU0
UPP (D400) -> TESTPOINT
J488
EMU1
UPP (D400) -> TESTPOINT
J489
GND
Ground point