Nokia 9000i, Service Manual

Page: 61 / 434

After Sales
Technical Documentation
RAE/RAK–1N
Baseband
Page 2–35
Original, 08/96
Physically the D2CA ASIC is located in MCM2. The VCXO clock buffer
and SIM power switch are assembled on CMT motherboard.
Technical specification
Table 36. External Signals and Connections, Inputs
Signal Name Signal description From
VL1 Logic supply voltage. Max 150 mA. PWRU
IOX I/O enable. Indicates access to DSP I/O address space. DSPU
RWX Read/WriteX DSPU
WSTROBEX MCU’s write strobe CTRLU
RSTROBEX MCU’s read strobe CTRLU
RFC Reference clock from VCXO (26 MHz) RF
XRES Master reset PWRU
DSPAD(16:0) DSP’s address bus and control signals DSPU
MCUAD(19:16,4:0
) MCU’s address bus CTRLU
DAX Data acknowledge RFI
MRBUSDET MBUS/RBUS activity detection CTRLU
DBUSDET DBUS activity detection DSPU
Table 37. External Signals and Connections, Outputs
Signal Name Signal description To
INT0, INT1 Interrupts for DSP DSPU
NMI Not maskable interrupt request CTRLU
IRQX Interrupt request CTRLU
RESETX Master (power up) reset CTRLU,
RFI
DSP1RSTX Reset for the DSP DSPU
SIMRESET Reset for the SIM SIMFLEX
conn
WRX Write strobe RFI
RDX Read strobe RFI
RFIAD(3:0) RFI address bus RFI
SCLK Synthesizer load clock RF
SDATA Synthesizer load data RF
SENA1 UHF and VHF PLL enable RF
RXPWR RX circuitry power enable RF
TXPWR TX circuitry power enable RF
SYNTHPWR Synthesizer circuitry power enable RF
TXP Transmitter power control enable RF
MCUCLK Main clock for MCU (26 MHz) CTRLU