PEAK 6320A User’s Guide
BIOS Setup 4-
21
delayed to allow for the completion of the I/O. This item allows you to determine the
recovery time allowed for 8 bit I/O. Choices are from NA, 1 to 8 CPU clocks.
16 Bit I/O Recovery Time
This item allows you to determine the recovery time allowed for 16 bit I/O. Choices are
from NA, 1 to 4 CPU clocks.
Memory Hole At 15M-16M
In order to improve performance, certain space in memory can be reserved for ISA cards.
This memory must be mapped into the memory space below 16 MB.
Enabled
Memory hole supported.
Disabled
Memory hole not supported.
Passive Release
When Enabled, CPU to PCI bus accesses are allowed during passive release.
Otherwise, the arbiter only accepts another PCI master access to local DRAM. The
choice: Enabled, Disabled.
Delayed Transaction
The chipset has an embedded 32-bit posted write buffer to support delay transactions
cycles. Select Enabled to support compliance with PCI specification version 2.1. The
choice: Enabled, Disabled.
AGP Aperture Size (MB)
Select the size of the Accelerated Graphics Port (AGP) aperture. The aperture is a
portion of the PCI memory address range dedicated for graphics memory address space.
Host cycles that hit the aperture range are forwarded to the AGP without any
translation. See
www.agpforum.org
for AGP information.
The choice: 4, 8, 16, 32, 64, 128, 256
Auto Detect DIMM/PCI Clk
This item auto detect the clock generator. The unused pins of DIMM/PCI Clk are
disabled. The amplitudes of the radiated electromagnetic emissions are reduced.
Choices: Enabled, Disabled.
Summary of Contents for PEAK 6320A
Page 4: ...Appendix 1 Watch Dog Timer Appendix 2 Memory Mapping ...
Page 10: ...Peak 6320A User s Guide 9 z z 4 3 19 5 7 z 4 3 02 19 5 0 2 z 4 3 0 19 5 0 z 4 3 19 5 ...
Page 27: ...Peak 6320A User s Guide Capability Expanding 3 2 ...
Page 47: ...PEAK 6320A User s Guide BIOS Setup 4 16 Disabled Video shadow is disabled ...
Page 58: ...PEAK 6320A User s Guide BIOS Setup 4 27 2 Hour 4 Hour ...
Page 91: ...PEAK 6320A User s Guide Memory Mapping A2 1 Appendix 2 Memory Mapping ...