Copyright © 2016 NEXCOM International Co., Ltd. All Rights Reserved.
46
NEX 614 User Manual
Chapter 3: BIOS Setup
Enable Root Port
Enables or disables the root port.
Max Link Speed
Configures the maximum link speed of the PEG device.
PEG0 Slot Power Limit Scale
Configures the scale used for the slot power limit value.
Detect Non-Compliance Device
Enables or disables detection of non-compliance device in the PEG.
Program PCIe ASPM After OpROM
Enabled
PCIe ASPM is programmed after OpROM.
Disabled
PCIe ASPM is programmed before OpROM.
Program Static Phase1 Eq
Enables or disables program static phase1.
Always Attempt SW EQ
Enables or disables Always Attempt SW EQ, even if it has been done once.
Number of Presets to Test
Configures the number of presets to test.
Version 2.17.1255. Copyright (C) 2016 American Megatrends, Inc.
Aptio Setup Utility - Copyright (C) 2016 American Megatrends, Inc.
→←: Select Screen
↑↓: Select Item
Enter: Select
+/-: Change Opt.
F1: General Help
F2: Previous Values
F3: Optimized Defaults
F4: Save & Exit
ESC: Exit
Enable or Disable the Root Port
PEG Port Configuration
PEG 0:1:0
Enable Root Port
Max Link Speed
PEG0 Slot Power Limit Value
PEG0 Slot Power Limit Scale
PEG0 Physical Slot Number
Detect Non-Compliance Device
Program PCIe ASPM after OpROM
Program Static Phase1 Eq
Gen3 Root Port Preset value for each Lane
Gen3 Endpoint Preset value for each Lane
Gen3 Endpoint Hint value for each Lane
Gen3 RxCTLE Control
Gen3 Adaptive Software
Equalization
Always Attempt SW EQ
Number of Presets to test
Allow PERST# GPIO Usage
SW EQ Enable VOC
Jitter Dwell Time
Jitter Error Target
VOC Dwell Time
Not Present
[Auto]
[Auto]
75
[1.0x]
1
[Disabled]
[Disabled]
[Enabled]
[Disabled]
[Auto]
[Enabled]
[Auto]
3000
2
10000
Version 2.17.1255. Copyright (C) 2016 American Megatrends, Inc.
Aptio Setup Utility - Copyright (C) 2016 American Megatrends, Inc.
→←: Select Screen
↑↓: Select Item
Enter: Select
+/-: Change Opt.
F1: General Help
F2: Previous Values
F3: Optimized Defaults
F4: Save & Exit
ESC: Exit
Max Link Speed
PEG0 Slot Power Limit Value
PEG0 Slot Power Limit Scale
PEG0 Physical Slot Number
Detect Non-Compliance Device
Program PCIe ASPM after OpROM
Program Static Phase1 Eq
Gen3 Root Port Preset value for each Lane
Gen3 Endpoint Preset value for each Lane
Gen3 Endpoint Hint value for each Lane
Gen3 RxCTLE Control
Gen3 Adaptive Software
Equalization
Always Attempt SW EQ
Number of Presets to test
Allow PERST# GPIO Usage
SW EQ Enable VOC
Jitter Dwell Time
Jitter Error Target
VOC Dwell Time
VOC Error Target
Generate BDAT PEG Margin Data
PCIe Rx CEM Test Mode
PCIe Spread Spectrum Clocking
[Auto]
75
[1.0x]
1
[Disabled]
[Disabled]
[Enabled]
[Disabled]
[Auto]
[Enabled]
[Auto]
3000
2
10000
2
[Disabled]
[Disabled]
[Enabled]
PEG Port Configuration
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Chipset
Chipset
Chipset
