Copyright © 2021 NEXCOM International Co., Ltd. All Rights Reserved.
34
DFA1163 User Manual
Chapter 4: BIOS Setup
Data Bits
The options are 7 and 8.
Parity
A parity bit can be sent with the data bits to detect some transmission errors.
Even
Parity bit is 0 if the number of 1’s in the data bits is even.
Odd
Parity bit is 0 if number of 1’s in the data bits is odd.
Stop Bits
Stop bits indicate the end of a serial data packet. (A start bit indicates the
beginning). The standard setting is 1 stop bit. Communication with slow
devices may require more than 1 stop bit.
Flow Control
Flow control can prevent data loss from buffer overflow. When sending data
and the receiving buffers are full, a “stop” signal can be sent to stop the
data flow.
VT-UTF8 Combo Key Support
Enables or disables VT-UTF8 combo key support.
Recorder Mode
When this field is enabled, only text will be sent. This is to capture the
terminal data.
Resolution 100x31
Enables or disables extended terminal resolution.
Putty Keypad
Selects the Putty keyboard emulation type.
PCI Subsystem Settings
This section is used to configure the PCI.
PCI Latency Timer
Configures the length of time allowed for the PCI device to control the bus
before another takes over.
VGA Palette Snoop
Enables or disables the VGA palette registers snooping.
PERR# Generation
Enables or disables the PCI device to generate PERR#.
Advanced
Version 2.19.1266. Copyright (C) 2021 American Megatrends, Inc.
Aptio Setup Utility - Copyright (C) 2021 American Megatrends, Inc.
→←: Select Screen
↑↓: Select Item
Enter: Select
+/-: Change Opt.
F1: General Help
F2: Previous Values
F3: Optimized Defaults
F4: Save & Exit
ESC: Exit
Value to be programmed into
PCI Latency Timer Register.
PCI Bus Driver Versio
PCI Devices Common Settings:
PCI Latency Timer
VGA Palette Snoop
PERR# Generation
SERR# Generation
Above 4G Decoding
SR-IOV Support
BME DMA Mitigation
PCI Express Settings
PCI Express GEN 2 Settings
A5.01.12
[32 PCI Bus Clocks]
[Disable]
[Disable]
[Disable]
[Disable]
[Disable]
[Disable]
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