NED
UME-0031-03
Sui7440
31
4.3 Digital Processing flow in FPGA
The figure below shows the digital processing flow in the FPGA.
After the CCD output passes through A/D conversion, data is processed in the digital
domain and converted to Camera Link Medium Configuration (for 8 bit output) for output.
power
supply
conector
＋１２Ｖ
＋１２Ｖ
power supply
indicator
（ＬＥＤ green ）
ＣＤＳ
ＰＧＡ
ＡＤＣ
ＣＣＤ ＰＲＯＣＥＳＳＯＲ
ＣＣＤ
timing
generator
Ｃｈａｎｎｅｌ
Ｌｉｎｋ
driver
ＭＤＲ
２６Ｐ
Ｉ／Ｏ
connector
Ｘ０±，Ｘ１±，
Ｘ２±，Ｘ３±，
ＸＣｌｋ±
ＣＣ１±
ＣＣ２±
ＣＣ３±
ＣＣ４±
ＳｅｒＴＦＧ±
ＬＶＤＳ
receiver
ＬＶＤＳ
driver ・
receiver
ＳｅｒＴＣ±
controller
２８
４
LVAL，DVAL
CK
PortA，B
Figure 4-3-1 FPGA Processing block diagram
4.4 Startup
After turning on, the camera runs a startup procedure before it starts getting images
and outputting data. It takes about four seconds.
The startup procedure is as follows.
(1) The camera initializes the hardware.
(2) Reads out the latest camera settings from the flash memory. (User settings if any
or factory default settings)
(3) Sets up the camera with the setting values from the flash memory.
After this sequence, the camera is ready to get images and output data.
