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RMSL8K76CP/RMSL6K76CP/RMSL4K76CP UME-0094-02
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4.3 Digital Processing flow in FPGA
The
digital processing flow in FPGA is shown below.
Video(10bit)
From
Sensor
-
x
White reference
multipl
Test Pattern
select
Black reference
substract
FPGA Processing block diagram
x
Video(8 or 10bit)
To CoaxPress
Driver
Digital Gain
-
Digital Offset
8 or 10bit
select
Output Block
select
In Test Pattern mode, Black / White reference and Digital Gain /Offset will be skipped.
Figure 4-3-1 FPGA Processing Block Diagram
4.4 Startup
After turning on, the camera run a startup procedure before it starts getting images
and outputting data.
It takes about ten seconds.
The startup procedure is as follows.
(1) The camera hardware initializes.
(2) Reads out the latest camera settings from the flash memory.
(User settings if any or factory default settings)
(3) Set up the camera with the setting value from the flash memory.
After those sequences, the camera is ready to get images and output data.
In order to output camera control and images, it is necessary to perform device
discovery from the grabber board.
