NEC V850E/PH2, User Manual

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Chapter 12 16-bit 2-Phase Encoder Input Up/Down Counter/General Purpose Timer (TMENC10)
User’s Manual U16580EE3V1UD00
(4) Capture/compare register 100 (CC100)
CC100 is a 16-bit register. It can be used as a capture register or as a compare register through
specification with capture/compare control register n (CCR).
This register can be read/written in 16-bit units.
Reset input clears this register to 0000H.
Cautions: 1. When used as a capture register (CMS0 bit of CCR register = 0), write access is
prohibited.
2. When used as a compare register (CMS0 bit of CCR register = 1) and the TM1CE
bit of the TMC10 register is 1, overwriting the CC100 register values is prohibited.
3. When the TM1CE bit of the TMC10 register is 0, the capture trigger is disabled.
4. When the operation mode is changed from capture register to compare register,
set a new compare value.
5. Continuous reading of CC100 is prohibited. If CC100 is continuously read, the
second read value may differ from the actual value. If CC100 must be read twice,
be sure to read another register between the first and the second read operation.
Figure 12-5: Capture/Compare Register 100 (CC100)
(a) When set as a capture register
When CC100 is set as a capture register, the valid edge of the corresponding external TICC10
signal is detected as the capture trigger. TMENC10 latches the count value in synchronization with
the capture trigger (capture operation). The latched value is held in the capture register until the
next capture operation.
The valid edge of external interrupts (rising edge, falling edge, both edges) is selected with signal
edge selection register 10 (SESA10).
When the CC100 register is specified as a capture register, an INTCC10 interrupt is generated
upon detection of the valid edge of the external TICC10 signal.
(b) When set as a compare register
When CC100 is set as a compare register, it always compares its own value with the value of
TMENC10. If the value of CC100 matches the value of the TMENC10, CC100 generates an
interrupt signal (INTCC10).
After reset: 0000H R/W Address: FFFFF6B6H
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC100