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Chapter 13
FCAN Interface Function
Preliminary User’s Manual U14913EE1V0UM00
(5)
CAN 1 to 3 error counter registers (C1ERC to C3ERC)
The CxERC registers reflect the status of the transmit and the receive error counters of the corre-
sponding CAN module x
(x = 1 to 3).
These registers can be read-only in 8-bit and 16-bit units.
Figure 13-37: CAN 1 to 3 Error Counter Registers (C1ERC to C3ERC)
Note: The register address is calculated according to the following formula:
effective address = P address offset
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Address
Offset
Note
Initial
value
C1ERC REC7 REC6 REC5 REC4 REC3 REC2 REC1 REC0 TEC7 TEC6 TEC5 TEC4 TEC3 TEC2 TEC1 TEC0
856H
00FFH
C2ERC REC7 REC6 REC5 REC4 REC3 REC2 REC1 REC0 TEC7 TEC6 TEC5 TEC4 TEC3 TEC2 TEC1 TEC0
896H
00FFH
C3ERC REC7 REC6 REC5 REC4 REC3 REC2 REC1 REC0 TEC7 TEC6 TEC5 TEC4 TEC3 TEC2 TEC1 TEC0
8D6H
00FFH
Bit Position
Bit Name
Function
15 to 8
REC7 to
REC0
The receive error counter (REC) holds the status of the error counter of reception
errors as defined in the CAN protocol.
7 to 0
TEC7 to
TEC0
The transmit error counter (TEC) holds the status of the error counter of transmission
errors as defined in the CAN protocol.
Summary of Contents for V850E/CA1 ATOMIC
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