CHAPTER 4 CAUTIONS
User’s Manual U15447EJ1V0UM
25
4.2
NMI Signal
The input signal (NMI signal) from the target system is delayed (t
pD
= 0.25 ns (TYP.)) because it passes through
QS3125 (Q switch), and I/O signals (ports 4, 5, 6, 9, 11) pass through QS3384 (Q switch) before it is input to the
emulator chip.
In addition, the DC characteristics change. The input voltage becomes V
IH
= 2.0 V (MIN.), V
IL
= 0.8 V (MAX.), and
the input current becomes I
IN
=
±
0.5
µ
A (MAX.).
Figure 4-2. NMI Signal Flow Path
4.3
V
PP
Signal
The V
PP
signal from the target system is left open in the emulator.
4.4
NMI Signal Mask Function
When using the P00/NMI pin in the port mode, do not mask the NMI signal.
NMI pin
QS3125
IE-703079-MC-EM1
Port pin
QS3125
Target
system
Emulator chip
NMI signal
Port signal
