NEC uPD72256 Preliminary User'S Manual Download | Manualshive

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Bit

Bit name

Function

18

BUFPUEN2

Internal pull-up resistor control of pin group 2: pins 127, 132 - 134, 137 - 141

0 internal pull-up disabled

1 internal pull-up enabled

17

BUFPUEN1

Internal pull-up resistor control of pin group 1: pins 102, 144 -151

0 internal pull-up disabled

1 internal pull-up enabled

16

BUFPUEN0

Internal pull-up resistor control of pin group 0: pins 118 - 126

0 internal pull-up disabled

1 internal pull-up enabled

12

SMUX91

Pin 91 multiplexer control

0 output determined by PINMUX[3:0]

1 VO1G0 output

11

SMUX92

Pin 92 multiplexer control

0 output determined by PINMUX[3:0]

1 VO1R1 output

10

SMUX93

Pin 93 multiplexer control

0 output determined by PINMUX[3:0]

1 VO1R0 output

9

SMUX94

Pin 94 multiplexer control

0 output determined by PINMUX[3:0]

1 VO1B1 output

8

SMUX95

Pin 95 multiplexer control

0 output determined by PINMUX[3:0]

1 VO1B0 output

7

SMUX12

Pin 12 multiplexer control

0 output determined by PINMUX[3:0]

1 VO0EN output

6

SMUX78

Pin 78 multiplexer control

0 output determined by PINMUX[3:0]

1 VO1R1

5

SMUX26

Pin 26 multiplexer control

0 output determined by PINMUX[3:0]

1 VO1B1

4

SMUX127

Pin 127 multiplexer control

0 output determined by PINMUX[3:0]

1 VO0EN output

3 to 0

PINMUX[3:0]

These bits determine the pin multiplexer option.

System Controller

Chapter 4

Preliminary User's Manual S19203EE1V3UM00

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Summary of Contents for uPD72256

Page 1: ...Preliminary User s Manual µPD72256 µPD72257 Graphics Controllers Hardware Document No S19203EE1V3UM00 Date published July 07 2009 NEC Electronics 2008 Printed in Germany ...

Page 2: ...rcuits software and information While NEC Electronics endeavors to enhance the quality reliability and safety of NEC Electronics products customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely To minimize risks of damage to property or injury including death to persons arising from defects in NEC Electronics products customers must incorporate suffici...

Page 3: ...onics they must contact an NEC Electronics sales representative in advance to determine NEC Electronics willingness to support a given application Note 1 NEC Electronics as used in this statement means NEC Electronics Corporation and also includes its majority owned subsidiaries 2 NEC Electronics products means any product developed or manufactured by or for NEC Electronics as defined above Prelim...

Page 4: ...ingdom Branch Cygnus House Sunrise Parkway Linford Wood Milton Keynes MK14 6NP U K Tel 01908 691133 Succursale Française 9 rue Paul Dautier B P 52 78142 Velizy Villacoublay Cédex France Tel 01 30675800 Tyskland Filial Täby Centrum Entrance S 7th floor 18322 Täby Sweden Tel 08 6387200 Filiale Italiana Via Fabio Filzi 25 A 20124 Milano Italy Tel 02 667541 Branch The Netherlands Steijgerweg 6 5616 HS...

Page 5: ...ress High order at high stage and low order at low stage Note Additional remark or tip Caution Item deserving extra attention Numeric notation Binary xxxx or xxxB or xxxB Decimal xxxx Hexadecimal xxxxH or xxxxH or 0x xxxx Prefixes representing powers of 2 address space memory capacity K kilo 210 1024 M mega 220 10242 1 048 576 G giga 230 10243 1 073 741 824 Data units Byte 8 bit Half word 2 byte 1...

Page 6: ...age field denotes the half frame holding the even respectively odd lines of a frame in interlaced video mode thus one entire frame is made up of two fields Trademarks AHB stands for AMBA Advanced High performance Bus and is a trademark of ARM Limited APB stands for AMBA Advanced Peripheral Bus and is a trademark of ARM Limited AMBA stands for Advanced Microcontroller Bus Architecture and is a regi...

Page 7: ... 4 System Controller 86 4 1 Functional Overview 87 4 2 Clock Generator 88 4 2 1 PLL configuration 89 4 2 2 Main system clock 90 4 2 3 Video Output clocks 90 4 2 4 Internal RAM clock Ravin L only 90 4 3 Resets 91 4 3 1 PLL restart 92 4 3 2 Software and Watchdog reset 93 4 3 3 Host CPU synchronization 93 4 4 System Watchdog 94 4 5 Modules Control Functions 94 4 5 1 Internal RAM control Ravin L only ...

Page 8: ...ion status information 156 6 3 Video Capturing 156 6 3 1 Video capturing modes 156 6 3 2 Start and stop of video capturing 157 6 4 Scaling Cropping and Storing 158 6 4 1 Cropping 159 6 4 2 Scaling 160 6 4 3 Storing 164 6 5 Colour Format Conversions 164 6 5 1 RGB 666 565 to RGB 888 conversion 164 6 5 2 YUV 4 2 2 to YUV 4 4 4 conversion 165 6 5 3 YUV 4 4 4 to RGB 888 conversion 166 6 6 YUV Adjustmen...

Page 9: ...a Formats 223 8 4 1 Source and destination data 223 8 4 2 Texture colour formats 223 8 4 3 Framebuffer colour formats 223 8 5 Rendering Pipeline 225 8 5 1 Coordinate transformation 225 8 5 2 Rasterization 225 8 5 3 Edge setup linear case 227 8 5 4 Edge setup quadratic case 231 8 5 5 Band filter 234 8 5 6 Clamping unit 235 8 5 7 Combiner unit 236 8 5 8 Rasterization optimization 237 8 5 9 Colouriza...

Page 10: ... 2 SDRAM Refresh Control 297 9 3 Static Memory Interface 302 9 3 1 Static RAM timing 302 9 4 Address Decoder 307 9 4 1 Chip select configuration 307 9 4 2 Address adjustment 311 9 5 Memory Controller Power Down 312 9 6 Memory Controller Registers 314 9 6 1 Memory Controller registers overview 314 9 6 2 Memory Controller registers details 315 Chapter 10 Register List 332 10 Preliminary User s Manua...

Page 11: ...on behind Note Throughout this document the name Ravin L is used for the µPD72256 and Ravin M for the µPD72257 device The graphics controllers provide following features Table 1 1 Ravin L and Ravin M features Feature Ravin L Ravin M Typical display size QVGA HVGA VGA External Memory Controller SDRAM SRAM NOR flash SDRAM SRAM NOR flash External Memory I F width 16 bit data bus 32 bit data bus Inter...

Page 12: ... Output 0 VO0HSYNC VO0VSYNC VO0CLK VO0EN VO0R 5 0 VO0G 5 0 VO0B 5 0 System Controller XT1 XT2 RESET Host I F HLBD 7 0 HADD 15 0 LBus I F ADBus I F HADBEN 1 0 HADA 20 0 HLBWR HLBRD HLBCS HLBDRQ HINT HADWAIT HADWR HADRD HADCS External Memory I F MD 31 0 MA 24 0 MCS0 MCS1 MDCKE MDCLK MDBA 1 0 MDDQM 3 0 MDFBCLK MDA10PC MDRAS MDWE MSOE MSWR MSBEN 3 0 MDCAS Common I F SDRAM I F Static memory I F APB mas...

Page 13: ...used to give the external Host CPU access the control registers of the System Controller Video Input and Drawing Engine The Host I F module is the only APB master AHB The main purpose of the AHB is to transfer video and image content data Since the Video Input and Output modules the Drawing Engine as well as the Host CPU deal with video data these modules can access the AHB as bus masters All vide...

Page 14: ...ock HCLK that is supplied to most modules It is also used to set up and generate the pixel clocks VO0CLK and VO1CLK for the Video Output modules Another important task of the System Controller is the generation of internal reset signals Chapter 1 Introduction 14 Preliminary User s Manual S19203EE1V3UM00 ...

Page 15: ...INMUX BUFPUEN 7 0 is also determined by MODE 3 0 Ravin L Ravin L does not feature different pinout options For Ravin L the boot mode pins MODE 3 0 have to be set to 0011B at release of RESET which sets also SYSBOOTMODE BOOTMODE 3 0 and further SYSPINMUX PINMUX 3 0 to the same value By this the only valid pinout is selected Depending on the boot mode pin MODE9 which enables respectively disables th...

Page 16: ...NC O 12 VO0VSYNC O 13 VO0CLK O 14 n c I O 5 15 n c I O 5 16 DVDD33 PWR n a 17 DGND33 PWR n a 18 n c I O 5 19 n c I O 5 20 n c I O 5 21 n c I O 5 22 n c I O 5 23 DVDD15 PWR n a 24 DGND15 PWR n a 25 n c I O BUFPUEN5 26 n c O 27 MA2 O 28 MA1 O 29 DVDD33 PWR n a 30 DGND33 PWR n a 31 MA0 O 32 MDA10PC O 33 MDBA1 O 34 MDBA0 O 35 MCS0 O 36 MDRAS O 37 MDCAS O 38 MDWE O 39 DVDD33 PWR n a Chapter 2 Pin Funct...

Page 17: ...53 MD14 I O 4 54 MD13 I O 4 55 MD12 I O 4 56 MD11 I O 4 57 MD10 I O 4 58 DGND15 PWR n a 59 DVDD15 PWR n a 60 MD9 I O 4 61 MD8 I O 4 62 MDDQM1 O 63 DVDD33 PWR n a 64 DGND33 PWR n a 65 MDCLK O 66 MDFBCLK I 7 67 MDCKE O 68 MA11 O 69 MA9 O 70 MA8 O 71 MA7 O 72 MA6 O 73 MA5 O 74 DGND33 PWR n a 75 DVDD33 PWR n a 76 MA4 O 77 MA3 O 78 n c O 79 n c I O 5 80 n c I O 5 81 n c I O 5 Pin Functions Chapter 2 Pr...

Page 18: ...96 n c I 6 97 DVDD33 PWR n a 98 DGND33 PWR n a 99 n c I 6 100 n c I 6 101 DVDD33 I 7 102 n c O 1 103 MCS1 O 104 MSWR O 105 MSOE O 106 n c O 107 n c O 108 DVDD15 PWR n a 109 DGND15 PWR n a 110 MSBEN1 O 111 MSBEN0 O 112 DGND33 PWR n a 113 DVDD33 PWR n a 114 MA16 O 115 MA24 O 116 MA23 O 117 MA22 O 118 n c I 0 119 n c I 0 120 n c I 0 121 n c I 0 122 n c I 0 123 n c I 0 Chapter 2 Pin Functions 18 Preli...

Page 19: ...0 MA18 O 2 141 MA17 O 2 142 DGND33 PWR n a 143 DVDD33 PWR n a 144 HLBD7 I O 1 145 HLBD6 I O 1 146 HLBD5 I O 1 147 HLBD4 I O 1 148 HLBD3 I O 1 149 HLBD2 I O 1 150 HLBD1 I O 1 151 HLBD0 I O 1 152 HLBRD I 153 HLBWR I 154 HLBDRQ O 7 155 HLBCS I 7 156 n c I 3 157 DVDD15 PWR n a 158 DGND15 PWR n a 159 AVDD15 PWR n a 160 AGND PWR n a 161 XT1 A n a 162 XT2 A n a 163 RESET I n a 164 DGND33 I 165 VO0R0_MODE...

Page 20: ...MODE4 I O 170 DVDD33 PWR n a 171 DGND33 PWR n a 172 VO0R5_MODE5 I O 173 VO0G0_MODE6 I O 174 VO0G1_MODE7 I O 175 VO0G2_MODE8 I O 176 VO0G3_MODE9 I O n c do not connect this pin leave it open PWR power supply pins n a pull up not applicable no internal pull up Chapter 2 Pin Functions 20 Preliminary User s Manual S19203EE1V3UM00 ...

Page 21: ... 5 15 MD22_VO1G1_MA14 I O 5 16 DVDD33 PWR n a 17 DGND33 PWR n a 18 MD21_VO1G0_MA13 I O 5 19 MD20_VO1B5_MCS1 I O 5 20 MD19_VO1B4_MSWR I O 5 21 MD18_VO1B3_MSOE I O 5 22 MD17_VO1B2_MSBEN1 I O 5 23 DVDD15 PWR n a 24 DGND15 PWR n a 25 MD16_VO1B1_MSBEN0 I O 5 26 MDDQM2_VO0EN_MA24_VO1B1 O 27 MA2 O 28 MA1 O 29 DVDD33 PWR n a 30 DGND33 PWR n a 31 MA0 O 32 MDA10PC O 33 MDBA1 O 34 MDBA0 O 35 MCS0 O 36 MDRAS ...

Page 22: ...4 55 MD12 I O 4 56 MD11 I O 4 57 MD10 I O 4 58 DGND15 PWR n a 59 DVDD15 PWR n a 60 MD9 I O 4 61 MD8 I O 4 62 MDDQM1 O 63 DVDD33 PWR n a 64 DGND33 PWR n a 65 MDCLK O 66 MDFBCLK I 7 67 MDCKE O 68 MA11 O 69 MA9 O 70 MA8 O 71 MA7 O 72 MA6 O 73 MA5 O 74 DGND33 PWR n a 75 DVDD33 PWR n a 76 MA4 O 77 MA3 O 78 MDDQM3_VO1R5_VO1R1 O 79 MD31_VO1R2_MA23 I O 5 80 MD30_VO1R1_MA22 I O 5 81 MD29_VO1CLK_MA21 I O 5 ...

Page 23: ...VI0R1ITU1_MA14 I O 6 100 VI0R0ITU0_MA13 I O 6 101 VI0CLK I 7 102 HADA20_VO1G4 O 1 103 HADA19_VO1R4_MCS1 O 104 HADA18_VO1R3_MSWR O 105 HADA17_VO1R2_MSOE O 106 HADA16_VO1G3_MSBEN3 O 107 HADA15_VO1G2_MSBEN2 O 108 DVDD15 PWR n a 109 DGND15 PWR n a 110 HADA14_VO1R5_MSBEN1 O 111 HADA13_VO1G4_MSBEN0 O 112 DGND33 PWR n a 113 DVDD33 PWR n a 114 HADA12_MA21_MA16_VO1G0 O 115 HADA11_VO1G1_MA24 O 116 HADA10_MA...

Page 24: ...10_MA21_VO1B3 I O 2 140 HADD9_MA18_VO1B2 I O 2 141 HADD8_MA17_VO1G5 I O 2 142 DGND33 PWR n a 143 DVDD33 PWR n a 144 HADD7_HLBD7 I O 1 145 HADD6_HLBD6 I O 1 146 HADD5_HLBD5 I O 1 147 HADD4_HLBD4 I O 1 148 HADD3_HLBD3 I O 1 149 HADD2_HLBD2 I O 1 150 HADD1_HLBD1 I O 1 151 HADD0_HLBD0 I O 1 152 HADRD_HLBRD I 153 HADWR_HLBWR I 154 HADWAIT_HLBDRQ O 7 155 HADCS_HLBCS I 7 156 HADBEN0_VO1R2_VI0G4 I O 3 157...

Page 25: ...MODE4 I O 170 DVDD33 PWR n a 171 DGND33 PWR n a 172 VO0R5_MODE5 I O 173 VO0G0_MODE6 I O 174 VO0G1_MODE7 I O 175 VO0G2_MODE8 I O 176 VO0G3_MODE9 I O n c do not connect this pin leave it open PWR power supply pins n a pull up not applicable no internal pull up Pin Functions Chapter 2 Preliminary User s Manual S19203EE1V3UM00 25 ...

Page 26: ... HADA0_VI0G5_VI0R0ITU0 1 SYSPINMUX BUFPUEN1 102 HADA20_VO1G4 144 HADD7_HLBD7 145 HADD6_HLBD6 146 HADD5_HLBD5 147 HADD4_HLBD4 148 HADD3_HLBD3 149 HADD2_HLBD2 150 HADD1_HLBD1 151 HADD0_HLBD0 2 SYSPINMUX BUFPUEN2 127 HADBEN1_MA24_VO0EN 132 HADD15_MA15_VO1VSYNC 133 HADD14_MA14_VO1HSYNC 134 HADD13_MA13_VO1CLK 137 HADD12_MA19_VO1B5 138 HADD11_MA20_VO1B4 139 HADD10_MA21_VO1B3 140 HADD9_MA18_VO1B2 141 HAD...

Page 27: ...28_VO1VSYNC_MA20 83 MD27_VO1HSYNC_MA19 84 MD26_VO1G5_MA18 87 MD25_VO1G4_MA17 88 MD24_VO1G3_MA16 6 SYSPINMUX BUFPUEN6 91 VI0G1ITU7_MA20_VO1G0 92 VI0G0ITU6_MA19_VO1R1 93 VI0R5ITU5_MA18_VO1R0 94 VI0R4ITU4_MA17_VO1B1 95 VI0R3ITU3_MA16_VO1B0 96 VI0R2ITU2_MA15 99 VI0R1ITU1_MA14 100 VI0R0ITU0_MA13 7 SYSPINMUX BUFPUEN7 66 MDFBCLK 101 VI0CLK 128 HINT 154 HADWAIT_HLBDRQ 155 HADCS_HLBCS Table 2 4 Ravin L pul...

Page 28: ... 148 HLBD3 149 HLBD2 150 HLBD1 151 HLBD0 2 BUFPUEN2 127 VO0EN 132 MA15 133 MA14 134 MA13 137 MA19 138 MA20 139 MA21 140 MA18 141 MA17 3 BUFPUEN3 89 n c 90 n c 156 n c 4 BUFPUEN4 42 MD7 43 MD6 44 MD5 45 MD4 46 MD3 47 MD2 48 MD1 49 MD0 52 MD15 53 MD14 54 MD13 55 MD12 56 MD11 57 MD10 60 MD9 Chapter 2 Pin Functions 28 Preliminary User s Manual S19203EE1V3UM00 ...

Page 29: ... c 20 n c 21 n c 22 n c 25 n c 79 n c 80 n c 81 n c 82 n c 83 n c 84 n c 87 n c 88 n c 6 BUFPUEN6 91 n c 92 n c 93 n c 94 n c 95 n c 96 n c 99 n c 100 n c 7 BUFPUEN7 66 MDFBCLK 101 DVDD33 128 HINT 154 HLBDRQ 155 HLBCS Pin Functions Chapter 2 Preliminary User s Manual S19203EE1V3UM00 29 ...

Page 30: ...oup 0 n c If SYSBOOTMODE BOOTMODE9 1 IRAM enabled SYSPINMUX 00FD 0003H PINMUX 3 0 0011B pinout option 3 fixed all SMUXm 0 no SMUX selection fixed BUFPUEN 7 0 FDH internal pull up resistors enabled for group 7 HINT HLBDRQ HLBCS MDFBCLK group 6 n c group 5 n c group 4 n c group 3 n c group 2 n c group 0 n c Features The Ravin L pinout provides following features 8 bit LBus Host I F multiplexed addre...

Page 31: ...RGB 6 6 6 16 bit SRAM Flash 16 bit SDRAM Internal RAM VO0EN C H VSYNC Host CPU 8 bit multiplexed bus D 7 0 Figure 2 1 Ravin L pinout 2 3 1 Ravin L pin to signals reference The following table lists the signals available for Ravin L pinout option Table 2 5 Ravin L pin to signal reference Pin number Signal 1 VO0G4 2 VO0G5 3 VO0B0 4 VO0B1 5 DVDD33 6 DGND33 7 VO0B2 8 VO0B3 9 VO0B4 10 VO0B5 11 VO0HSYNC...

Page 32: ...30 DGND33 31 MA0 32 MDA10PC 33 MDBA1 34 MDBA0 35 MCS0 36 MDRAS 37 MDCAS 38 MDWE 39 DVDD33 40 DGND33 41 MDDQM0 42 MD7 43 MD6 44 MD5 45 MD4 46 MD3 47 MD2 48 MD1 49 MD0 50 DVDD33 51 DGND33 52 MD15 53 MD14 54 MD13 55 MD12 56 MD11 57 MD10 58 DGND15 59 DVDD15 Chapter 2 Pin Functions 32 Preliminary User s Manual S19203EE1V3UM00 ...

Page 33: ...1 MA7 72 MA6 73 MA5 74 DGND33 75 DVDD33 76 MA4 77 MA3 78 n c 79 n c 80 n c 81 n c 82 n c 83 n c 84 n c 85 DGND33 86 DVDD33 87 n c 88 n c 89 n c 90 n c 91 n c 92 n c 93 n c 94 n c 95 n c 96 n c 97 DVDD33 98 DGND33 99 n c 100 n c 101 DVDD33 102 n c Pin Functions Chapter 2 Preliminary User s Manual S19203EE1V3UM00 33 ...

Page 34: ...4 116 MA23 117 MA22 118 n c 119 n c 120 n c 121 n c 122 n c 123 n c 124 n c 125 n c 126 n c 127 VO0EN 128 HINT 129 DGND33 130 DGND33 131 DVDD33 132 MA15 133 MA14 134 MA13 135 MA12 136 MA10 137 MA19 138 MA20 139 MA21 140 MA18 141 MA17 142 DGND33 143 DVDD33 144 HLBD7 145 HLBD6 Chapter 2 Pin Functions 34 Preliminary User s Manual S19203EE1V3UM00 ...

Page 35: ...LBCS 156 n c 157 DVDD15 158 DGND15 159 AVDD15 160 AGND 161 XT1 162 XT2 163 RESET 164 DGND33 165 VO0R0 166 VO0R1 167 VO0R2 168 VO0R3 169 VO0R4 170 DVDD33 171 DGND33 172 VO0R5 173 VO0G0 174 VO0G1 175 VO0G2 176 VO0G3 n c do not connect leave pin open Pin Functions Chapter 2 Preliminary User s Manual S19203EE1V3UM00 35 ...

Page 36: ...SPINMUX PINMUX 3 0 in signal groups but single signals of the selected signal groups can be replaced by other SMUX signals via dedicated separate multiplexers The separate multiplexers are controlled by the register bits SYSPINMUX SMUXm whereas m stands for the concerned pin number The following figure show the multiplexer configuration Ravin M Core Pin multiplexer SYSPINMUX PINMUX 3 0 MODE 3 0 Sy...

Page 37: ...al pinout options are indicated by lower case alphanumeric characters appended to the option numbers 6 and 7 That results in options 6a 6b and 7a to 7e Setting SYSPINMUX SMUXm 1 outputs a dedicated signal at pin m instead of the signal from the pin multiplexer thus overruling the multiplexing via PINMUX 3 0 Following table summarizes all Ravin M pin multiplexing options Table 2 7 Ravin M PINMUX 3 ...

Page 38: ... LBus 8 bit multiplexed HLBD 7 0 ADBus 16 bit separate HADD 15 0 HADA 20 0 Video Output Video out I F 0 RGB 6 6 6 VO0HSYNC VO0VSYNC VO0EN Video out I F 1 RGB 4 5 4 RGB 5 5 5 RGB 5 6 5 RGB 6 6 6 VO1HSYNC VO1VSYNC Video Input RGB 6 6 6 ITU656 YUV 4 2 2 VI0SYNC1 VI0SYNC2 SDRAM 16 bit data 32 bit data SRAM Flash 16 bit data 32 bit data available not available For further explanations of the various si...

Page 39: ...Pin Functions Chapter 2 Preliminary User s Manual S19203EE1V3UM00 39 ...

Page 40: ...t I F 0 18 bit RGB 6 6 6 composite VO0CSYNC or separate VO0HSYNC VO0VSYNC VO0EN display enable signal Video Input I F ITU656 32 bit SDRAM I F Mem I F 16bit SD SR Host I F 16bit 2MByte System Control Power Supply 3 3V 1 5V Xtal Reset Test 32 bit SDRAM VO0 18bit 6 6 6 VI 18bit ITU656 RGB TFT 18bit 6 6 6 ITU656 RGB18bpp System Control Power Supply 3 3V 1 5V Xtal Reset ITU656 Mem I F 32 bit SDRAM TFT ...

Page 41: ...bit RGB 6 6 6 composite VO0CSYNC or separate VO0HSYNC VO0VSYNC VO0EN display enable signal Video Input I F ITU656 16 bit SDRAM SRAM I F Mem I F 16bit SD SR Host I F 16bit 2MByte System Control Power Supply 3 3V 1 5V Xtal Reset Test 16 bit SDRAM VO0 18bit 6 6 6 VI 18bit ITU656 RGB TFT 18bit 6 6 6 ITU656 RGB18bpp System Control Power Supply 3 3V 1 5V Xtal Reset 16 bit SRAM ITU656 Mem I F 16 bit SDRA...

Page 42: ...B 6 6 6 composite VO0CSYNC or separate VO0HSYNC VO0VSYNC VO0EN display enable signal Video Input I F ITU656 18 bit RGB 6 6 6 composite VI0SYNC1 or separate VI0SYNC1 VI0SYNC2 32 bit SDRAM SRAM I F Xtal Reset 32 bit SRAM Flash Mem I F 32 bit SDRAM SRAM 32 bit SDRAM TFT 18 bit RGB 6 6 6 Video Out 0 18 bit RGB 6 6 6 Host I F 8bit muxed 3 5V System Control Power Supply 3 3V 1 5V Xtal Reset TFT 18 bit R...

Page 43: ...O0EN display enable signal Video Output I F 1 16 bit RGB 5 6 5 composite VO1CSYNC or separate VO1HSYNC VO1VSYNC or VO1HSYNC and VO1EN via VO1VSYNC selectable by SYSVOCTR register Video Input I F ITU656 16 bit SDRAM I F Host I F 8bit muxed 3 5V System Control Power Supply 3 3V 1 5V Xtal Reset Test 32bit SD VO1 16bit 6 6 6 System Control Power Supply 3 3V 1 5V 16 bit SDRAM Xtal Reset TFT 16 bit RGB ...

Page 44: ...Chapter 2 Pin Functions 44 Preliminary User s Manual S19203EE1V3UM00 ...

Page 45: ...RGB 6 6 6 composite VO0CSYNC or separate VO0HSYNC VO0VSYNC VO0EN display enable signal Video Output I F 1 18 bit RGB 6 6 6 composite VO1CSYNC or separate VO1HSYNC VO1VSYNC or VO1HSYNC and VO1EN via VO1VSYNC selectable by SYSVOCTR register 16 bit SDRAM I F Host I F 8bit muxed 3 5V System Control Power Supply 3 3V 1 5V Xtal Reset Test 32bit SD VO1 16bit 6 6 6 System Control Power Supply 3 3V 1 5V 16...

Page 46: ...Chapter 2 Pin Functions 46 Preliminary User s Manual S19203EE1V3UM00 ...

Page 47: ...it RGB 4 5 4 composite VO1CSYNC or separate VO1HSYNC VO1VSYNC or VO1HSYNC and VO1EN via VO1VSYNC selectable by SYSVOCTR register Video Input I F ITU656 32 bit SDRAM SRAM I F Xtal Reset 32 bit SRAM Flash Mem I F 32 bit SDRAM SRAM 32 bit SDRAM Host I F 8bit muxed 3 5V System Control Power Supply 3 3V 1 5V Xtal Reset System Control Power Supply 3 3V 1 5V LBus Host I F 8 bit multiplexed TFT 18 bit RGB...

Page 48: ...nal Video Output I F 1 13 bit RGB 4 5 4 composite VO1CSYNC or separate VO1HSYNC VO1VSYNC or VO1HSYNC and VO1EN via VO1VSYNC selectable by SYSVOCTR register Video Input I F ITU656 32 bit SDRAM SRAM I F CSYNC Xtal Reset 32 bit SRAM Flash Mem I F 32 bit SDRAM SRAM 32 bit SDRAM Host I F 8bit muxed 3 5V System Control Power Supply 3 3V 1 5V Xtal Reset System Control Power Supply 3 3V 1 5V LBus Host I F...

Page 49: ...Pin Functions Chapter 2 Preliminary User s Manual S19203EE1V3UM00 49 ...

Page 50: ...e VO0HSYNC VO0VSYNC VO0EN display enable signal Video Output I F 1 18 bit RGB 6 6 6 composite VO1CSYNC or separate VO1HSYNC VO1VSYNC or VO1HSYNC and VO1EN via VO1VSYNC selectable by SYSVOCTR register Video Input I F ITU656 32 bit SDRAM SRAM I F Xtal Reset 32 bit SRAM Flash Mem I F 32 bit SDRAM SRAM 32 bit SDRAM Host I F 8bit muxed 3 5V System Control Power Supply 3 3V 1 5V Xtal Reset System Contro...

Page 51: ...lay enable signal Video Output I F 1 13 bit RGB 4 5 4 composite VO1CSYNC or separate VO1HSYNC VO1VSYNC or VO1HSYNC and VO1EN via VO1VSYNC selectable by SYSVOCTR register Video Input I F ITU656 32 bit SDRAM SRAM I F Xtal Reset 32 bit SRAM Flash Mem I F 32 bit SDRAM SRAM 32 bit SDRAM Host I F 8bit muxed 3 5V System Control Power Supply 3 3V 1 5V Xtal Reset System Control Power Supply 3 3V 1 5V LBus ...

Page 52: ...Chapter 2 Pin Functions 52 Preliminary User s Manual S19203EE1V3UM00 ...

Page 53: ...ate VO0HSYNC VO0VSYNC Video Output I F 1 15 bit RGB 5 5 5 composite VO1CSYNC or separate VO1HSYNC VO1VSYNC or VO1HSYNC and VO1EN via VO1VSYNC selectable by SYSVOCTR register Video Input I F ITU656 16 bit SDRAM SRAM I F Xtal Reset 16 bit SRAM Flash Mem I F 16 bit SDRAM SRAM 16 bit SDRAM Host I F 8bit muxed 3 5V System Control Power Supply 3 3V 1 5V Xtal Reset System Control Power Supply 3 3V 1 5V L...

Page 54: ...Chapter 2 Pin Functions 54 Preliminary User s Manual S19203EE1V3UM00 ...

Page 55: ...F 1 16 bit RGB 5 6 5 composite VO1CSYNC or separate VO1HSYNC VO1VSYNC or VO1HSYNC and VO1EN via VO1VSYNC selectable by SYSVOCTR register Video Input I F ITU656 18 bit RGB 6 6 6 composite VI0SYNC1 or separate VI0SYNC1 VI0SYNC2 32 bit SDRAM I F Host I F 8bit muxed 3 5V System Control Power Supply 3 3V 1 5V Xtal Reset Test 32bit SD VO1 16bit 6 6 6 System Control Power Supply 3 3V 1 5V 32 bit SDRAM Xt...

Page 56: ... VO0B2 VO0B2 8 VO0B3 VO0B3 VO0B3 VO0B3 VO0B3 9 VO0B4 VO0B4 VO0B4 VO0B4 VO0B4 10 VO0B5 VO0B5 VO0B5 VO0B5 VO0B5 11 VO0HSYNC VO0HSYNC VO0HSYNC VO0HSYNC VO0HSYNC 12 VO0VSYNC VO0VSYNC VO0VSYNC VO0VSYNC VO0VSYNC 13 VO0CLK VO0CLK VO0CLK VO0CLK VO0CLK 14 MD23 MA15 MD23 VO1G2 VO1G2 15 MD22 MA14 MD22 VO1G1 VO1G1 16 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 17 DGND33 DGND33 DGND33 DGND33 DGND33 18 MD21 MA13 MD21 VO...

Page 57: ...QM0 42 MD7 MD7 MD7 MD7 MD7 43 MD6 MD6 MD6 MD6 MD6 44 MD5 MD5 MD5 MD5 MD5 45 MD4 MD4 MD4 MD4 MD4 46 MD3 MD3 MD3 MD3 MD3 47 MD2 MD2 MD2 MD2 MD2 48 MD1 MD1 MD1 MD1 MD1 49 MD0 MD0 MD0 MD0 MD0 50 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 51 DGND33 DGND33 DGND33 DGND33 DGND33 52 MD15 MD15 MD15 MD15 MD15 53 MD14 MD14 MD14 MD14 MD14 54 MD13 MD13 MD13 MD13 MD13 55 MD12 MD12 MD12 MD12 MD12 56 MD11 MD11 MD11 MD11 M...

Page 58: ...1HSYNC VO1HSYNC 84 MD26 MA18 MD26 VO1G5 VO1G5 85 DGND33 DGND33 DGND33 DGND33 DGND33 86 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 87 MD25 MA17 MD25 VO1G4 VO1G4 88 MD24 MA16 MD24 VO1G3 VO1G3 89 leave open leave open VI0G3 VO1R4 VO1R4 90 VO0EN VO0EN VI0G2 VO1R3 VO1R3 91 VI0G1_ITU7 VI0G1_ITU7 VI0G1_ITU7 VI0G1_ITU7 VI0G1_ITU7 92 VI0G0_ITU6 VI0G0_ITU6 VI0G0_ITU6 VI0G0_ITU6 VI0G0_ITU6 93 VI0R5_ITU5 VI0R5_ITU5 V...

Page 59: ...ADA11 HADA11 MA24 HADA11 HADA11 116 HADA10 HADA10 MA23 HADA10 HADA10 117 HADA9 HADA9 MA22 HADA9 HADA9 118 HADA8 HADA8 VI0SYNC2 HADA8 HADA8 119 HADA7 HADA7 VI0SYNC1 HADA7 HADA7 120 HADA6 HADA6 VI0B5 HADA6 HADA6 121 HADA5 HADA5 VI0B4 HADA5 HADA5 122 HADA4 HADA4 VI0B3 HADA4 HADA4 123 HADA3 HADA3 VI0B2 HADA3 HADA3 124 HADA2 HADA2 VI0B1 HADA2 HADA2 125 HADA1 HADA1 VI0B0 HADA1 HADA1 126 HADA0 HADA0 VI0G...

Page 60: ...D0 HADD0 HADD0 152 HADRD HADRD HLBRD HADRD HADRD 153 HADWR HADWR HLBWR HADWR HADWR 154 HADWAIT HADWAIT HLBDRQ HADWAIT HADWAIT 155 HADCS HADCS HLBCS HADCS HADCS 156 HADBEN0 HADBEN0 VI0G4 HADBEN0 HADBEN0 157 DVDD15 DVDD15 DVDD15 DVDD15 DVDD15 158 DGND15 DGND15 DGND15 DGND15 DGND15 159 AVDD15 AVDD15 AVDD15 AVDD15 AVDD15 160 AGND AGND AGND AGND AGND 161 XT1 XT1 XT1 XT1 XT1 162 XT2 XT2 XT2 XT2 XT2 163 ...

Page 61: ...B0 VO0B0 4 VO0B1 VO0B1 VO0B1 VO0B1 VO0B1 VO0B1 5 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 6 DGND33 DGND33 DGND33 DGND33 DGND33 DGND33 7 VO0B2 VO0B2 VO0B2 VO0B2 VO0B2 VO0B2 8 VO0B3 VO0B3 VO0B3 VO0B3 VO0B3 VO0B3 9 VO0B4 VO0B4 VO0B4 VO0B4 VO0B4 VO0B4 10 VO0B5 VO0B5 VO0B5 VO0B5 VO0B5 VO0B5 11 VO0HSYNC VO0HSYNC VO0HSYNC VO0HSYNC VO0HSYNC VO0HSYNC 12 VO0VSYNC VO0EN VO0VSYNC VO0VSYNC VO0VSYNC VO0VSYNC 1...

Page 62: ...CAS MDCAS MDCAS MDCAS 38 MDWE MDWE MDWE MDWE MDWE MDWE 39 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 40 DGND33 DGND33 DGND33 DGND33 DGND33 DGND33 41 MDDQM0 MDDQM0 MDDQM0 MDDQM0 MDDQM0 MDDQM0 42 MD7 MD7 MD7 MD7 MD7 MD7 43 MD6 MD6 MD6 MD6 MD6 MD6 44 MD5 MD5 MD5 MD5 MD5 MD5 45 MD4 MD4 MD4 MD4 MD4 MD4 46 MD3 MD3 MD3 MD3 MD3 MD3 47 MD2 MD2 MD2 MD2 MD2 MD2 48 MD1 MD1 MD1 MD1 MD1 MD1 49 MD0 MD0 MD0 MD0 MD...

Page 63: ...ND33 DGND33 75 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 76 MA4 MA4 MA4 MA4 MA4 MA4 77 MA3 MA3 MA3 MA3 MA3 MA3 78 MDDQM3 MDDQM3 MDDQM3 MDDQM3 VO1R1 MDDQM3 79 MD31 MD31 MD31 MD31 MD31 MD31 80 MD30 MD30 MD30 MD30 MD30 MD30 81 MD29 MD29 MD29 MD29 MD29 MD29 82 MD28 MD28 MD28 MD28 MD28 MD28 83 MD27 MD27 MD27 MD27 MD27 MD27 84 MD26 MD26 MD26 MD26 MD26 MD26 85 DGND33 DGND33 DGND33 DGND33 DGND33 DGND33 86...

Page 64: ...VDD33 DVDD33 DVDD33 114 MA21 MA21 MA21 MA21 MA21 VO1G0 115 VO1G1 VO1G1 VO1G1 VO1G1 VO1G1 VO1G1 116 MA23 MA23 MA23 MA23 MA23 VO1R1 117 MA22 MA22 MA22 MA22 MA22 VO1B1 118 VO1R5 VO1R5 VO1R5 VO1R5 VO1R5 VI0SYNC2 119 VI0G1_ITU7 VI0G1_ITU7 VI0G1_ITU7 VI0G1_ITU7 VI0G1_ITU7 VI0SYNC1 120 VI0G0_ITU6 VI0G0_ITU6 VI0G0_ITU6 VI0G0_ITU6 VI0G0_ITU6 VI0B5 121 VI0R5_ITU5 VI0R5_ITU5 VI0R5_ITU5 VI0R5_ITU5 VI0R5_ITU5 ...

Page 65: ...HLBD5 147 HLBD4 HLBD4 HLBD4 HLBD4 HLBD4 HLBD4 148 HLBD3 HLBD3 HLBD3 HLBD3 HLBD3 HLBD3 149 HLBD2 HLBD2 HLBD2 HLBD2 HLBD2 HLBD2 150 HLBD1 HLBD1 HLBD1 HLBD1 HLBD1 HLBD1 151 HLBD0 HLBD0 HLBD0 HLBD0 HLBD0 HLBD0 152 HLBRD HLBRD HLBRD HLBRD HLBRD HLBRD 153 HLBWR HLBWR HLBWR HLBWR HLBWR HLBWR 154 HLBDRQ HLBDRQ HLBDRQ HLBDRQ HLBDRQ HLBDRQ 155 HLBCS HLBCS HLBCS HLBCS HLBCS HLBCS 156 VO1R2 VO1R2 VO1R2 VO1R2 ...

Page 66: ...tion 7a Option 7b Option 7c Option 7d Option 7e Option 9 170 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 171 DGND33 DGND33 DGND33 DGND33 DGND33 DGND33 172 VO0R5 VO0R5 VO0R5 VO0R5 VO0R5 VO0R5 173 VO0G0 VO0G0 VO0G0 VO0G0 VO0G0 VO0G0 174 VO0G1 VO0G1 VO0G1 VO0G1 VO0G1 VO0G1 175 VO0G2 VO0G2 VO0G2 VO0G2 VO0G2 VO0G2 176 VO0G3 VO0G3 VO0G3 VO0G3 VO0G3 VO0G3 Chapter 2 Pin Functions 66 Preliminary User s Manua...

Page 67: ... used as they are clamped to high level internally Caution According to the chosen pinout option pull up resistors are activated in order to prevent malfunction of the graphics controller due to unspecified pin levels Since the pull up resistors can be disabled respectively enabled in groups by modifying SYSPINMUX BUFPUEN 7 0 take care for external pin level fixation if the internal pull up resist...

Page 68: ... DGND33 n a DGND33 n a DGND33 n a DGND33 n a 31 MA0 open MA0 open MA0 open MA0 open 32 MDA10PC open MDA10PC open MDA10PC open MDA10PC open 33 MDBA1 open MDBA1 open MDBA1 open MDBA1 open 34 MDBA0 open MDBA0 open MDBA0 open MDBA0 open 35 MCS0 open MCS0 open MCS0 open MCS0 open 36 MDRAS open MDRAS open MDRAS open MDRAS open 37 MDCAS open MDCAS open MDCAS open MDCAS open 38 MDWE open MDWE open MDWE op...

Page 69: ...A8 open MA8 open 71 MA7 open MA7 open MA7 open MA7 open 72 MA6 open MA6 open MA6 open MA6 open 73 MA5 open MA5 open MA5 open MA5 open 74 DGND33 n a DGND33 n a DGND33 n a DGND33 n a 75 DVDD33 n a DVDD33 n a DVDD33 n a DVDD33 n a 76 MA4 open MA4 open MA4 open MA4 open 77 MA3 open MA3 open MA3 open MA3 open 78 MDDQM3 open unused open MDDQM3 open VO1R5 open 79 MD31 open MA23 open MD31 open VO1R2 open ...

Page 70: ...GND15 n a 110 HADA14 open HADA14 open MSBEN1 open HADA14 open 111 HADA13 open HADA13 open MSBEN0 open HADA13 open 112 DGND33 n a DGND33 n a DGND33 n a DGND33 n a 113 DVDD33 n a DVDD33 n a DVDD33 n a DVDD33 n a 114 HADA12 open HADA12 open MA16 open HADA12 open 115 HADA11 open HADA11 open MA24 open HADA11 open 116 HADA10 open HADA10 open MA23 open HADA10 open 117 HADA9 open HADA9 open MA22 open HADA...

Page 71: ...D1 open HADD1 open HLBD1 open HADD1 open 151 HADD0 open HADD0 open HLBD0 open HADD0 open 152 HADRD open HADRD open HLBRD open HADRD open 153 HADWR open HADWR open HLBWR open HADWR open 154 HADWAIT iPU HADWAIT iPU HLBDRQ iPU HADWAIT iPU 155 HADCS iPU HADCS iPU HLBCS iPU HADCS iPU 156 HADBEN0 n a HADBEN0 n a VIG4 iPU HADBEN0 n a 157 DVDD15 n a DVDD15 n a DVDD15 n a DVDD15 n a 158 DGND15 n a DGND15 n...

Page 72: ... VO0B4 open VO0B4 open 10 VO0B5 open VO0B5 open VO0B5 open VO0B5 open 11 VO0HSYNC open VO0HSYNC open VO0HSYNC open VO0HSYNC open 12 VO0VSYNC open VO0VSYNC open VO0EN open VO0VSYNC open 13 VO0CLK open VO0CLK open VO0CLK open VO0CLK open 14 VO1G2 open MD23 open MD23 open MD23 open 15 VO1G1 open MD22 open MD22 open MD22 open 16 DVDD33 n a DVDD33 n a DVDD33 n a DVDD33 n a 17 DGND33 n a DGND33 n a DGND...

Page 73: ...MD1 open MD1 open MD1 open 49 MD0 open MD0 open MD0 open MD0 open 50 DVDD33 n a DVDD33 n a DVDD33 n a DVDD33 n a 51 DGND33 n a DGND33 n a DGND33 n a DGND33 n a 52 MD15 open MD15 open MD15 open MD15 open 53 MD14 open MD14 open MD14 open MD14 open 54 MD13 open MD13 open MD13 open MD13 open 55 MD12 open MD12 open MD12 open MD12 open 56 MD11 open MD11 open MD11 open MD11 open 57 MD10 open MD10 open MD...

Page 74: ...pen 89 VO1R4 open VO1R4 open VO1R4 open VO1R4 open 90 VO1R3 open VO1R3 open VO1R3 open VO1R3 open 91 unused iPU MA20 open MA20 open VO1G0 open 92 unused iPU MA19 open MA19 open VO1R1 open 93 VO1R0 iPU MA18 open MA18 open VO1R0 open 94 unused iPU MA17 open MA17 open VO1B1 open 95 VO1B0 iPU MA16 open MA16 open VO1B0 open 96 unused iPU MA15 open MA15 open MA15 open 97 DVDD33 n a DVDD33 n a DVDD33 n a...

Page 75: ...MA24 open MA24 open VO0EN open 128 HINT iPU HINT iPU HINT iPU HINT iPU 129 DGND33 n a DGND33 n a DGND33 n a DGND33 n a 130 DGND33 n a DGND33 n a DGND33 n a DGND33 n a 131 DVDD33 n a DVDD33 n a DVDD33 n a DVDD33 n a 132 HADD15 open VO1VSYNC open VO1VSYNC open VO1VSYNC open 133 HADD14 open VO1HSYNC open VO1HSYNC open VO1HSYNC open 134 HADD13 open VO1CLK open VO1CLK open VO1CLK open 135 MA12 open MA1...

Page 76: ...R2 open VO0R2 open 168 VO0R3 open VO0R3 open VO0R3 open VO0R3 open 169 VO0R4 open VO0R4 open VO0R4 open VO0R4 open 170 DVDD33 n a DVDD33 n a DVDD33 n a DVDD33 n a 171 DGND33 n a DGND33 n a DGND33 n a DGND33 n a 172 VO0R5 open VO0R5 open VO0R5 open VO0R5 open 173 VO0G0 open VO0G0 open VO0G0 open VO0G0 open 174 VO0G1 open VO0G1 open VO0G1 open VO0G1 open 175 VO0G2 open VO0G2 open VO0G2 open VO0G2 op...

Page 77: ...n MD16 open MD16 open unused iPU 26 MDDQM2 open VO1B1 open MDDQM2 open unused open 27 MA2 open MA2 open MA2 open MA2 open 28 MA1 open MA1 open MA1 open MA1 open 29 DVDD33 n a DVDD33 n a DVDD33 n a DVDD33 n a 30 DGND33 n a DGND33 n a DGND33 n a DGND33 n a 31 MA0 open MA0 open MA0 open MA0 open 32 MDA10PC open MDA10PC open MDA10PC open MDA10PC open 33 MDBA1 open MDBA1 open MDBA1 open MDBA1 open 34 M...

Page 78: ... n a DGND33 n a 65 MDCLK open MDCLK open MDCLK open MDCLK open 66 MDFBCLK iPU MDFBCLK iPU MDFBCLK iPU MDFBCLK iPU 67 MDCKE open MDCKE open MDCKE open MDCKE open 68 MA11 open MA11 open MA11 open MA11 open 69 MA9 open MA9 open MA9 open MA9 open 70 MA8 open MA8 open MA8 open MA8 open 71 MA7 open MA7 open MA7 open MA7 open 72 MA6 open MA6 open MA6 open MA6 open 73 MA5 open MA5 open MA5 open MA5 open 7...

Page 79: ... VO1R2 open MSOE open 106 VO1G3 open VO1G3 open VO1G3 open unused open 107 VO1G2 open VO1G2 open VO1G2 open unused open 108 DVDD15 n a DVDD15 n a DVDD15 n a DVDD15 n a 109 DGND15 n a DGND15 n a DGND15 n a DGND15 n a 110 MSBEN1 open MSBEN1 open VO1R5 open MSBEN1 open 111 MSBEN0 open MSBEN0 open unused open MSBEN0 open 112 DGND33 n a DGND33 n a DGND33 n a DGND33 n a 113 DVDD33 n a DVDD33 n a DVDD33 ...

Page 80: ...pen HLBD7 open HLBD7 open HLBD7 open 145 HLBD6 open HLBD6 open HLBD6 open HLBD6 open 146 HLBD5 open HLBD5 open HLBD5 open HLBD5 open 147 HLBD4 open HLBD4 open HLBD4 open HLBD4 open 148 HLBD3 open HLBD3 open HLBD3 open HLBD3 open 149 HLBD2 open HLBD2 open HLBD2 open HLBD2 open 150 HLBD1 open HLBD1 open HLBD1 open HLBD1 open 151 HLBD0 open HLBD0 open HLBD0 open HLBD0 open 152 HLBRD open HLBRD open H...

Page 81: ...GND33 n a DGND33 n a DGND33 n a DGND33 n a 172 VO0R5 open VO0R5 open VO0R5 open VO0R5 open 173 VO0G0 open VO0G0 open VO0G0 open VO0G0 open 174 VO0G1 open VO0G1 open VO0G1 open VO0G1 open 175 VO0G2 open VO0G2 open VO0G2 open VO0G2 open 176 VO0G3 open VO0G3 open VO0G3 open VO0G3 open a If the internal RAM of Ravin L is enabled SYSBOOTMODE BOOTMODE9 1 internal pull up resistors of the external memory...

Page 82: ...s During reset all input pins are not active all other pins are in Hi Z state For a period of four oscillator clocks CLKIN with its frequency of the external resonator at XT1 XT2 after reset release all input pins are active all other pins remain in Hi Z or are internally fixed to high level if the pin is equipped with an activated internal pull up resistor After four oscillator clocks CLKIN after...

Page 83: ...he internal SRAM is enabled The internal SRAM is enabled by SYSCLKCTRL IRAMCLKEN 1 Table 3 1 Ravin L memory and register map internal SRAM enabled Address range Bus Target 0000 0000H to 0000 002FH Host I F module internal Host I F registers 0000 030H to 0000 07FFH Reserved 0000 0800H to 0000 08FFH APB System Controller registers 0000 0900H to 0000 1CFFH Reserved 0000 1D00H to 0000 1DFFH Drawing En...

Page 84: ...00H to 0000 3FFFH Memory Controller registers 0000 4000H to 0000 4FFFH Reserved 0000 5000H to 07FF FFFFH External memory bus 0800 0000H to FFFF FFFFH Reserved Table 3 3 Ravin L AHB master priorities Priority AHB master 1 highest Host I F 2 Video Output 0 framebuffer access 3 lowest Drawing Engine framebuffer access Chapter 3 Memory and Register Map 84 Preliminary User s Manual S19203EE1V3UM00 ...

Page 85: ...isters 0000 1E00H to 0000 1EFFH Video Input module registers 0000 1F00H to 0000 1FFFH Reserved 0000 2000H to 0000 2FFFH AHB Video Output 0 registers 0000 3000H to 0000 3FFFH Memory Controller registers 0000 4000H to 0000 4FFFH Video Output 1 registers 0000 5000H to 07FF FFFFH External memory bus 0800 0000H to FFFF FFFFH Reserved Table 3 5 Ravin M AHB master priorities Priority AHB master 1 highest...

Page 86: ...Controller register addresses are given as address offsets to the base address SysC_Base The SysC_Base address of the System Controller is given in the following table System Controller SysC_Base address SysC 0000 0800H 86 Preliminary User s Manual S19203EE1V3UM00 ...

Page 87: ...ystem Controller functions VISEL 1 0 APB Pin mux XT1 XT2 MODE 11 0 WDRESET SWRESET Reset control Boot mode control Video Input control Pin mux control System watchdog Clock generator Registers PLLRESET SYSRESET HCLK IRAMCLK VO0CLK VO1CLK Memory I F control VIEN Video Output 1 control Video Output 0 control VO1RAMEN VO0LOCKEN VO1LOCKEN VO0CSSEL VO0RAMEN VO1CSSEL VO1VSSEL VO0VSSEL SDREN IRAMCKEN APB...

Page 88: ...K IRAMCLK VO0CLK VO1CLK IRAMCKEN IRAM clock control Figure 4 2 Clock Generator The entire clock generator is controlled by means of the SYSPLLCTRL and SYSCLKCTRL registers Boot mode The default values i e the values after release of the external RESET are subject to the boot mode function Thus one out of four default settings for SYSPLLCTRL and SYSCLKCTRL are chosen depending on the MODE 5 4 pins ...

Page 89: ...ncerning the allowed settings of the PLL parameters refer to the description of the SYSPLLCTRL register SYSPLLCTRL MDIV 6 0 SYSPLLCTRL NDIV 6 0 SYSPLLCTRL PC SYSPLLCTRL MDL 1 0 SYSPLLCTRL ADJ 2 0 SYSPLLCTRL S 1 0 CLKIN VCOIN VCOOUT PLLCLKOUT PLL VCO 1 m 1 n 1 2p SYSPLLCTRL PDIV 1 0 Figure 4 3 PLL configuration New PLL parameters set up in SYSPLLCTRL are becoming effective only after a reset has be...

Page 90: ...ut interfaces The frequencies of VOxCLK is calculated as follows for SYSCLKCTRL VOxDIV 5 0 0 fVOxCLK fPLLCKOUT VOxDIV 5 0 1 for SYSCLKCTRL VOxDIV 5 0 0 fVOxCLK fPLLCKOUT 2 Boot mode The default values of SYSCLKCTRL VO0DIV 5 0 and SYSCLKCTRL VO1DIV 5 0 are subject to the boot mode function and depend on the MODE4 and MODE8 pin levels at RESET release 4 2 4 Internal RAM clock Ravin L only The clock ...

Page 91: ...on the reset source external RESET An external RESET sets the SYSPLLCTRL register to its default values defined by MODE 5 4 and restarts the PLL with the default parameters in SYSPLLCTRL by user SYSRESET PLLRESET 1 This user reset restart only the PLL but does not reset the SYSPLLCTRL register and hence does not apply the MODE 5 4 default settings to the register Purpose of this reset is to enable...

Page 92: ... to ensure a stable internal main system clock HCLK prior to release of all internal modules the internal SYSRESET remains active for some time after the PLL restart reset is released As a consequence all modules will not be in operation until SYSRESET is deasserted The diagrams below outline the initial start timing initiated by an external RESET and restart timing initiated by SYSRESET PLLRESET ...

Page 93: ...At the end of TPLLSTART the reset interrupt RESINT is asserted which has to be cleared by the Host CPU 4 3 3 Host CPU synchronization Since the graphics controller is not operable until release of the internal SYSRESET the Host CPU must not access the graphics controller until deassertion of SYSRESET Thus the Host CPU has to wait for the end of the TPLLSTART respectively TSWSTART period before acc...

Page 94: ...Functions The System Controller incorporates facilities to control several functions of other modules 4 5 1 Internal RAM control Ravin L only Prior using the Ravin L internal RAM its clock IRAMCLK has to be enabled This is done by SYSCLKCTRL IRAMCLKEN 0 IRAMCLK disabled SYSCLKCTRL IRAMCLKEN 1 IRAMCLK enabled The default setting of SYSCLKCTRL IRAMCLKEN is subject to the boot mode function and depen...

Page 95: ...es particular attention as a special sequence must be applied Refer to the section Start and stop of video capturing 4 5 3 2 Video Input source selection For testing and evaluation purposes the graphics controllers provide a loop back mode that allows to capture the video data output from the Video Output module by the Video Input module without external connections The Video Input source is selec...

Page 96: ...OL RGBEN 1 VInCONTROL RGBSEL 0 VOnLCDCONTROL LCDBPP 2 0 110B RGB 666 VInCONTROL RGBEN 1 VInCONTROL RGBSEL 1 VOnLCDCONTROL LCDBPP 2 0 101B VInCONTROL RGBEN 1 VInCONTROL RGBSEL 1 VInSCALING MX 6 0 00H VInSCALING NX 5 0 00H VOnLCDCONTROL LCDBPP 2 0 011B a Data clock phase rising edge sampling VInCONTROL CLKPH 0 VOnLCDTIMING2 IPC 1 falling edge sampling VInCONTROL CLKPH 1 VOnLCDTIMING2 IPC 0 Sync mode...

Page 97: ...ion of Video Output synchronization signals can be selected SYSVOCTRL CSYNCSELn 0 separate sync signals VOnVSYNC VOnHSYNC SYSVOCTRL CSYNCSELn 1 composite sync signal VOnCSYNC output instead of VOnHSYNC pin After release of RESET SYSVOCTRL CSYNCSELn is set to 0 thus separate sync signals VOnVSYNC VOnHSYNC are generated CLUT RAM enable The colour look up table palette RAM can be en or disabled SYSVO...

Page 98: ...l set to L level MODE7 enable H disable L SDRAM enable H disable L SDRAM MODE8 set to L level set to H level MODE9 enable H disable L IRAM set to L level MODE10 software application use software application use MODE11 set to L level set to L level MODE 3 0 Pin configuration Ravin M only MODE 3 0 are stored in SYSBOOTMODE BOOTMODE 3 0 after RESET release and are used to select a certain Ravin M pin...

Page 99: ...E8 1 Ravin M Refer also to the description of the SYSBOOTMODE register MODE9 Internal RAM enable Ravin L only MODE9 is used to enable the clock for the internal RAM after RESET release MODE9 is stored in SYSBOOTMODE BOOTMODE9 and is used to set the reset value of the SYSCLKCTRL IRAMCLKEN bit Refer also to the description of the SYSBOOTMODE and SYSCLKCTRL registers MODE10 User defined configuration...

Page 100: ...ss of the registers are defined in the first section of this chapter under the key word Register base addresses 4 7 2 System Controller registers write protection Generally all System Controller registers are read only and hence are protected against unintentional write accesses For unlocking the registers for write accesses the SYSPROTECT register has to be written with the value 0000 00A5H prior...

Page 101: ...25 24 23 22 21 20 19 18 17 16 S 1 0 MDL 1 0 0 ADJ 1 0 0 0 0 PC 0 0 PDIV 1 0 R W R W R R W R R R R W R R R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 NDIV 6 0 0 MDIV 6 0 R R W R R W Writing to the read only bits is ignored reading returns undefined values Bit Bit name Function 31 to 30 S 1 0 S selector only valid if PC 1 29 to 28 MDL 1 0 Modulation frequency range selection only valid if PC 1 26 to ...

Page 102: ... 00B 15 KHz to 25 KHz 00B 1 00 fVCOIN 1 20 001B ca 1 0 01B 25 KHz to 35 KHz 01B 1 20 fVCOIN 1 45 010B ca 2 0 10B 34 KHz to 46 KHz 10B 1 45 fVCOIN 1 70 011B ca 3 0 11B 45 KHz to 65 KHz 11B 1 70 fVCOIN 2 00 100B ca 4 0 101B ca 5 0 110B to 111B invalid The default reset value of SYSPLLCTRL is determined by the MODE 5 4 pin level at de assertion of RESET Thus one out of 4 default reset PLL configurati...

Page 103: ...ed fCLKIN Resulting fPLLCKOUT 11B B510 5F0BH NDIV 95 MDIV 11 PDIV 0 PC 1 ADJ 5 MDL 3 S 2 20 MHz 160 MHz dithering on modulation frequency 45 65 KHz dither range ca 5 System Controller Chapter 4 Preliminary User s Manual S19203EE1V3UM00 103 ...

Page 104: ...31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SDR EN IRAM CLK ENa 0 0 0 0 0 0 0 0 VO1DIV 5 0 R W R W R R R R R R R R R W a Ravin L only 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 BUSDIV 1 0 0 0 VO0DIV 5 0 R R R R R R R W R R R W Writing to the read only bits is ignored reading returns undefined values Bit Bit name Function 31 SDREN SDREN enables disables the external SDRAM 0 SDRAM disable...

Page 105: ...register for Ravin L and Ravin M Table 4 8 Ravin L SYSCLKCTRL reset values MODE9 IRAMCLKEN MODE7 SDREN MODE4 dividers Reset value 0 0 0 003F 0317H 0 0 1 003F 032FH 0 1 0 803F 0317H 0 1 1 803F 032FH 1 0 0 403F 0317H 1 0 1 403F 032FH 1 1 0 C03F 0317H 1 1 1 C03F 032FH Table 4 9 Ravin M SYSCLKCTRL reset values MODE7 SDREN MODE4 dividers Reset value 0 0 0017 0105H 0 1 0017 0104H 1 0 8017 0105H 1 1 8017...

Page 106: ...K and HCLK are calculated as follows fVOxCLK fPLLCLKOUT VOxDIV 1 fHCLK fPLLCLKOUT BUSDIV 1 The tables below summarize the default clock settings for Ravin L respectively Ravin M under the assumption that SYSPLLCTRL holds any of the default settings and has not been modified i e fPLLCLKOUT 160 MHz Table 4 10 Ravin L default clock settings MODE4 SYSCLKCTRL 23 0 reset value Resulting fHCLK Resulting ...

Page 107: ...28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 SWR ESET 0 0 0 PLLR ESET R R R R R R R R R R R R W R R R R W Writing to the read only bits is ignored reading returns undefined values Bit Bit name Function 4 SWRESET Software reset Resets all modules except the PLL Writing 1 asserts the...

Page 108: ... Bit Bit name Function 11 BOOTMODE11 Level of MODE11 pin the level of MODE11 must be set to 0 thus BOOTMODE11 0 10 BOOTMODE10 Level of MODE10 pin this pin and bit can be used for application purposes by the application software 9 BOOTMODE9 Level of MODE9 pin enable internal SRAM 0 internal SRAM disabled 1 internal SRAM enabled 8 BOOTMODE8 Level of MODE8 pin selects the graphic controller type 0 Ra...

Page 109: ...ial Value 0000 0001H This register is never modified 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MAJOR MINOR R R Bit Bit name Function 15 to 8 MAJOR Major revision number 7 to 0 MINOR Minor revision number System Controller Chapter 4 Preliminary User s Manual S19203EE1V3UM00 109 ...

Page 110: ... 3 2 1 0 0 0 0 SMUX 91 SMUX 92 SMUX 93 SMUX 94 SMUX 95 SMUX 12 SMUX 78 SMUX 26 SMU X127 PINMUX 3 0 R R R W R W R W R W R W R W R W R W R W R W R W Writing to the read only bits is ignored reading returns undefined values Caution The default value 0 of bit 13 must not be changed Bit Bit name Function 23 BUFPUEN7 Internal pull up resistor control of pin group 7 0 internal pull up disabled 1 internal...

Page 111: ...termined by PINMUX 3 0 1 VO1R1 output 10 SMUX93 Pin 93 multiplexer control 0 output determined by PINMUX 3 0 1 VO1R0 output 9 SMUX94 Pin 94 multiplexer control 0 output determined by PINMUX 3 0 1 VO1B1 output 8 SMUX95 Pin 95 multiplexer control 0 output determined by PINMUX 3 0 1 VO1B0 output 7 SMUX12 Pin 12 multiplexer control 0 output determined by PINMUX 3 0 1 VO0EN output 6 SMUX78 Pin 78 multi...

Page 112: ...rther information concerning the pin groups 7 to 0 refer to the chapter Pin Function Ravin M For Ravin M SYSBOOTMODE BOOTMODE8 1 the reset value of SYSPINMUX BUFPUEN 7 0 depend on the chosen pin multiplex option SYSBOOTMODE BOOTMODE 3 0 MODE 3 0 pin Table 4 12 Ravin M SYSPINMUX reset values SYSBOOTMODE BOOTMODE 3 0 SYSPINMUX BUFPUEN SYSPINMUX reset value 7 6 5 4 3 2 1 0 0001B 1 1 0 0 0 0 0 0 00C0 ...

Page 113: ...MUX reset values SYSBOOTMODE BOOTMODE9 SYSPINMUX BUFPUEN SYSPINMUX reset value 7 6 5 4 3 2 1 0 0 1 1 1 0 1 1 0 1 00ED 0000H 1 1 1 1 1 1 1 0 1 00FD 0000H System Controller Chapter 4 Preliminary User s Manual S19203EE1V3UM00 113 ...

Page 114: ...5 to 4 VISEL 1 0 Selects the data source of the Video Input 00B no data to Video Input 01B Video Input data source is external video input interface 10B loopback mode 0 Video Input data source is Video Output 0 11B loopback mode 1 Video Input data source is Video Output 1 0 VIEN Enables the Video Input 0 Video Input disabled 1 Video Input enabled Note that setting SYSVIEN VIEN 1 does not start cap...

Page 115: ...CK EN VO0 RAM EN CSYN CSEL 0 R R R R R R R R R W R W R W R W R W R W R W R W Writing to the read only bits is ignored reading returns undefined values Bit Bit name Function 7 VO1VSSEL Controls function of VO1VSYNC of Video Output 1 0 VO1VSYNC 1 VO1EN via VO1VSYNC 6 VO1LOCKEN Enables AHB HLOCK generation of Video Output 1 0 HLOCK generation disabled 1 HLOCK generation enabled 5 VO0RAMEN Enables the...

Page 116: ...utput 0 0 RAM palette disabled 1 RAM palette enabled 0 CSYNCSEL0 Controls generation of composite VO0CSYNC or separate VO0HSYNC VO0VSYNC synchronization signals of Video Output 0 0 VO0HSYNC VO0VSYNC 1 VO0CSYNC via VO0HSYNC Chapter 4 System Controller 116 Preliminary User s Manual S19203EE1V3UM00 ...

Page 117: ...12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AD WAIT ZEN R R R R R R R R R R R R R R R R W Writing to the read only bits is ignored reading returns undefined values Bit Bit name Function 0 ADWAITZEN Controls the System Watchdog function 0 System Watchdog disabled 1 System Watchdog enabled If the System Watchdog is enabled it observes the ADBus Host I F signal ADWAIT If ADWAIT is acti...

Page 118: ...owed Reading of SYSPROTECT returns an undefined value After any reset the write protection is enabled Access This register can be written in 32 bit units Address SysC_Base 2CH Initial Value none 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SYSPROTECT 31 16 W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SYSPROTECT 15 0 W Bit Bit name Function 31 to 0 SYSPROTECT 31 0 0000 00A5H must be written to SYSPRO...

Page 119: ... and the interrupt pin HINT Interrupts Following tables define the assignment of the Ravin M respectively Ravin L interrupts Table 5 2 Ravin M interrupt assignments Interrupt HOSTINTFLAG INTINn Group Number Name Cause A 0 AHB_UNDERRUN AHB overrun INTIN0 1 AHB_OVERRUN AHB underrun INTIN1 2 AHB_ERROR Host I F AHB error INTIN2 3 VO0MBEINT Video Output 0 master bus error INTIN3 4 VI0AHEINT Video Input...

Page 120: ...NT Video Output 1 next base address INTIN25 26 VO1VCPINT Video Output 1 vertical compare INTIN26 27 not used INTIN27 28 not used INTIN28 29 not used INTIN29 30 not used INTIN30 31 not used INTIN31 Table 5 3 Ravin L interrupt assignments Interrupt HOSTINTFLAG INTINn Group Number Name Cause A 0 AHB_UNDERRUN AHB overrun INTIN0 1 AHB_OVERRUN AHB underrun INTIN1 2 AHB_ERROR Host I F AHB error INTIN2 3 ...

Page 121: ...e INTIN18 19 not used INTIN19 20 not used INTIN20 21 DRWINT Drawing Engine common interrupt INTIN21 22 VO0INT Video Output 0 common interrupt INTIN22 23 not used INTIN23 24 not used INTIN24 25 not used INTIN25 26 not used INTIN26 27 not used INTIN27 28 not used INTIN28 29 not used INTIN29 30 not used INTIN30 31 not used INTIN31 Host CPU Interface Chapter 5 Preliminary User s Manual S19203EE1V3UM00...

Page 122: ...es The addresses provided by the Host CPU are decoded by an address decoder and mapped to 3 different areas Host I F register bus for accessing all Host I F controller internal registers APB single master bus with the Host I F as the only master of the APB AHB multi master bus with the Host I F as one of several masters of the AHB While the Host I F register bus and the APB are exclusively used fo...

Page 123: ...a 24 bit short offset addressing mode is provided in order to unload the LBus Additionally a burst transfer mode with automatic address incrementing functions minimizes the overhead of address transfers and offers maximum data transfer bandwidth The data width can be specified to be byte half word and word If enabled the signal HLBDRQ is generated if the LBus I F is ready to accept the next data t...

Page 124: ...eShortOffs The eeShort command defines the lower 12 bit of the entire address and initiates the data transfer Thus the short addressing mode allows fast access to a 4 KB data segment by the 2 byte eeShort command Since short addressing generates a 24 bit address the address range is limited to the first 16 MB of the entire 28 bit address range The data length can be defined within the eeShort comm...

Page 125: ...sfered The commands can have up to six byte length followed by a specified number of data bytes Five different commands are available to set the related data transfer modes Following table gives an overview of the commands Table 5 4 LBus I F commands overview Command Function Shortcut Size Name eeShortOffs 2 byte Short address offset Sets the upper 12 address bits for short addressing mode eeShort...

Page 126: ... a eeShort access Byte 2nd byte 1st byte Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Content SHADDOFF 11 4 SHADDOFF 3 0 1 1 0 0 Parameters bit 15 4 SHADDOFF 11 0 upper 12 bit of a short address eeShortOffs byte1 eeShortOffs byte2 command transfer Figure 5 3 eeShortOffs command flow Chapter 5 Host CPU Interface 126 Preliminary User s Manual S19203EE1V3UM00 ...

Page 127: ...ive bit 3 2 L 1 0 defines the data length i e the number of data bytes to transfer L 1 0 00B 1 data byte 8 bit data L 1 0 01B 2 data bytes 16 bit data L 1 0 10B 4 data bytes 32 bit data L 1 0 11B setting prohibited bit 15 4 LADD 11 0 lower 12 bit of the address eeShort byte1 eeShort byte2 command transfer word data transfer L 1 0 00B L 1 0 01B L 1 0 10B data byte1 data byte2 data byte3 data byte4 ...

Page 128: ...e data length i e the number of data bytes to transfer L 1 0 00B 1 data byte 8 bit data L 1 0 01B 2 data bytes 16 bit data L 1 0 10B 4 data bytes 32 bit data L 1 0 11B setting prohibited bit 31 4 ADD 27 0 28 bit address eeLong byte1 eeLong byte2 eeLong byte3 command transfer word data transfer L 1 0 00B L 1 0 01B L 1 0 10B eeLong byte4 data byte1 data byte2 data byte3 data byte4 eeLong byte1 eeLon...

Page 129: ...65535 Byte 2nd byte 1st byte Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Content ADD 11 4 ADD 3 0 1 1 RW 1 Byte 4th byte 3rd byte Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Content ADD 27 20 ADD 19 12 Byte 6th byte 5th byte Bit 47 46 45 44 43 42 41 40 30 29 28 4 3 2 1 0 Content BSTLEN 15 8 BSTLEN 7 0 Parameters bit1 RW defines the direction of the data transfer RW 0 write mode LBDIN 7 0 from Host CPU...

Page 130: ...ing the 6 byte eeBstCfg command by two eeNOP commands Thus the entire command transfer is extended to two words eeNOP byte1 eeNOP byte1 eeBstCfg byte1 eeBstCfg byte2 eeBstCfg byte3 word1 word2 command transfer data transfer word3 word n 4 2 eeBstCfg byte4 eeBstCfg byte5 eeBstCfg byte6 data byte1 data byte2 data byte3 data byte4 data byte n 3 data byte n 2 data byte n 1 data byte n time Figure 5 8 ...

Page 131: ...d in order to reset the LBus I F s command data flow mechanism Afterwards the Host CPU can restart to send new commands 3 The Host CPU initiates data read transfers but doesn t perform any further read The LBus I F keeps on waiting for further read from the Host CPU The Host CPU shall write one byte followed by a read in order to reset the LBus I F s command data flow mechanism Afterwards the Host...

Page 132: ...ed HOSTCONTROL DRQEN 1 the DMA byte counter can be cleared and restarted by setting HOSTCONTROL DRQEN 1 again By this the Host CPU can restarted the DMA transfer if the byte transfer sequence was interrupted for any reason DMA request status The status of the HLBDRQ signals is reflected in the bit HOSTSTATUS DREQ 5 2 4 3 LBus I F DMA operation cautions Following operating cautions must be regarded...

Page 133: ...e enable HADBEN 1 0 write strobe HADWR read strobe HADRD chip select HADCS wait HADWAIT 5 3 2 ADBus I F address offset function The external address bus HADA 20 0 allows to address a range of 2 MB In order to achieve access to the entire internal 28 bit address range iADDR 27 0 offset addressing is used via four n 0 to 3 9 bit base addresses BASEADDRn defined in the the HOSTADBASEn registers The b...

Page 134: ...R 8 0 base address Instead the offset 0 is used and the resulting address has iADDR 27 13 0 though HOSTBASE0 BASEADDR 8 0 may define an address 0 Thus define HOSTBASE0 BASEADDR 8 0 0 and do not change this setting 5 3 3 ADBus I F data access Data read write accesses on the ADBus I F can be performed as byte and halfword accesses The size is derived from the ADBus I F byte enable signals HADBEN 1 0...

Page 135: ...he next halfword address HADA 1 0 10B read access the word combining process is disrupted and the write accesses are treated as consecutive separate writes Both half words are separately forwarded to their destinations b Combined read access If a ADBus read is performed with HADBEN 1 0 00B and HADA 1 0 00B it is assumed to be the first half word of a word read Thus a word is acquired from the addr...

Page 136: ...efore the falling edge of the HADRD HADWR strobe The rising edge of the HADRD HADWR strobe sets HADWAIT again to low level The rising edge of the HADCS sets HADWAIT back to high level and completes the access cycle Depending on the access type and especially on the occupation of the internal AHB HADWAIT may be active for some longer time forcing the Host CPU to stretch the current access In the fo...

Page 137: ...4 1 2 3 4 Figure 5 9 ADBus principle read write timing 1 HADWAIT falling edge because of HADCS falling edge 2 HADWAIT rising edge after HADRD HADWR falling edge 3 HADWAIT falling edge after HADRD HADWR rising edge 4 HADWAIT rising edge because of HADCS rising edge Host CPU Interface Chapter 5 Preliminary User s Manual S19203EE1V3UM00 137 ...

Page 138: ...e write timing with wait 1 HADWAIT falling edge because of HADCS falling edge 2 HADWAIT rising edge after HADWR falling edge 3 HADWAIT falling edge after HADWR rising edge 4 delayed HADWAIT rising edge after HADWR falling edge and wait time 5 HADWAIT rising edge because of HADCS rising edge Chapter 5 Host CPU Interface 138 Preliminary User s Manual S19203EE1V3UM00 ...

Page 139: ...rs is specified by the L 1 0 parameters of the eeShort eeLong commands the data size of ADBus I F transfers is specified by the ADBus HADBEN 1 0 byte half word and the word combining function word Depending on the size of the data transferred via the Host I F addresses the internal address iADDR 27 0 is forcibly aligned to the correct address low byte transfer low byte alignment iADD0 0 high byte ...

Page 140: ...UN AHB_OVERRUN AHB_ERR INT15 INT16 INT17 INT18 INT31 INTEN0 INTEN1 INTEN2 INTEN15 INTEN16 INTEN17 INTEN18 INTEN31 Figure 5 12 Interrupt controller HOSTINTFLAG The interrupts are grouped in 2 categories Group A INT 15 0 An occurence of these interrupts are latched in the circuit of the HOSTINTFLAG register and the assigned interrupt flag HOSTINTFLAG INTINn is set to 1 For resetting the flag to 0 a ...

Page 141: ...he HOSTINTFLAG register the HOSTSTATUS register contains two status bits that reflect the status of each interrupt group HOSTSTATUS INTA 1 at least one of the group A interrupts is pending HOSTSTATUS INTB 1 at least one of the group B interrupts is pending HINT output The Host I F interrupt request signal HINT stays active as long as any HOSTINTSTAT INTSTAT 31 0 is 1 Following diagram gives an exa...

Page 142: ...Host I F is performed and completed before the data is available the AHB master underrun interrupt is activated and the interrupt flag HOSTINTFLAG INTIN0 is set If AHB master underrun INT0 is unmasked HOSTINTENAB INTEN0 1 the Host I F interrupt HINT is asserted Reason for an AHB master underrun is the Host CPU reads data too fast from the Host I F Beside demanding the Host CPU to guarantee suffici...

Page 143: ...us base address 0 register HOSTADBASE0 0000 0020H ADBus base address 1 register HOSTADBASE1 0000 0024H ADBus base address 2 register HOSTADBASE2 0000 0028H ADBus base address 3 register HOSTADBASE3 0000 002CH 32 bit access to 8 bit 16 bit registers All registers can be accessed with 32 bit access However writing to bits not specified for registers with less than 32 bit width is ignored and reading...

Page 144: ...on 7 CIFNRDY Host I F not ready 0 Host I F is in operation 1 Host I F and Ravin M in reset state 6 DREQ Status of HLBDRQ pin 0 HLBDRQ is active 1 HLBDRQ is inactive 5 INTA Group A interrupt status 0 no group A interrupt pending 1 group A interrupt pending INTA 1 indicates that at least one of the group A interrupts is pending 4 INTB Group B interrupt status 0 no group B interrupt pending 1 group B...

Page 145: ...ter is read 16 bit or 32 bit units the upper bits 15 to 8 respectively 31 to 8 return undefined values Address 0000 000CH Initial Value 0000 002BH This register is never modified 7 6 5 4 3 2 1 0 MAJORREV MINORREV R R Bit Bit name Function 7 to 4 MAJORREV Major revision number 3 to 0 MINORREV Minor revision number Host CPU Interface Chapter 5 Preliminary User s Manual S19203EE1V3UM00 145 ...

Page 146: ...ST AT16 R R R R R R R R R R R R R R R R 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 INTST AT15 INTST AT14 INTST AT13 INTST AT12 INTST AT11 INTST AT10 INTST AT9 INTST AT8 INTST AT7 INTST AT6 INTST AT5 INTST AT4 INTST AT3 INTST AT2 INTST AT1 INTST AT0 R R R R R R R R R R R R R R R R Bit Bit name Function 31 to 3 INTSTAT 31 3 Status of interrupt n 0 interrupt n not pending 1 interrupt n pending 2 INTSTAT2 ...

Page 147: ...2 21 20 19 18 17 16 INTEN 31 17 R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 INTEN 15 3 INT EN2 INT EN1 INT EN0 R W R W R W R W Bit Bit name Function 31 to 3 INTEN 31 3 Interrupt n control 0 interrupt n not disabled 1 interrupt n enabled 2 INTEN2 AHB_ERR interrupt control 0 AHB_ERR interrupt disabled 1 AHB_ERR interrupt enabled 1 INTEN1 AHB_OVERRUN interrupt control 0 AHB_OVERRUN interrupt disabled 1...

Page 148: ...lized by any reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 INTIN 31 17 R 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 INTIN 15 3 INT IN2 INT IN1 INT IN0 R W R W R W R W Writing to the read only bits is ignored Bit Bit name Function 31 to 17 INTIN 31 17 Status of interrupt n 0 interrupt n not asserted 1 interrupt n asserted Writing 1 clears the bit to 0 writing 0 has no effect 16 to 3 INTIN 16 3 S...

Page 149: ...s register is initialized by any reset 7 6 5 4 3 2 1 0 0 0 0 0 0 0 DRQDIR DRQEN R R R R R R R W R W Writing to the read only bits is ignored reading returns undefined values Bit Bit name Function 1 DRQDIR Selects the transfer direction for which the DMA request control is active 0 transmit direction data transfer to Host CPU 1 receive direction data transfer from Host CPU 0 DRQEN Enables the opera...

Page 150: ... HOSTADBASE3 0031H These registers are initialized by any reset 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 BASEADDR 8 0 0 0 0 WC R R R R W R R R R W Writing to the read only bits is ignored reading returns undefined values Caution The default value 000000000B of HOSTBASE0 BASEADDR 8 0 must not be changed Bit Bit name Function 12 to 4 BASEADDR 8 0 These bits define the address bits ADADD 27 19 whe...

Page 151: ...ss offsets to the base address VIn_Base The VIn_Base addresses of the Video Input I F is given in the following table Video Input I F VIn_Base address VI0 0000 1E00H Pin functions The availability of Video Input signals at external pins depend on the selected Ravin M pinout option Table 6 1 Video Input Ravin M pinout options Signal Ravin M pinout option 3 9 1 2 3 6a 7 9 RGB 6 6 6 ITU656 VI0R 5 0 I...

Page 152: ...8 internal 24 bit RGB 888 to framebuffer 16 bit RGB 565 adjustment of YUV input data brightness colour saturation contrast replacement of U and V component with predefined value up downscaling and cropping in x direction downscaling and cropping in y direction scalable dithering for reducing visible luminance steps due to 16 bit colour format built in 32 x 32 bit FIFO for burst transfer of RGB 565...

Page 153: ... brightness contrast and colour saturation If monochrome images are captured the colour can be changed by replacing U and V by predefined values RGB 888 conversion All further data video data processing is applied to 24 bit RGB 888 data i e YUV 4 4 4 and RGB 565 RGB 666 is converted to RGB 888 Scale and crop The RGB 888 video data is passed to a scaling and cropping unit that allows to resize the ...

Page 154: ...ta is input via VInR 5 0 VInG 5 0 VInB 5 0 YUV 4 2 2 VInCONTROL RGBEN 0 ITU R656 coform Video Input data format supported orders are Y0 U Y1 V VInCONTROL YUVSEL 1 U Y0 V Y1 VInCONTROL YUVSEL 0 frame line synchronization is achieved by the ITU R656 embedded synchronization bytes the data is input via ITU 7 0 The table below summarizes the VInCONTROL register settings for setting up a dedicated Vide...

Page 155: ...te wise via the ITU 7 0 signals in synchronization with the clock input VInCLK The edge of VInCLK to be used for sampling the video data ITU 7 0 can be selected VInCONTROL CLKPH 0 ITU 7 0 is sampled with the rising edge of VInCLK VInCONTROL CLKPH 1 ITU 7 0 is sampled with the falling edge of VInCLK 6 2 2 RGB data input Video data input The RGB video data is input via the VInR 5 0 VInG 5 0 VInB 5 0...

Page 156: ... bits in the Video Input status register VInSTATUS FIELD indicates the current field information VInSTATUS VSYNC indicates the current status of the internal VSYNC signal VInSTATUS HSYNC indicates the current status of the internal HSYNC signal 6 3 Video Capturing 6 3 1 Video capturing modes The Video Input module can capture interlaced as well as progressive scanned video data frames It distingui...

Page 157: ...roller Note If the Video Input module is disabled by SYSVIEN VIEN 0 all Video Input registers can be accessed but writing to the registers is ignored and reading returns undefined values Start of capturing Below describes the sequence of how to start up the capturing of video data 1 enable the Video Input module by SYSVIEN VIEN 1 2 define the Video Input data format and the synchronization method ...

Page 158: ...ls in progressive scan mode The 512 x 300 pixels area starting at x 90 and y 40 shall be captured and scaled to 600 x 225 pixels to be stored in the framebuffer 0 0 PXCNT VInSTARTY 40 VInSTARTX 90 VInSCALEDHEIGHT 225 Cropping Scaling Storing P0 P1 P2 P3 P559 P558 P0 P1 P2 P3 P559 P558 VInSCALING MX 6 0 4BH factor 75 64 VInSCALING MY 5 0 30H factor 48 64 VInSCALEDWIDTH 600 VInSTARTADDR2 VInSTARTADD...

Page 159: ...owing lines of the respective field are captured and passed on for further processing In case of progressive capturing VInSTARTY STARTY2 9 0 defines the first line to capture while VInSTARTY STARTY1 9 0 is not of concern Cropping of the image at the right and lower edge is done by the definition of the scaled width and height VInSCALEDWIDTH and VInSCALEDHEIGHT in the scaler unit Interlaced mode In...

Page 160: ... frame the y scaler is reset and the xin and y coordinates are set to address the first pixel of the first line Depending on the y scaling factor a decision is taken whether the current line produces an output If not only the luminance values Y for each pixel of that line are calculated which contribute later to the calculation of the output lines If a line is to generate an output the x scaler is...

Page 161: ... yes yes reset y scaler y 0 reset x scaler xin xin 1 xin xin 1 y y 1 y y 1 xin 0 yes new frame y scaler x scaler Figure 6 4 Video Input scaler unit 6 4 2 1 Y scaler The y scaler allows downscaling of a field The y scaling factor is determined by VInSCALING MY 5 0 and is calculated as y_scale VInSCALING MY 5 0 64 MY 5 0 must be less than 64 If MY 0 the y scaler is disabled Video Input Ravin M only ...

Page 162: ...in is handed over to the x scaler Note Pin xin and Pyout xin includes the three colour channels R G B frame end no yes yes y y 1 xin 0 yadd y_scale frame end no yes y y 1 new frame line end no no line output no yes ysum ysum yadd xin xin 1 read pixel Pin xin Y R 2G B Ylinebuf xin Ylinebuf xin Y yadd reset y scaler y_scale MY 64 ysum 0 Ylinebuf 1023 0 0 y 0 yadd ysum 1 line end line output no yes f...

Page 163: ...olour channels C i e is R or G or B xadd xsum 1 xremainder 1 xsum xadd xadd xremainder Cxout xout Cxout xout Cyout xin xremainder Cxout xout Cxout xout Cyout xin xadd xsum xsum xadd Cxout xout 0 xsum 0 xadd x_scale Pyout xin from y scaler next_pixel to y scaler output Cxout xout to position xout yes no no pixel output pixel output Pyout xin include the colour channels C with C R or G or B Figure 6...

Page 164: ...32 pixels VInSTRIDEX 0000 0260H is the correct setting 8 pixels 16 bytes are left unused The start address of the first captured pixel is set to VInSTARTADDR2 0010 0000H The entire captured field occupies the address range 0010 0000H to 001B 4800H 6 5 Colour Format Conversions 6 5 1 RGB 666 565 to RGB 888 conversion The RGB 888 converter generates 24 bit RGB 888 data out of either 16 bit RGB 565 o...

Page 165: ...able in the original YUV 4 2 2 signal from the ITU R656 source The U and V values are assigned to both of the YUV 4 2 2 two macro pixels YUV422 Y0U Y1V YUV444 Y0UV Y1UV The converter allows to convert two different component orders of the YUV 4 2 2 signal The correct order must be chosen with the VInCONTROL YUVSEL bit VInCONTROL YUVSEL 0 YUV422 Y0U Y1V VInCONTROL YUVSEL 1 YUV422 UY0 VY1 Before con...

Page 166: ...mum 235 and minimum 16 value Amplification mode In amplification mode VInADJUSTLEVEL ADJMODE 0 the colour saturation can be changed by amplifying the U and V values The amplification factors are set by VInADJUSTLEVEL AU 4 0 and VInADJUSTLEVEL AV 4 0 The output values Uout and Vout are calculated as follows Uout Uin 128 AU 4 0 16 128 Vout Vin 128 AV 4 0 16 128 Uout and Vout are clamped to their max...

Page 167: ...for red and blue The data manipulation of the dithering unit can be represented as follows R5 4 0 R8 7 0 RNG k 0 and 0xF8 3 G6 5 0 G8 7 0 RNG k 1 0 and 0xFC 2 B5 4 0 B8 7 0 RNG k 0 and 0xF8 3 6 8 Video Data FIFO and Framebuffer addressing This section describes the function of the video data FIFO and the way how the FIFO data is transferred to the memory 6 8 1 Video data FIFO The 32 x 32 bit FIFO ...

Page 168: ...er one or two framebuffers in the memory The framebuffer address the FIFO content is written to is defined by registers VInSTARTADDR1 base address of first field framebuffer denotes the address of the first pixel of the first field VInSTARTADDR2 base address of second field framebuffer denotes the address of the first pixel of the secondfield The framebuffer base address must be aligned to 8 pixel...

Page 169: ...s an undefined address range via the first field framebuffer start address register VInSTARTADDR1 second field framebuffer start address register VInSTARTADDR2 the bus error interrupt VInAHEINT is generated The bus error interrupt serves only for debug purpose VInFFOINT FIFO overflow interrupt The FIFO overflow interrupt VInFFOINT is generated if the FIFO is filled with data waiting for beeing tra...

Page 170: ...ACTSL 11 0 active unscaled scanline number The scanline interrupt VOnSCLINT is activated under following conditions First field scanline interrupt if VInACTSCANLINE ACTSL 11 0 VInSCANLINEINT SLINT 11 0 0 and VInSCANLINEINT FLD1EN 1 or VInSCANLINEINT FLD2EN 1 and VInACTSCANLINE AFLD 0 Second field scanline interrupt if VInACTSCANLINE ACTSL 11 0 VInSCANLINEINT SLINT 11 0 0 and VInSCANLINEINT FLD1EN ...

Page 171: ...DHEIGHT VIn_Base 14H Video Input control settings VInCONTROL VIn_Base 18H Scaling factors register VInSCALING VIn_Base 1CH Video Input status register VInSTATUS VIn_Base 20H Active scanline register VInACTSCANLINE VIn_Base 24H Scanline interrupt control register VInSCANLINEINT VIn_Base 28H CSYNC separator control register VInSYNCDECODE VIn_Base 2CH Scanlines offset register VInSTRIDEX VIn_Base 30H...

Page 172: ...e number of bits to be used for dithering 0000B dithering disabled 0001B one bit 0 used for dithering 0010B two bits 0 1 used for dithering 0100B three bits 0 2 used for dithering 1000B four bits 0 3 used for dithering 7 RGBSEL Selects RGB input format 0 input format is RGB 565 1 input format is RGB 666 6 YUVSEL Selects YUV 4 2 2 input format 0 input format is Y1 U Y2 V 1 input format is U Y1 V Y2...

Page 173: ...clock edge of VInCLK 1 RGBEN Selects Video Input data format 0 YUV format 1 RGB format 0 CAPEN Enable Video Input data capture 0 video capture disabled 1 video capture enabled starting with a new frame Video Input data is captured and processed Video Input Ravin M only Chapter 6 Preliminary User s Manual S19203EE1V3UM00 173 ...

Page 174: ...n 32 bit units Address VIn_Base 00H Initial Value 0000 0000H This register is initialized by any reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 START1 28 16 R R R R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 START1 15 4 0 0 0 0 R W R R R R Writing to the read only bits is ignored reading returns undefined values Bit Bit name Function 28 to 4 START1 28 4 Framebuffer start address for the ...

Page 175: ...2 bit units Address VIn_Base 04H Initial Value 0000 0000H This register is initialized by any reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 START2 28 16 R R R R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 START2 15 4 0 0 0 0 R W R R R R Writing to the read only bits is ignored reading returns undefined values Bit Bit name Function 28 to 4 START2 28 4 Framebuffer start address for the fir...

Page 176: ...Initial Value 0000 0000H This register is initialized by any reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 MY 5 0 0 0 0 0 0 0 0 0 0 R R W R R R R R R R R R 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 MX 6 0 0 0 0 0 0 0 0 0 R R W R R R R R R R R Writing to the read only bits is ignored reading returns undefined values Bit Bit name Function 30 to 25 MY 5 0 y scaler factor MY 5 0 0 y scaler dis...

Page 177: ...t 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 SCWIDTH 10 2 SCWIDTH 1 0 R R R R R R W R W Writing to the read only bits is ignored reading returns undefined values Bit Bit name Function 10 to 2 SCWIDTH 10 2 Scaled pixels per scanline 1 to 0 SCWIDTH 1 0 Lower address bits SCWIDTH 1 0 m...

Page 178: ...egister is initialized by any reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 SCHEIGHT 9 0 R R R R R R R W Writing to the read only bits is ignored reading returns undefined values Bit Bit name Function 9 to 0 SCHEIGHT 9 0 Scaled lines per field Chapter 6 Video Input Ravin M only...

Page 179: ...en and odd numbers Access This register can be read written in 32 bit units Address VIn_Base 08H Initial Value 0000 0000H This register is initialized by any reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 STARTX 9 0 R R R R R R R W Writing to the read only bits is ignored readin...

Page 180: ...efines the first line to capture whereas STARTY1 9 0 is disregarded Access This register can be read written in 32 bit units Address VIn_Base 0CH Initial Value 0000 0000H This register is initialized by any reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 STARTY2 9 0 R R R R R R R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 STARTY1 9 0 R R R R R R R W Writing to the read o...

Page 181: ...ue 0000 0000H This register is initialized by any reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 LSTRIDEX 12 0 R R R R W Writing to the read only bits is ignored reading returns undefined values Bit Bit name Function 12 to 0 LSTRIDEX 12 0 Line stride x in byte Video Input Ravin M only...

Page 182: ... 24 23 22 21 20 19 18 17 16 AVREP 7 0 AUREP 7 0 R W R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADJ MOD E 0 0 AY 4 0 OY 7 0 R W R R R W R W Writing to the read only bits is ignored reading returns undefined values Bit ADJMODE Bit name Function 28 to 24 0 AV 4 0 Amplification of V channel in amplification mode 31 to 24 1 AVREP 7 0 Replacement value for V channel in replacement mode 20 to 16 0 AU 4 0 ...

Page 183: ... any reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 34SCN 9 6 34SCN 5 0 R R R R R R R W R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 14SCN 9 6 14SCN 5 0 R R R R R R R W R W Writing to the read only bits is ignored reading returns undefined values Bit Bit name Function 25 to 16 34SCN 9 0 3 4 scanline Lower bits 34SCN 5 0 must be fixed to 0 due to 64 pixel alignment 9 to ...

Page 184: ...R R R Bit Bit name Function 13 to 8 FFUSEDW 5 0 Number of words in FIFO 7 VIIDLE Operation status of Video Input 0 capture operation active 1 idle 6 FIELD Current status of the internal field signal 0 first field 1 second field 5 VSYNC Current status of the internal VSYNC signal 0 not active 1 active 4 HSYNC Current status of the internal HSYNC signal 0 not active 1 active 1 START2PEND New address...

Page 185: ...R R R R R R R R R R 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 AFLD ACTSL 11 0 R R R R R Bit Bit name Function 12 AFLD Current status of the internal field signal 0 first field 1 second field 11 to 0 ACTSL 11 0 Current scanline number of the current field AFLD Note In progressive scan mode the scanline counter counts from 0 to field_height 1 In interlaced scan mode the scanline counter counts fro...

Page 186: ...anline interrupt for second field enabled 12 FLD1EN Enable scanline interrupt for first field 0 scanline interrupt for first field disabled 1 scanline interrupt for first field enabled 11 to 0 SLINT 11 0 Number of the unscaled scanline to generate the interrupt The scanline interrupt VInSCLINT is activated under following conditions First field scanline interrupt if VInACTSCANLINE ACTSL 11 0 VInSC...

Page 187: ...lue 0000 0100H This register is never modified 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MAJOR MINOR R R Bit Bit name Function 7 to 4 MAJOR Major revision number 3 to 0 MINOR Minor revision number Video Input Ravin M only Chapter 6 Preliminary User s Manual S19203EE1V3UM00 187 ...

Page 188: ...nce of a Video Output I F is identified by the index n n 0 1 for example VO0LCDTIMING0 for the VO0 LCD timing register 0 Register base addresses All VOn register addresses are given as address offsets to the individual base address VOn_Base The VOn_Base addresses of the Video Output I Fs are given in the following table VOn VOn_Base address VO0 0000 2000H VO1 0000 4000H 188 Preliminary User s Manu...

Page 189: ...O1R 5 2 VO1G0 VO1G 5 1 VO1B0 VO1B1 VO1B 5 2 VO1VSYNCb VO1HSYNCc VO1CLK b VOnVSYNC can also output VOnEN configurable in the System Controller c VOnHSYNC can also output VOnCSYNC configurable in the System Controller Ravin L pin functions The Ravin L provides only Video Output module 0 with following external signals VO0R 5 0 VO0G 5 0 VO0B 5 0 VO0HSYNC VO0VSYNC VO0EN VO0VSYNC can also output VO0EN ...

Page 190: ... colour look up table to external iRGB 1555 internal true colour 16 bpp RGB 565 to external RGB 565 internal true colour 24 bpp RGB 888 to external RGB 666 display geometry width and height programmable maximum resolution 1024 x 1024 pixels Below diagram shows the functional blocks of the Video Output module Sync and clock generator VOnR 5 0 VOnG 5 0 VOnB 5 0 VOnVSYNC VOnHSYNC VOnCLK VOnEN FIFO DM...

Page 191: ...lour Formats The Video Output module operates basically with two different colour formats true colour mode RGB colour data with 24 bpp or 16 bpp resolution is read from the framebuffer and output as 18 bpp RGB 666 or 16 bpp RGB 565 colours CLUT mode an 8 bpp colour index is read from the framebuffer and converted by the colour look up table to 16 bpp iRGB 1555 output colour The format is chosen by...

Page 192: ...nLCDPALETTE 127 0 Two entries can be written into the palette from a single word write access Note The intensity bit written to the CLUT can be constructed as an OR combination of the LSB of all colours i e I VOnR0 or VOnG0 or VOnB0 7 2 2 Display data output formats The display data output format is either 18 bpp RGB 666 or 16 bpp RGB 565 Depending on the colour mode some signals have different me...

Page 193: ...nR4 R4 R3 R3 VOnR3 R3 R2 R2 VOnR2 R2 R1 R1 VOnR1 R1 R0 R0 VOnR0 R0 undefined I 7 3 Timing Signals 7 3 1 Display data clock signal The data output clock i e the pixel clock VOnCLK is generated in the System Controller s clock generator The edge of VOnCLK used by the Video Output to output the pixel data can be selected VOnLCDTIMING2 IPC 0 data out with rising VOnCLK edge data stable at falling edge...

Page 194: ... also of VOnCSYNC synchronization signals are programmable via the registers VOnLCDTIMING0 and VOnLCDTIMING1 These registers allow also to define the output width and height The unit for the various values are pixel clocks for horizontal and lines for vertical synchronization timing Following timings are to be defined Table 7 5 Synchronization timing registers Register Function Range VOnLCDTIMING0...

Page 195: ...ideo data valid VOnEN IOE 1 Figure 7 3 VOnHSYNC timing setting VOnVSYNC The diagram below illustrates the line synchronization timing settings The active level of the VOnVSYNC signal can be defined as follows active level of VOnVSYNC VOnLCDTIMING2 IVS 0 VOnVSYNC is active high VOnLCDTIMING2 IVS 1 VOnVSYNC is active low The point in time to generate the vertical compare interrupt VOnVCPINT that ind...

Page 196: ...nLCDTIMING2 IHS VOnLCDTIMING2 IVS 1 VOnCSYNC active at low level if VOnLCDTIMING2 IVS VOnLCDTIMING2 IVS IHS thus VOnLCDTIMING2 IHS 0 and VOnLCDTIMING2 IVS 1 or VOnLCDTIMING2 IHS 1 and VOnLCDTIMING2 IVS 0 7 4 DMA FIFO and Framebuffer Addressing In order to sustain a high pixel data rate to the display the pixel data fetched from the memory is buffered by the DMA FIFO The FIFO is 32 words deep by 32...

Page 197: ...xt base address update interrupt VOnNBAINT is generated Note The VOnLCDUPCURR value may change at any moment and is not normally read It can be read to determine the approximate position within the framebuffer or for test purposes In case the frame to be output to the display shall be changed VOnLCDUPBASE must be rewritten Since a new VOnLCDUPBASE address becomes effective always with the start of...

Page 198: ...COMP 1 0 11B at start of the front porch You can clear the interrupt by writing VOnLCDICR VCOMPIC 1 VOnNBAINT Next address base update interrupt The LCD next base address update interrupt VOnNBAINT is generated when the framebuffer base address VOnLCDUPBASE LCDUPBASE 31 0 value has been made effective This signals to the system that it is safe to update the VOnLCDUPBASE register with new frame bas...

Page 199: ...DRIS reflects the occurence of any raw interrupt Any of the bits set here can generate a system interrupt provided it is enabled i e unmasked VOnLCDIMSC Any of the raw interrupts can be enabled unmasked respectively disabled masked by setting respectively resetting the corresponding bit in the LCD interrupt mask register VOnLCDIMSC The interrupt is enabled unmasked if its mask bit in VOnLCDIMSC is...

Page 200: ... setting VOnLCDTIMING0 6 define the vertical timing parameters by setting VOnLCDTIMING1 7 define the signal polarity of VOnEN VOnHSYNC VOnVSYNC the valid edge of VOnCLK the number of VOnCLK periods per line by setting VOnLCDTIMING2 8 unmask the interrupts to be used by setting VOnLCDIMSC 9 define the framebuffer address of the pixel data to be output by setting VOnLCDUPBASE 10 set VOnLCDCONTROL LC...

Page 201: ...ess register VOnLCDUPBASE VOn_Base 010H Control register VOnLCDCONTROL VOn_Base 018H Interrupt mask set clear register VOnLCDIMSC VOn_Base 01CH Raw interrupt status register VOnLCDRIS VOn_Base 020H Masked interrupt status register VOnLCDMIS VOn_Base 024H Interrupt clear register VOnLCDICR VOn_Base 028H Current address register VOnLCDUPCURR VOn_Base 02CH Colour palette registers VOnLCDPALETTE VOn_B...

Page 202: ...izontal back porch width HBP 7 0 specifies the number of VOnCLK periods between deassertion of VOnHSYNC and the start of active data The minimun value of HBP 7 0 is 2 The actual width of the back porch is HBP 7 0 1 TVOnCLK thus spans the range 3 to 256 TVOnCLK 23 to 16 HFP 7 0 Horizontal front porch width HFP 7 0 specifies the number of VOnCLK periods between the end of active data and assertion o...

Page 203: ... the number of inactive lines at the start of a frame after vertical synchronization period The actual vertical back porch width is VBP 7 0 TVOnHSYNC thus spans the range 0 to 255 lines 23 to 16 VFP 7 0 Vertical front porch width VFP 7 0 is the number of inactive lines at the end of frame before vertical synchronization period The actual vertical front porch width is VFP 7 0 TVOnHSYNC thus spans t...

Page 204: ... default value 0 of bit 31 to 27 and 10 to 0 must not be changed Bit Bit name Function 26 bit 26 The default value 0 of this bit must be changed to 1 after reset and must not be altered afterwards 25 to 16 CPL 9 0 Number of VOnCLK clocks per line CPL 9 0 specifies the number of VOnCLK clocks to the LCD display on each line This equals the number of pixels line as specified by VoOnLCDTiming0 PPL 5 ...

Page 205: ...s follows VOnCSYNC active at high level if VOnLCDTIMING2 IVS VOnLCDTIMING2 IVS IHS thus VOnLCDTIMING2 IHS VOnLCDTIMING2 IVS 0 or VOnLCDTIMING2 IHS VOnLCDTIMING2 IVS 1 VOnCSYNC active at low level if VOnLCDTIMING2 IVS VOnLCDTIMING2 IVS IHS thus VOnLCDTIMING2 IHS 0 and VOnLCDTIMING2 IVS 1 or VOnLCDTIMING2 IHS 1 and VOnLCDTIMING2 IVS 0 Video Output Chapter 7 Preliminary User s Manual S19203EE1V3UM00 ...

Page 206: ...t not be altered afterwards 2 The default value 0 of bit 10 to 9 7 to 6 and 4 must not be changed Bit Bit name Function 16 WATERMARK DMA FIFO watermark level WATERMARK defines the number of empty locations in the DMA FIFO to initiate new data read from the framebuffer 0 4 empty locations 1 8 empty locations 13 to 12 LCDVCOMP 1 0 Vertical compare interrupt control LCDVCOMP 1 0 defines the time to g...

Page 207: ... 565 true colour mode The colour format selection determines the colour format of the pixel data in the framebuffer as well as the format of the display data output 0 LCDEN Video Output control enable LCDEN 1 enables the Video Output control signals VOnHSYNC VOnVSYNC VOnCLK VOnEN 0 control and display data signals disabled output low level 1 control signals enabled active LCDEN 0 disables also the...

Page 208: ...this register make sure that the previous address is effectively in use and can be overwritten Therefore wait for the occurence of the VOnNBAINT before rewriting this register Access This register can be read written in 32 bit units Address VOn_Base 010H Initial Value 0000 0000H This register is initialized by any reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 LCDLPBASE 31 16 R W 15 14 13 1...

Page 209: ...n be read in 32 bit units Address VOn_Base 02CH Initial Value 0000 0000H This register is initialized by any reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 UPCURRADDR 31 16 R 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 UPCURRADDR 15 0 R Bit Bit name Function 31 to 0 UPCURRADDR 31 0 Approximate current pixel data address Note The VOnLCDUPCURR value may change at any moment and is not normally read...

Page 210: ... IS LNBU IS FUF IS 0 R R R R R R R R R R R R R R R R Bit Bit name Function 4 MBERRORIS AHB master bus error status MBERRORIS is set when the Video Output AHB master interface encounters a bus error response from the framebuffer 3 VCOMPIS Vertical compare VCOMPIS is set at the beginning of a new frame i e during the vertical synchronization period The exact time can be selected by VOnLCDCONTROL LCD...

Page 211: ...1 0 0 0 0 0 0 0 0 0 0 0 0 MBER ROR IM VCO MP IM LNBU IM FUF IM 0 R R R R R R R R R R R R W R W R W R W R Bits marked as read only must be written with 0 reading returns undefined values Bit Bit name Function 4 MBERRORIM AHB master error interrupt VOnBEINT enable 0 VOnBEINT disabled masked 1 VOnBEINT enabled unmasked 3 VCOMPIM Vertical compare interrupt VOnVCPINT enable 0 VOnVCPINT disabled masked ...

Page 212: ... 28 27 26 25 24 23 22 21 20 19 18 17 16 I B 4 0 G 4 0 R 4 0 R W R W R W R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 I B 4 0 G 4 0 R 4 0 R W R W R W R W Bit Bit name Function 31 I Intensity bit a 30 to 26 B 4 0 Blue palette data 25 to 21 G 4 0 Green palette data 20 to 16 R 4 0 Red palette data 15 I Intensity bit a 14 to 10 B 4 0 Blue palette data 9 to 5 G 4 0 Green palette data 4 to 0 R 4 0 Red palet...

Page 213: ... 0 0 0 0 0 0 0 0 0 0 0 0 W W W W W W W W W W W W W W W W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 MBER ROR IC VCO MP IC LNBU IC FUF IC 0 W W W W W W W W W W W W W W W W Reading this register returns an undefined value Bit Bit name Function 4 MBERRORIC Clear AHB master error sytem interrupt Clear is performed by writing 1 3 VCOMPIC Clear Vertical compare sytem interrupt Clear is ...

Page 214: ...30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 MBER ROR MIS VCO MP MIS LNBU MIS FUF MIS 0 R R R R R R R R R R R R R R R R Bit Bit name Function 4 MBERRORMIS AHB master error interrupt VOnBEINT status bit 0 VOnBEINT pending 1 VOnBEINT inactive 3 VCOMPMIS Vertical compare interru...

Page 215: ...registers m 1 to 2 denotes the band limiter number Register base addresses All Drawing Engine register addresses are given as address offsets to the base address DrwE_Base The DrwE_Base address of the Drawing Engine is given in the following table Drawing Engine DrwE_Base address DrwE 0000 1D00H Preliminary User s Manual S19203EE1V3UM00 215 ...

Page 216: ... Pixel selection FIFO 128 x 107 bit DRWINT APB AHB AHB master interface APB I F Blend unit Framebuffer cache 1024 x 9 bit Texture cache 64 x 32 bit Figure 8 1 Drawing Engine block diagram The Drawing Engine accesses the memory via its AHB master interface for for reading writing pixel data from to the framebuffer reading textures reading display lists via separate caches The control registers are ...

Page 217: ...cribe the whole object If a pixel is inside the object it is selected for rendering if it is outside it is discarded If it is on the edge an alpha value can be chosen proportional to the distance of the pixel to the nearest edge for antialiasing Every pixel that is selected for rendering can be textured The resulting aRGB quadruple can be modified by a general raster operation approach independent...

Page 218: ...g Memory read CPU Ravin Figure 8 3 Simplified rendering pipeline setup The Drawing Engine also supports the usage of display lists which makes it possible to decouple CPU and graphics controller efficiently and do rendering in parallel to other CPU activities Chapter 8 Drawing Engine 218 Preliminary User s Manual S19203EE1V3UM00 ...

Page 219: ...ing BitBLT features fill copy stretch BitBLT rotate and scale alpha blending bilinear filtering colour conversion subpixel exact placement 8 3 1 3 Vector drawing features The vector Drawing Engine uses a halfplane rendering approach Therefore it is easy to implement edge antialiasing and blurring without much overhead When combining some of the units not only linear primitives like lines or polygo...

Page 220: ... and ellipses all conic sections filled or with arbitrary width arcs of 0 360 soft edges alpha gradients render Attribute colour pattern texture Quadratic Bezier approximated by circle arcs arbitrary width round or truncated endpoints outlines blurring alpha gradients render attribute colour Texture mapping 2D array of pixels This array can be mapped implicit or explicit on all primitives provided...

Page 221: ... In case of the selected colour format is less than 32 bpp then the driver takes care for the correct alignment and copies 32 bit per clock This results in 2 4 times larger copy performance for 8 bpp and 16 bpp formats 8 3 3 3 Stretch BitBLT This is very similar to the normal copy operation As the copy is done as kind of texture mapping the full texture mapping feature set can be used The user can...

Page 222: ...le ratios 8 3 3 7 Colour conversion Colour conversion is necessary when using different texture formats than the framebuffer format For saving texture memory several formats are supported with less bpp than the framebuffer usually has The Drawing Engine internally always operates with 32 bpp aRGB 8888 For that all input data are converted into 32 bpp and finally are converted back into the framebu...

Page 223: ... 16 bpp RGB 565 The colour format uses 2 byte per pixel with 5 bit for red 5 bit for blue and 6 bit for green The blue colour is taken as the alpha channel during colour conversion The alpha can be substituted with any alpha during the colourization step in the Drawing Engine 16 bpp aRGB 4444 The colour format uses 2 byte per pixel with 4 bit for every channel 16 bpp aRGB 1555 The colour format us...

Page 224: ...ing colour conversion This alpha can be substituted with any alpha during the colourization step in the Drawing Engine 16 bpp aRGB 4444 The colour format uses 2 byte per pixel with 4 bit for every channel 32 bpp aRGB 8888 The colour format uses 4 byte per pixel with 8 bit for every channel Chapter 8 Drawing Engine 224 Preliminary User s Manual S19203EE1V3UM00 ...

Page 225: ... pixel is positioned There are six hardware limiters build into the Ravin Drawing Engine In the linear setup a limiter describes a half plane The intersection of all halfplanes is the object If three halfplanes are intersected a triangle is created Figure 8 4 Intersection of halfplanes The limiter output is clamped to an interval of 0 1 In limiter 1 and 2 it is possible to apply a band filter befo...

Page 226: ... to be calculated This is done by the CPU in the driver With this information the Drawing Engine scans the whole bounding box and calculates the decision value for every pixel incrementally A block diagram of the whole rasterization unit can be seen in figure Simplified rendering pipeline setup in the chapter Introduction clamp Limiter1 Limiter2 Limiter3 Limiter4 Limiter5 Limiter6 Bandfilter clamp...

Page 227: ...is is a more general form Lets look at a vector form with c n p c y b x a y x f b a n y x p If a point 0 p is on the line then n p c c n p y x f 0 0 0 If you rewrite the constant the equation looks like this n p p y x f n p c 0 0 The vector n is called the normal vector and it is perpendicular to the line The setup can be seen in the next image n O p 0 p 0 p p d Drawing Engine Chapter 8 Preliminar...

Page 228: ...in x direction and a step in y direction have to be calculated a p f n e p f n p e p e p f x x x 0 with 0 1 x e a p f n e p f n p e p e p f x x x 0 b p f n e p f n p e p e p f y y y 0 with 1 0 y e This means the new distance can be calculated from the old distance with the increments a and b A step in x direction changes the distance by a and a step in y direction changes the distance by b The dis...

Page 229: ...old mode Then all values above 0 are considered 1 This is used in case antialiasing is not desired e g for shared edges Note In the diagram below following abbreviations are used start DRWLnSTART xadd DRWLnXADD yadd DRWLnYADD x 0 y 0 xadd a yadd b start c value start output value x width x x 1 Value value xadd y height y y 1 start start yadd End Begin yes no yes Figure 8 9 Flowchart of linear limi...

Page 230: ...0 0 0 The limiter parameters would be x yadd y xadd x y y x start 0 0 In the normalized case normal vector is 2 2 y x x y n The distance between edge and origin is x y y x n p 0 0 0 2 2 y x The limiter parameters would be 2 2 2 2 2 2 0 0 y x x yadd y x y xadd y x x y y x start Normalization is only needed if antialiasing is used The driver contains a optimized inverse square root to speed up the n...

Page 231: ...by x f y x f y dy bx y x f f d dy cx by by ax f y d cx y b ax y x f In the quadratic case the increments dx dy depend on x and y and are not constant They can be calculated incrementally a c ax c x a x dx x dx x d 2 1 2 1 1 2 1 2 b d by d y b y dy y dy y d 2 1 2 1 1 2 1 2 At the Origin the increments are like this 1 0 c dx and 1 0 d dy With incrementing the value by dx dy for every step in x and y...

Page 232: ...lues above 0 are considered 1 This is used in case antialiasing is not desired Note In the below diagram followign abbreviations are used start1 DRWL1START start2 DRWL2START xadd1 DRWL1XADD xadd2 DRWL2XADD yadd1 DRWL1YADD yadd2 DRWL2YADD x 0 y 0 xadd1 c 1 xadd2 2a yadd1 d 1 yadd2 2b start1 f start2 xadd1 value1 start value2 start2 output value1 x width x x 1 value1 value1 xadd1 value2 value2 xadd2...

Page 233: ...equation 2 2 2 2 2 2 2 r t s ty sx y x y x f With the following assignments the circle equation can be calculated incrementally 2 2 2 2 2 1 1 r t s f t d s c b a This would mean for the limiters with the results calculated in section Mathematical background in this chapter 2 2 2 2 2 2 1 2 1 2 1 1 1 2 1 1 1 2 2 2 b yadd a xadd xadd start t d yadd s c xadd r t s f start Drawing Engine Chapter 8 Prel...

Page 234: ...ilter has a single filter parameter w Input value value w yes no value w 1 value output value Figure 8 14 Bandfilter 0 0 2 0 4 0 6 0 8 1 10 5 0 5 10 Input Output after clamp Figure 8 15 Bandfilter output after clamp with w 5 Chapter 8 Drawing Engine 234 Preliminary User s Manual S19203EE1V3UM00 ...

Page 235: ...clamping unit cuts the limiter output to the interval 0 1 Input value value 0 yes no value 0 output value value 1 no value 1 yes Figure 8 16 Clamping unit Drawing Engine Chapter 8 Preliminary User s Manual S19203EE1V3UM00 235 ...

Page 236: ...esents the intersection and the maximum mode the union of the two regions Input value1 Input value2 Value1 value2 yes no output value2 output value1 Figure 8 17 Combiner operated in minmum mode intersection Input value1 Input value2 Value1 value2 yes no output value2 output value1 Figure 8 18 Combiner operated in maximum mode union Chapter 8 Drawing Engine 236 Preliminary User s Manual S19203EE1V3...

Page 237: ...ne 8 5 8 1 Spanstore Consider the following case If the grey triangle has to be rendered half of the pixel processed by the rendering engine the dotted bounding box would not be drawn This can be optimized with the spanstore operation When spanstore is activated and a span start is detected the x position of the span start is detected In the next line the rendering starts with the stored x positio...

Page 238: ...ft empty corner would not be rasterized because of the spanabort optimization 8 5 8 2 Spanabort The second optimization assumes that the object that has to be drawn is convex This means there is only one span per scanline to be drawn A non convex object would be e g a triangle that is not filled and just consists of a thick border In case of a convex object the rasterization can be stopped in case...

Page 239: ...er optimizations In this case the spanstore delay is used 46 2 28 2 37 85 6 42 2 45 98 3 96 6 79 5 0 10 20 30 40 50 60 70 80 90 100 Triangle A Triangle B Triangle C enumeration coverage Box Box span abort Box span abort span store Figure 8 23 Efficiency of spanstore and spanabort optimizations enumeration coverage pixels of primitive pixels of bounding box Drawing Engine Chapter 8 Preliminary User...

Page 240: ...g in g A g out b B b A b in b A b Figure 8 24 Colourization step interpolation between the two colour registers A DRWCOLOR1 and B DRWCOLOR2 This general approach can be used to several different colour modes These modes can be applied to any colour or alpha channel of the input individually Operation Settings for A and B copy A 0 B 0xff replace with a constant value v A v B v multiply with a const...

Page 241: ...3 points in object space x y to 3 points in texture space u v Let there be the following mapping h v u p y x p w v u p y x p v u p y x p 0 0 0 0 2 2 2 2 2 2 1 1 1 1 1 1 0 0 0 0 0 0 While w is the width of the texture and h is the height of the texture Examine the following picture in object space To simplify calculations the difference vectors are taken for calculations 0 2 2 0 1 1 p p d p p d Thi...

Page 242: ... mapping object space transformation from coordinate system O to O to simplify calculations O u v w h Figure 8 27 Texture mapping texture space texture with width w and height h Chapter 8 Drawing Engine 242 Preliminary User s Manual S19203EE1V3UM00 ...

Page 243: ... 1 dy dx dy dx A then the equation system can be rewritten as 12 11 12 11 0 0 m m A w m m A w This can be easily solved with determinants Let 1 2 2 1 1 det 1 dy dx dy dx A c Then the resulting constants are dy dv dx h c m dx dv dx h c m dy du dx w c m dx du dy w c m 2 22 1 21 2 12 2 11 To calculate the start values for u and v at the top of the bounding box the transformation into O from O has to ...

Page 244: ...WLVXADDI floor dv dx DRWTEXPITCH This is the integer part of dv dx DRWLVYADD floor dv dy DRWTEXPITCH This is the integer part of dv dy DRWLVYXADDF dv dy floor dv dy DRWTEXPITCH dv dx floor dv dx DRWTEXPITCH This is the fractional part of dv dy and dv dx combined in one register DRWTEXMASK Contains a mask for u and v separately to wraparound values of u and v This is useful for staying inside the l...

Page 245: ...ONE SRC_ALPHA SRC_ONE_MINUS_ALPHA DST_ZERO DST_ONE DST_ALPHA DST_ONE_MINUS_ALPHA The selection of the blend modes is done with the following flags BSF blend source factor is alpha BSI blend source factor invert BDF blend destination factor is alpha BDI blend destination factor invert The formula for the blending is D S f dst f src dst 1 0 0 S f BSI BSF α S f BSI BSF 0 1 0 1 0 S f BSI BSF α 1 0 1 S...

Page 246: ...C_ZERO DST_ONE_MINUS_ALPHA 0 1 1 1 DST 1 ALPHA SRC_ALPHA DST_ONE 1 0 0 0 SRC ALPHA DST SRC_ALPHA 1 0 0 1 SRC ALPHA SRC_ALPHA DST_ALPHA 1 0 1 0 SRC ALPHA DST ALPHA SRC_ALPHA DST_ONE_MINUS_ALPHA 1 0 1 1 SRC ALPHA DST 1 ALPHA SRC_ONE_MINUS_ALPHA DST_ONE 1 1 0 0 SRC 1 ALPHA DST SRC_ONE_MINUS_ALPHA 1 1 0 1 SRC 1 ALPHA SRC_ONE_MINUS_ALPHA DST_ALPHA 1 1 1 0 SRC 1 ALPHA DST ALPHA SRC_ONE_MINUS_ALPHA DST_O...

Page 247: ...ed Therefore make sure that DRWSTATUS DLISTACTIVE 0 displaylist reader is idle DRWSTATUS BUSENUM 0 enumeration unit is idle before starting a new register setup Finally write the framebuffer start address to the DRWORIGIN register The write also triggers the Drawing Engine to start rendering 8 6 2 Display list based mode In display list mode the Display list reader reads a memory block containing ...

Page 248: ...egister 1AH 26 which is DRWCOLOR2 write 00010000H to register 20H 32 which is DRWORIGIN Address word indices Beside referencing a register the indices of an address word can also have other meanings depending on its value Table 8 1 Address indices function Index Function 00H to 7FH register indices Two register indices trigger additional actions 20H 32 A write to DRWORIGIN to set a new framebuffer...

Page 249: ...ance index1 80H index3 index4 Thus always fill all indices after 80H also with the gap index 2 If any of the special indices 80H and FFH are used no register index may follow after them in the same address word Drawing Engine Chapter 8 Preliminary User s Manual S19203EE1V3UM00 249 ...

Page 250: ...t processing has been stopped because a new display list start has been triggered by writing to the display list start address register DRWDLISTSTART 8 7 2 Interrupt control The three Drawing Engine interrupts are combined to the single common interrupt DRWINT towards the external Host CPU Each interrupt can be masked disabled respectively unmasked enabled by setting its enable bit in the interrup...

Page 251: ...RWINT mask DRWIRQCTL BUSIRQEM DLISTIRQEM ENUMIRQEM hold clear or DRWSTATUS BUSIRQCLR BUSIRQ DLISTIRQCLR DLISTIRQ ENUMIRQCLR ENUMIRQ Figure 8 30 Interrupt controller Drawing Engine Chapter 8 Preliminary User s Manual S19203EE1V3UM00 251 ...

Page 252: ... can be chosen from below list Table 8 2 Performance counter trigger events DRWPERFTRIGGER PERFTRIGGERk Event 0 disable performance counter 1 Drawing Engine active cycles 2 framebuffer read access 3 framebuffer write access 4 texture read access 5 invisible pixels enumerated but selected with alpha 0 6 invisible pixels while internal FIFO is empty lost cycles 7 display list reader active cycles 8 ...

Page 253: ... 25 Secondary colour register DRWCOLOR2 DrwE_Base 68H 26 Pattern register DRWPATTERN DrwE_Base 74H 29 Limiter registers Limiter 1 start value DRWL1START DrwE_Base 10H 4 Limiter 2 start value DRWL2START DrwE_Base 14H 5 Limiter 3 start value DRWL3START DrwE_Base 18H 6 Limiter 4 start value DRWL4START DrwE_Base 1CH 7 Limiter 5 start value DRWL5START DrwE_Base 20H 8 Limiter 6 start value DRWL6START Dr...

Page 254: ...part DRWLVYADDI DrwE_Base A8H 42 V limiter increment fractional parts DRWLVYXADDF DrwE_Base ACH 43 Colour lookup table for the indexed texture format DRWTEXCLUT DrwE_Base D8H n a b Miscellaneous registers Bounding box dimension DRWSIZE DrwE_Base 78H 30 Framebuffer pitch and spanstore delay DRWPITCH DrwE_Base 7CH 31 Address of the first pixel in framebuffer DRWORIGIN DrwE_Base 80H 32 Display list s...

Page 255: ... ENABLE LIM6 THRESH OLD LIM5 THRESH OLD LIM4 THRESH OLD LIM3 THRESH OLD LIM2 THRESH OLD LIM1 THRESH OLD QUAD3 ENABLE W W W W W W W W 7 6 5 4 3 2 1 0 QUAD2 ENABLE QUAD1 ENABLE LIM6 ENABLE LIM5 ENABLE LIM4 ENABLE LIM3 ENABLE LIM2 ENABLE LIM1 ENABLE W W W W W W W W Wrting to bits marked with 0 is ignored Bit Bit name Function 23 SPANSTORE Nextline span start is always equal or left to current line sp...

Page 256: ...old mode 0 disabled 1 enabled 13 LIM5 THRESHOLD Enable limiter 5 threshold mode 0 disabled 1 enabled 12 LIM4 THRESHOLD Enable limiter 4 threshold mode 0 disabled 1 enabled 11 LIM3 THRESHOLD Enable limiter 3 threshold mode 0 disabled 1 enabled 10 LIM2 THRESHOLD Enable limiter 2 threshold mode 0 disabled 1 enabled 9 LIM1 THRESHOLD Enable limiter 1 threshold mode 0 disabled 1 enabled 8 QUAD3ENABLE En...

Page 257: ...limiter 5 0 disabled 1 enabled 3 LIM4ENABLE Enable limiter 4 0 disabled 1 enabled 2 LIM3ENABLE Enable limiter 3 0 disabled 1 enabled 1 LIM2ENABLE Enable limiter 2 0 disabled 1 enabled 0 LIM1ENABLE Enable limiter 1 0 disabled 1 enabled Drawing Engine Chapter 8 Preliminary User s Manual S19203EE1V3UM00 257 ...

Page 258: ... TEXTURE CLAMPY TEXTURE CLAMPX BC2 BDI BSI BDF BSF 0 W W W W W W W W 7 6 5 4 3 2 1 0 0 0 0 READ FORMAT 3 0 PATTERN SOURCE L5 TEXTURE ENABLE PATTERN ENABLE W W W W W W W W Wrting to bits marked with 0 is ignored Bit Bit name Function 23 to 22 WRITEALPHA Set the alpha source for the framebuffer 00B use alpha from colour 2 01B use source alpha pixel coverage 00B use 0 0 as alpha 11B use alpha from fr...

Page 259: ...ied through BDF 1 invert destination blend factor 1 x 11 BSI src factor will be inverted meaning 1 a or 1 1 depending on BSF 0 use blend factor as specified through BSF 1 invert source blend factor 1 x 10 BDF dst factor is alpha factor is 1 per default 0 use 1 0 as destination blend factor 1 use alpha as destination blend factor 9 BSF rc factor is alpha factor is 1 per default 0 use 1 0 as source ...

Page 260: ...NUMIRQ CLR DLISTIRQ EN ENUMIRQ EN W W W W W W W W Wrting to bits marked with 0 is ignored Bit Bit name Function 5 BUSIRQCLR Clear bus error interrupt BUSIRQ 0 no BUSIRQCLR clear 1 clear BUSIRQCLR After writing 1 this bit returns to 0 automatically 4 BUSIRQEN BUSIRQ interrupt mask enable 0 disable mask BUSIRQ 1 enable unmask BUSIRQ 3 DLISTIRQCLR Clear display list interrupt DLISTIRQ 0 no BUSIRQCLR ...

Page 261: ...LISTIRQ interrupt mask enable 0 disable mask DLISTIRQ 1 enable unmask DLISTIRQ 0 ENUMIRQEN ENUMIRQ interrupt mask enable 0 disable mask ENUMIRQ 1 enable unmask ENUMIRQ Drawing Engine Chapter 8 Preliminary User s Manual S19203EE1V3UM00 261 ...

Page 262: ... W W W W W W W 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 W W W W W W W W 7 6 5 4 3 2 1 0 0 0 0 0 CFLUSHT X CENABLE TX CFLUSHF B CENABLE FB W W W W W W W W Wrting to bits marked with 0 is ignored Bit Bit name Function 3 CFLUSHTX Flush texture cache 0 do not flush the texture cache 1 flush the texture cache 2 CENABLETX Texture cache enable 0 disable the texture cache 1 enable the texture cache 1 CFLUSHF...

Page 263: ...e Function 6 BUSIRQ 0 no bus error occurred or interrupt disabled 1 bus error interrupt triggered 5 DLISTIRQ 0 display list not finished or interrupt disabled 1 display list finished interrupt triggered 4 ENUMIRQ 0 enumeration not finished or interrupt disabled 1 enumeration finished interrupt triggered 3 DLISTACTIVE 0 display list reader is idle 1 display list reader busy no direct access to regi...

Page 264: ... TX CACHE FB CACHE DLR 0 R R R R R R R R 15 14 13 12 11 10 9 8 0 0 0 1 Revisionnumber R R R R R 7 6 5 4 3 2 1 0 Revisionnumber R Bit Bit name Function 20 PERFCOUNT Performance counter 0 no performance counter 1 two performance counters available 19 TXCACHE Texture cache 0 no texture cache 1 texture cache available 18 FBCACHE Framebuffer cache 0 no framebuffer cache 1 framebuffer cache available 17...

Page 265: ...ter is initialized by any reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 COLOR1A 7 0 COLOR1R 7 0 W W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 COLOR1G 7 0 COLOR1B 7 0 W W Bit Bit name Function 31 to 24 COLOR1A 7 0 Alpha channel of colour 1 00H transparent FFH opaque 23 to 16 COLOR1R 7 0 Red channel of colour 1 15 to 8 COLOR1G 7 0 Green channel of colour 1 7 to 0 COLOR1B 7 0 Blue channel of colo...

Page 266: ...Index 26 Initial Value 0000 0000H This register is initialized by any reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 COLOR2A 7 0 COLOR2R 7 0 W W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 COLOR2G 7 0 COLOR2B 7 0 W W Bit Bit name Function 31 to 24 COLOR2A 7 0 Alpha channel of colour 2 00H transparent FFH opaque 23 to 16 COLOR2R 7 0 Red channel of colour 2 15 to 8 COLOR2G 7 0 Green channel of colo...

Page 267: ...29 Initial Value 0000 0000H This register is initialized by any reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W W W W W W W W W W W W W W W W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 PATTERN 7 0 W W W W W W W W W Writing to bits marked with 0 is ignored Bit Bit name Function 7 to 0 PATTERN 7 0 Bitmap of the pattern Drawing Engine Chapter 8 Preli...

Page 268: ...rwE_Base 18H DRWL4START DrwE_Base 1CH DRWL5START DrwE_Base 20H DRWL6START DrwE_Base 24H Index DRWL1START 4 DRWL2START 5 DRWL3START 6 DRWL4START 7 DRWL5START 8 DRWL6START 9 Initial Value 0000 0000H This register is initialized by any reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 LnSTART 31 16 W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LnSTART 15 0 W Bit Bit name Function 31 to 0 LnSTART 31 0 S...

Page 269: ...WL3XADD DrwE_Base 30H DRWL4XADD DrwE_Base 34H DRWL5XADD DrwE_Base 38H DRWL6XADD DrwE_Base 3CH Index DRWL1XADD 10 DRWL2XADD 11 DRWL3XADD 12 DRWL4XADD 13 DRWL5XADD 14 DRWL6XADD 15 Initial Value 0000 0000H This register is initialized by any reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 LnXADD 31 16 W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LnXADD 15 0 W Bit Bit name Function 31 to 0 LnXADD 31 ...

Page 270: ...WL3YADD DrwE_Base 48H DRWL4YADD DrwE_Base 4CH DRWL5YADD DrwE_Base 50H DRWL6YADD DrwE_Base 54H Index DRWL1YADD 16 DRWL2YADD 17 DRWL3YADD 18 DRWL4YADD 19 DRWL5YADD 20 DRWL6YADD 21 Initial Value 0000 0000H This register is initialized by any reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 LnYADD 31 16 W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LnYADD 15 0 W Bit Bit name Function 31 to 0 LnYADD 31 ...

Page 271: ...he 16 16 fixed point inner width of band region Note m 1 to 2 Access This register can be written in 32 bit units Address DRWL1BAND DrwE_Base 58H DRWL2BAND DrwE_Base 5CH Index DRWL1BAND 22 DRWL2BAND 23 Initial Value 0000 0000H This register is initialized by any reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 LmBAND 31 16 W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LmBAND 15 0 W Bit Bit name Fun...

Page 272: ...ess This register can be written in 32 bit units Address DrwE_Base BCH Index 47 Initial Value 0000 0000H This register is initialized by any reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TEXORIGIN 31 16 W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TEXORIGIN 15 0 W Bit Bit name Function 31 to 0 TEXORIGIN 31 0 Texture base address Chapter 8 Drawing Engine 272 Preliminary User s Manual S19203EE1V3...

Page 273: ... DrwE_Base B4H Index 45 Initial Value 0000 0000H This register is initialized by any reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TEXPITCH 31 16 W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TEXPITCH 15 0 W Bit Bit name Function 31 to 0 TEXPITCH 31 0 Texels per texture line Drawing Engine Chapter 8 Preliminary User s Manual S19203EE1V3UM00 273 ...

Page 274: ...nits Address DrwE_Base B8H Index 46 Initial Value 0000 0000H This register is initialized by any reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TEXUMASK 20 5 W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TEXUMASK 4 0 TEXVMASK 10 0 W W Bit Bit name Function 31 to 11 TEXUMASK 20 0 V mask 10 to 0 TEXVMASK 10 0 U mask Chapter 8 Drawing Engine 274 Preliminary User s Manual S19203EE1V3UM00 ...

Page 275: ...n in 32 bit units Address DrwE_Base 90H Index 36 Initial Value 0000 0000H This register is initialized by any reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 LUSTART 31 16 W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LUSTART 15 0 W Bit Bit name Function 31 to 0 LUSTART 31 0 U limiter start value Drawing Engine Chapter 8 Preliminary User s Manual S19203EE1V3UM00 275 ...

Page 276: ...r can be written in 32 bit units Address DrwE_Base 94H Index 37 Initial Value 0000 0000H This register is initialized by any reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 LUXADD 31 16 W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LUXADD 15 0 W Bit Bit name Function 31 to 0 LUXADD 31 0 U limiter x axis increment Chapter 8 Drawing Engine 276 Preliminary User s Manual S19203EE1V3UM00 ...

Page 277: ... can be written in 32 bit units Address DrwE_Base 98H Index 38 Initial Value 0000 0000H This register is initialized by any reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 LUYADD 31 16 W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LUYADD 15 0 W Bit Bit name Function 31 to 0 LUYADD 31 0 U limiter y axis increment Drawing Engine Chapter 8 Preliminary User s Manual S19203EE1V3UM00 277 ...

Page 278: ... written in 32 bit units Address DrwE_Base 9CH Index 39 Initial Value 0000 0000H This register is initialized by any reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 LVSTARTI 31 16 W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LVSTARTI 15 0 W Bit Bit name Function 31 to 0 LVSTARTI 31 0 V limiter start value integer part Chapter 8 Drawing Engine 278 Preliminary User s Manual S19203EE1V3UM00 ...

Page 279: ...0H Index 40 Initial Value 0000 0000H This register is initialized by any reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W W W W W W W W W W W W W W W W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LVSTARTF 15 0 W Writing to bits marked with 0 is ignored Bit Bit name Function 31 to 0 LVSTARTF 15 0 V limiter start value fractional part Drawing Engine Chapter 8 Prelimi...

Page 280: ... can be written in 32 bit units Address DrwE_Base A4H Index 41 Initial Value 0000 0000H This register is initialized by any reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 LVXADDI 31 16 W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LVXADDI 15 0 W Bit Bit name Function 31 to 0 LVXADDI 31 0 V limiter x axis increment integer part Chapter 8 Drawing Engine 280 Preliminary User s Manual S19203EE1V3UM00...

Page 281: ...r can be written in 32 bit units Address DrwE_Base A8H Index 42 Initial Value 0000 0000H This register is initialized by any reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 LVYADDI 31 16 W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LVYADDI 15 0 W Bit Bit name Function 31 to 0 LVYADDI 31 0 V limiter y axis increment integer part Drawing Engine Chapter 8 Preliminary User s Manual S19203EE1V3UM00 28...

Page 282: ... ACH Index 43 Initial Value 0000 0000H This register is initialized by any reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 LVYADDF 15 0 W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LVXADDF 15 0 W Bit Bit name Function 31 to 16 LVYADDF 15 0 V y limiter increment fractional part 15 to 0 LVXADDF 15 0 V x limiter increment fractional part Chapter 8 Drawing Engine 282 Preliminary User s Manual S19203E...

Page 283: ...n via display list commands Initial Value 0000 0000H This register is initialized by any reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CLUTINDEX 7 0 CLUTENTRY 23 16 W W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CLUTENTRY 15 0 W Bit Bit name Function 31 to 24 CLUTINDEX 7 0 Index of CLUT entry to write 23 to 0 CLUTENTRY 23 0 RGB 888 CLUT entry Drawing Engine Chapter 8 Preliminary User s Manual S...

Page 284: ...bit units Address DrwE_Base 78H Index 30 Initial Value 0000 0000H This register is initialized by any reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SIZEY W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SIZEX W Bit Bit name Function 31 to 16 SIZEY Height of the bounding box in pixels 15 to 0 SIZEX Width of the bounding box in pixels Chapter 8 Drawing Engine 284 Preliminary User s Manual S19203EE1V3...

Page 285: ...s register is initialized by any reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SSD W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PITCH W Bit Bit name Function 31 to 16 SSD Spanstore delay 15 to 0 PITCH Pitch of the framebuffer A negative width can be used to render bottom up instead of top down Drawing Engine Chapter 8 Preliminary User s Manual S19203EE1V3UM00 285 ...

Page 286: ...32 bit units Address DrwE_Base 80H Index 32 Initial Value 0000 0000H This register is initialized by any reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ORIGIN W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ORIGIN W Bit Bit name Function 31 to 0 ORIGIN Address of the first pixel in framebuffer Chapter 8 Drawing Engine 286 Preliminary User s Manual S19203EE1V3UM00 ...

Page 287: ...inates Access This register can be written in 32 bit units Address DrwE_Base C8H Index 50 Initial Value 0000 0000H This register is initialized by any reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DLISTSTART W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DLISTSTART W Bit Bit name Function 31 to 0 DLISTSTART Display list start address Drawing Engine Chapter 8 Preliminary User s Manual S19203EE1V3U...

Page 288: ...ERFTRIGGER 2 Selects the internal event that will increment DRWPERFCOUNT2 register 0 disable performance counter 1 Drawing Engine active cycles 2 framebuffer read access 3 framebuffer write access 4 texture read access 5 invisible pixels enumerated but selected with alpha 0 6 invisible pixels while internal FIFO is empty lost cycles 7 display list reader active cycles 8 framebuffer read hits 9 fra...

Page 289: ...WPERFCOUNT1 DrwE_Base CCH DRWPERFCOUNT2 DrwE_Base D0H Index DRWPERFCOUNT1 51 DRWPERFCOUNT2 52 Initial Value 0000 0000H This register is initialized by any reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PERFCOUNTk 31 16 R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PERFCOUNTk 15 0 R W Bit Bit name Function 31 to 0 PERFCOUNTk 31 0 Counter k value Drawing Engine Chapter 8 Preliminary User s Manual...

Page 290: ... MemC_Base address of the Memory Controller is given in the following table Memory Controller MemC_Base address MemC 0000 3000H Ravin M pin functions The availability of external memory interface signals at external pins depend on the selected Ravin M pinout option Table 9 1 Ravin M external memory I F pinout options Bus Signal Ravin M option 1 9 2 7e 3 6 7a 7b 7c 7d Shared MA 12 0 MA 15 13 MA 23 ...

Page 291: ...sabled at system start up Default configuration Upon system start up the external memory interface is configured as follows MCS0 16 MB SDRAM 32 bit data bus width base and alias address 0000 0000H 8 bit column address 11 bit row address 4 banks 7 clocks after self refresh exit 7 clocks active to active command 7 clocks after auto refresh 1 clock from last data to next precharge 3 clocks precharge ...

Page 292: ...cles 4 clocks bus idle time 4 clocks Caution As the Ravin L supports only a 16 bit external memory data bus the data bus width has to be changed by setting MEMSCONR DDWIDTH 1 0 00B MEMSCONR SDWIDTH2 1 0 00B after reset if the external memory interface is used Chapter 9 External Memory Interface Controller 292 Preliminary User s Manual S19203EE1V3UM00 ...

Page 293: ... bank select addresses data width 16 bit 32 bit up to 128 MB SDRAM Static memory interface data width 8 bit 16 bit 32 bit up to 128 MB per chips select separate timings parameters and bus widths for each static memory chip select SDRAM static memory parameters configurable via registers Feedback clock MDFBCLK for data read accesses to compensate PCB propagation times To support refresh of SDRAM ev...

Page 294: ...s of the memory bus signals on the off chip PCB the data MD 31 0 signals are sampled with the SDRAM feed back clock MDFBCLK instead of MDCLK for data read accesses Sampling of the read data signals MD 31 0 with MDFBCLK applies only if data is read from the external SDRAM i e SDRAM is enabled by SDRAMEN 1 SRAM chip select is not active i e MCS1 1 In case of SRAM or flash the read data is registered...

Page 295: ...ssued 3 Auto refresh commands are issued depending on the value MEMSTMG1R INITREF 4 The mode registers of the SDRAM devices are written The Memory Controller performs a power on sequence of the SDRAM under these circumstances immediately after reset when initialization is commenced by setting MEMSCTRL INIT 1 If the initialization sequence is completed MEMSCTRL INIT is automatically reset to 0 Exte...

Page 296: ...ation The Memory Controller automatically sets the SDRAM devices mode registers during the power up initialization If the SDRAM mode registers shall be rewritten during normal operation set MEMSCTRL SDRMODE 1 After the Memory Controller finishes the SDRAM devices mode register setting it clears MEMSCTRL SDRMODE to 0 Following parameters are written to the SDRAM devices mode register Chapter 9 Exte...

Page 297: ...operations has to be defined by MEMSREFR TREF 15 0 register value MEMSREFR TREF is the value of a free running counter that the refresh logic in the Memory Controller operates on When the count expires the refresh logic gives a refresh request to the SDRAM control Caution In order to ensure reliable data storage in the SDRAM devices the refresh period parameter MEMSREFR TREF 15 0 in the SDRAM refr...

Page 298: ...ulates the minimum frequency in MHz fHCLK MHz num_of_rows 1280 Following table gives some values for the minimum system clock frequency fHCLK for different number of rows to refresh for a maximum burst length of max_burst_clocks 50 fHCLK periods and a typical SDRAM_refresh_period of 64 ms fHCLK is rounded up The possible MEMSREFR TREF settings are also given based on the rounded up fHCLK Note that...

Page 299: ...Ready for new command NOP NOP Auto refresh MEMSTMG0R TRCAR Figure 9 4 SDRAM auto refresh command sequence External Memory Interface Controller Chapter 9 Preliminary User s Manual S19203EE1V3UM00 299 ...

Page 300: ...OP NOP Auto refresh single FSREFA 0 or all FSREFA 1 rows Auto refresh single FSREFB 0 or all FSREFB 1 rows MEMSTMG0R TXSR MEMSTMG0R TRASMIN Figure 9 5 Self refresh command sequence You can force the Memory Controller to enter self refresh mode by setting MEMSCTRL SREF 1 The Memory Controller forces the SDRAM to come out of self refresh mode when setting MEMSCTRL SREF 0 The control bits FSREFB and ...

Page 301: ...RL SREFSTAT 1 before disabling the Memory Controller The self refresh initiation time mainly depends on whether all rows or one row defined by MEMSCTRL FSREFB are to be refreshed before entering self refresh mode The SDRAM must remain in self refresh mode for a minimum period defined by MEMSTMG0R TRASMIN and can remain in self refresh mode for an indefinite period of time After the SDRAM exits sel...

Page 302: ...1B static RAM for MCSn MEMSMSKRn MEMTYPE 2 0 010B flash for MCSn If static memory is chosen for a chip select this chip select needs to be associated with one of three timing registers MEMSMTMGRk k 0 to 2 in the chip select mask register for chip select n MEMSMSKRn REGSEL 2 0 k 0 to 2 timing register MSMTMGRk assigned to MCSn 9 3 1 Static RAM timing In the following the meaning of the timing param...

Page 303: ...aution Set the read cycle time parameter MEMSMTMGRk TRC 5 0 one clock higher than required by the connected memory TRC HCLK internal MA 24 0 MD 31 0 Address Data MCSn MSOE MSWR MSBEN H Figure 9 6 Static RAM and flash read timing In the above diagram following timing parameter settings are used MEMSMTMGRk TRC 2 3 clocks for read External Memory Interface Controller Chapter 9 Preliminary User s Manu...

Page 304: ...g read cycles TRC TPRC HCLK internal MA 24 2 MA 1 0 Address 00B 01B 10B 11B MD 31 0 D0 D1 D2 D3 MCSn MSOE MSWR MSBEN H Figure 9 7 Flash page read timing In the above diagram following timing parameter settings are used MEMSMTMGRk TRCk 1 2 clocks for first read MEMSMTMGRk TPRC 0 1 clock for all following reads of the page MEMSMTMGRk PAGEMODE 1 flash supports page mode MEMSMTMGRk PAGESIZE 00B 4 word...

Page 305: ...hold time parameter MEMSMTMGRk TWR defines the number of system clocks the data MD 31 0 and address MA 24 0 is hold stable after deassertion of MSWR TAS TWP TWR HCLK internal MA 24 0 MD 31 0 Address Data MCSn MSOE MSWR MSBEN H Figure 9 8 Static RAM and flash write timing In the above diagram following timing parameter settings are used MEMSMTMGRk TAS 1 MSWR delayed by 1 clock against MCSn MEMSMTMG...

Page 306: ...s turnaround time parameter MEMSMTMGRk TBTA defines the number of system clocks after completion of an access cycle the interface is kept in idle state before starting the next access TBTA TBTA HCLK internal MA 24 0 MD 31 0 A0 A1 A2 D0 write D1 read D2 write MCSn MSOE MSWR MSBEN Figure 9 9 Data bus turnaround timing In the diagram above following timing parameter settings are used MEMSMTMGRk TBTA ...

Page 307: ...AHB slave interface Chip select decoder Address adjustment MCSn MA 24 0 MEMCSALIASn MEMSCSLRn MEMSMSKRn MEMSIZE MEMSMCTRL SDATAW MEMSCONR DDATAW Figure 9 10 Address decoder 9 4 1 Chip select configuration Each chip select area MCSn can be configured to operate with different types of external memory devices The configuration for each chip select area is achieved by means of a register set dedicate...

Page 308: ...per 31 i bits of both match the MCSn is activated The remaining lower address bits i 1 0 are disregarded Below table shows the number of address bits used for comparison in dependency of the chosen memory size Table 9 3 Chip select area base addressing MEMSMSKRn MEMSIZE 4 0 Memory size Address bits i Address bits for comparison MEMSCSLRn CSBADDR 31 i 00000B none a 00001B 64 KB 16 31 16 00010B 128 ...

Page 309: ...ternal memory address IMEMADD 31 i Below figure illustrates the generation of the MCSn signal 30 31 31 i 31 i 31 i 0 0 0 0 0 1 1 1 i i 1 mask 30 31 0 i i 1 MEMSCSLRn 30 31 base address match alias address match 0 0 0 1 1 1 i i 1 mask compare 30 31 and and 0 i i 1 IMEMADD 31 0 compare and 30 31 0 0 0 0 0 1 1 1 i i 1 mask 30 31 0 i i 1 MEMCSALIASn MCSn nor Figure 9 11 Address masking and alias Note ...

Page 310: ...RAM and 0400 0000H to 04FF FFFFH for the flash MEMSCSLR0 0000 0000H MEMSCSLR1 0400 0000H The alias chip select address range shall be 0200 0000H to 03FF FFFFH for the SDRAM and 0500 0000H to 05FF FFFFH for the flash MEMCSALIAS0 0200 0000H MEMCSALIAS1 0500 0000H MEMSCSLR0 0000 0000H 01FF FFFFH MEMCSALIAS0 0200 0000H MEMSCSLR1 0400 0000H 03FF FFFFH 04FF FFFFH MEMCSALIAS1 0500 0000H 05FF FFFFH 16 MB ...

Page 311: ...AWn 2 0 100B SDRAM setup not supported external address output MA 24 0 internal address maximum memory 225 1 byte 32 MB per chips select external memory with 16 bit data bus static memory setup MEMSMCTRL SDATAWn 2 0 000B SDRAM setup MEMSCONR DDATAW 1 0 00B external address output MA 24 0 internal address 1 maximum memory 225 2 byte 64 MB per chips select external memory with 32 bit data bus static...

Page 312: ...DCKE low MDCKE high NOP NOP Refresh single row or execute read write access MEMSREFR TREF Figure 9 13 Power down command sequence The Memory Controller can be set into power down mode by setting MEMSCTRL PWDM 1 When in SDRAM power down mode the Memory Controller keeps switching the device back and forth between power down and refresh mode It remains in power down for a refresh period of time defin...

Page 313: ...te request to the SDRAM occurs while the SDRAM is in power down mode the Memory Controller brings the SDRAM out of power down mode and issues the read write access to the SDRAM The Memory Controller then puts the SDRAM back to power down mode after completion of the read write access External Memory Interface Controller Chapter 9 Preliminary User s Manual S19203EE1V3UM00 313 ...

Page 314: ... address register 1 MEMSCSLR1 MemC_Base 18H Chip select address mask registers 0 MEMSMSKR0 MemC_Base 54H Chip select address mask registers 1 MEMSMSKR1 MemC_Base 58H Chip select alias address register 0 MEMCSALIAS0 MemC_Base 74H Chip select alias address register 1 MEMCSALIAS1 MemC_Base 78H Static memory timing register 0 MEMSMTMGR0 MemC_Base 94H Static memory timing register 1 MEMSMTMGR1 MemC_Bas...

Page 315: ...d to 00B Writing to the read only bits is ignored reading returns undefined values Caution 1 Ravin L provides only a 16 bit external memory data bus Thus the default value 01B of bit 14 to 13 DDATAW 1 0 must be changed to 00B after any reset and must not be altered afterwards 2 The default value 1 of bits 20 and 18 0 of bits 19 and 17 to 15 must not be changed Bit Bit name Function 14 to 13 DDATAW...

Page 316: ... bit 1000B 9 bit 1001B 10 bit 1010B 11 bit default 1011B 12 bit 1100B 13 bit all other prohibited 4 to 3 BKADDRW 1 0 Number of bank address bits 00B 1 bit i e 2 banks 01B 2 bit i e 4 banks default all other prohibited Chapter 9 External Memory Interface Controller 316 Preliminary User s Manual S19203EE1V3UM00 ...

Page 317: ...ot be changed Bit Bit name Function 31 to 27 21 to 18 TEXSR 4 0 TXSR 3 0 TEXSR 4 0 and TXSR 3 0 define the time between exit of SDRAM self refresh mode by setting MEMCTRL SREF 0 and the start of the auto refresh mode respectively data transfer command The number of system clocks is calculated by TEXSR 4 0 4 TXSR 3 0 000H 1 clock 001H 2 clocks 006H 7 clocks default 1FFH 512 clocks 25 to 22 TRC 3 0 ...

Page 318: ...CD 2 0 defines the minimum delay between active and read write commands 000B 1 clock 001B 2 clocks default 111B 8 clocks 5 to 2 TRASMIN 3 0 TRASMIN 3 0 defines the minimum delay between active and precharge commands 0H 1 clock 1H 2 clocks 4H 5 clocks default FH 16 clocks 1 to 0 CASLAT 1 0 CASLAT 1 0 defines the delay between a read command and the availability of first data 00B 1 clock 01B 2 clock...

Page 319: ...14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TINIT 15 0 R W Writing to the read only bits is ignored reading returns undefined values Caution The default value 0 of bits 21 and 20 must not be changed Bit Bit name Function 19 to 16 INITREF 3 0 INITREF 3 0 defines the number of auto refreshes during initialization of the SDRAM 0H 1 refresh 1H 2 refreshes 7H 8 refreshes default FH 16 refreshes 15 to 0 TINIT 15...

Page 320: ...01H 2 banks open default 10H 1FH 31 banks open 11 SREFSTAT SREFSTAT reflects the status of entering the SDRAM self refresh mode Depending on whether all rows or one row are refreshed defined by MEMSCTRL FSREFB before entering self refresh mode it may take some time before SDRAM is put into self refresh mode SREFSTAT 1 indicates the completion of this process 0 SDRAM not in self refresh mode 1 SDRA...

Page 321: ...own mode 1 SREF SREF controls the SDRAM self refresh mode 0 leave SDRAM self refresh mode 1 enter SDRAM self refresh mode 0 INIT By use of INIT the Memory Controller can be forced to initialize the SDRAM 0 initialization sequence is complete 1 force SDRAM initialization This bit is set to 0 automatically once initialization sequence is complete Note After reset release INIT is set to 1 but is set ...

Page 322: ...32 bit units Address MemC_Base 10H Initial Value 0000 0410H This register is initialized by any reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TREF 15 0 R W Writing to the read only bits is ignored reading returns undefined values Bit Bit name Function 15 to 0 TREF 15 0 Number of clock cycl...

Page 323: ...Initial Value MEMSCSLR0 0000 0000H MEMSCSLR1 0400 0000H These registers are initialized by any reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CSBADDR 31 16 R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R Writing to the read only bits is ignored reading returns undefined values Bit Bit name Function 31 to 16 CSBADDR 31 16 Upper 16 bit...

Page 324: ...R R R W R W R W Writing to the read only bits is ignored reading returns undefined values Bit Bit name Function 10 to 8 REGSEL 2 0 REGSEL 2 0 determines which timing parameter register use MEMSMTMGk of memory connect to chip select n is to be used This is only of concern for static memory types SRAM and flash memory 000B use MEMSMTMG0 001B use MEMSMTMG1 010B use MEMSMTMG2 default 7 to 5 MEMTYPE 2 ...

Page 325: ...t 00001B 64 KB 00111B 4 MB 00010B 128 KB 01000B 8 MB 00011B 256 KB 01010B 32 MB 00100B 512 KB 01011B 64 MB MCS1 default 00101B 1 MB 01100B 128 MB 00110B 2 MB all other prohibited a No memory connected to chip select n External Memory Interface Controller Chapter 9 Preliminary User s Manual S19203EE1V3UM00 325 ...

Page 326: ...H Initial Value MEMCSALIAS0 0000 0000H MEMCSALIAS1 0400 0000H These registers are initialized by any reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CSAADDR 31 16 R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R Writing to the read only bits is ignored reading returns undefined values Bit Bit name Function 31 to 16 CSAADDR 31 16 Upper ...

Page 327: ... 7 6 5 4 3 2 1 0 TWP 5 0 TWR 1 0 TAS 1 0 TRC 5 0 R W R W R W R W a The default value 0 of bit 28 must be changed to 1 after any reset Writing to the read only bits is ignored reading returns undefined values Caution 1 Bit 28 of MEMSMTMGRk must be set to 1 after reset and must not be altered afterwards 2 The default value 0 of bits 26 to 29 must not be changed Bit Bit name Function 28 bit 28 The de...

Page 328: ... clocks of the MSWR active time 00H 1 clock 01H 2 clocks 3H 4 clocks MEMSMTMGR2 default 3FH 64 clocks 9 to 8 TWR 1 0 The write address data hold time parameter TWR 1 0 defines the number of system clocks the data MD 31 0 and address MA 24 0 is hold stable after deassertion of MSWR 00B 0 clocks 01B 1 clock MEMSMTMGR2 default 10B 2 clocks 11B 3 clocks 7 to 6 TAS 1 0 The write address setup time para...

Page 329: ...tion 0CH 13 clocks MEMSMTMGR2 default 3FH 64 clocks Caution Set TRC 5 0 one clock higher than required by the connected memory External Memory Interface Controller Chapter 9 Preliminary User s Manual S19203EE1V3UM00 329 ...

Page 330: ... bits is ignored reading returns undefined values Caution 1 Ravin L provides only a 16 bit external memory data bus Thus the default value 001B of bit 15 to 13 SDATAW2 2 0 must be changed after any reset 2 The default value 0 of bits 3 to 1 1 of bit 0 must not be changed Bit Bit name Function 15 to 13 12 to 10 9 to 7 SDATAW2 2 0 SDATAW1 2 0 SDATAW0 2 0 SDATAWk 2 0 k 0 to 2 defines the width of sta...

Page 331: ...External Memory Interface Controller Chapter 9 Preliminary User s Manual S19203EE1V3UM00 331 ...

Page 332: ... 0820H Video input enable control SYSVIEN R W 0000 0824H Video output control SYSVOCTRL R W 0000 0828H System watchdog control SYSWDCTRL R W 0000 082CH System control write protection SYSPROTECT W 0000 1D00H Geometry control DRWCONTROL W Status control DRWSTATUS R 0000 1D04H Surface control DRWCONTROL2 W Hardware version and feature set ID DRWHWREVISION R 0000 1D10H Limiter 1 start value DRWL1STAR...

Page 333: ... 0000 1DA4H V Limiter x axis increment integer part DRWLVXADDI W 0000 1DA8H V Limiter y axis increment integer part DRWLVYADDI W 0000 1DACH V Limiter increment fractional parts DRWLVYXADDF W 0000 1DB4H Texels per texture line DRWTEXPITCH W 0000 1DB8H Texture size or texture address mask DRWTEXMASK W 0000 1DBCH Texture base address DRWTEXORIGIN W 0000 1DC0H Interrupt control DRWIRQCTL W 0000 1DC4H ...

Page 334: ...alette registers VO0LCDPALETTE R W 0000 3000H SDRAM configuration MEMSCONR R W 0000 3004H SDRAM timing 0 MEMSTMG0R R W 0000 3008H SDRAM timing 1 MEMSTMG1R R W 0000 300CH SDRAM control MEMSCTLR R W 0000 3010H SDRAM refresh MEMSREFR R W 0000 3014H Chip select base address 0 MEMSCSLR0 R W 0000 3018H Chip select base address 1 MEMSCSLR1 R W 0000 3054H Chip select address mask 0 MEMSMSKR0 R W 0000 3058...

Page 335: ...us VO1LCDRIS R 0000 4024H VO1 Masked interrupt status VO1LCDMIS R 0000 4028H VO1 Interrupt clear VO1LCDICR R 0000 402CH VO1 Current address VO1LCDUPCURR R 0000 4200H 0000 43FCH VO1 Colour palette registers VO1LCDPALETTE R W Register List Chapter 10 Preliminary User s Manual S19203EE1V3UM00 335 ...

Page 336: ...9203EE1V1UM00 date published December 02 2008 Chapter Page Description 6 169 generation of VInSCLINT in case of interlaced video changed 6 186 FLD1EN FLD2EN settings corrected 6 186 generation of VInSCLINT in case of interlaced video changed 9 294 description of SDRAM feedback clock added 336 Preliminary User s Manual S19203EE1V3UM00 ...

Page 337: ...7 Drawing Engine 234 Band filter 234 Base address DrwE_Base 215 Base colour register DRWCOLOR1 265 Blending 245 Bounding box dimension DRWSIZE 284 Cache control register DRWCACHECTL 262 Clamping unit 235 Colour formats 223 Colourization 240 Colour lookup table for the indexed texture format DRWTEXCLUT 283 Combiner unit 236 Control registers 253 Coordinate transformation 225 Display list based mode...

Page 338: ... 255 DRWCONTROL2 258 DRWDLISTIRQ 250 DRWDLISTSTART 287 DrwE_Base 215 DRWENUMIRQ 250 DRWHWREVISION 264 DRWIRQCTL 260 DRWLmBAND 271 DRWLnSTART 268 DRWLnXADD 269 DRWLnYADD 270 DRWLUSTART 275 DRWLUXADD 276 DRWLUYADD 277 DRWLVSTARTF 279 DRWLVSTARTI 278 DRWLVXADDI 280 DRWLVYADDI 281 DRWLVYXADDF 282 DRWORIGIN 286 DRWPATTERN 267 DRWPERFCOUNTk 289 DRWPERFTRIGGER 288 DRWPITCH 285 DRWSIZE 284 DRWSTATUS 263 D...

Page 339: ... Chip select address mask register MEMSMSKRn 324 Chip select alias address registers MEMCSALIASn 326 Chip select base address registers MEMSCSLRn 323 Chip select configuration 307 Control Registers 314 data hold time SRAM flash 327 MEMCSALIASn 308 Memory Size 308 MEMSCSLRn 308 MEMSMSKRn 308 MEMSREFR 297 Pin functions 290 Power down 312 RAS timing 317 read cycle time 327 SDRAM configuration registe...

Page 340: ...ode register SYSBOOTMODE 108 Clock control register SYSCLKCTRL 104 Control Registers 100 Pin multiplex control register SYSPINMUX 110 PLL control register SYSPLLCTRL 101 Reset control register SYSRESET 107 System Controller revision register SYSREV 109 System register write protection register SYSPROTECT 118 System watchdog control register SYSWDCTRL 117 Video Input control register SYSVIEN 114 Vi...

Page 341: ...M enable 97 Colour formats 191 Colour look up table 191 Control Registers 201 Display data output formats 192 FIFO 197 Framebuffer base address 197 Framebuffer base address register VOnLCDUPBASE 208 Horizontal axis display control register VOnLCDTIMING0 202 Interrupt controller 199 Interrupt mask register VOnLCDIMSC 211 Interrupts 197 Interrupt sources 198 LCD colour palette registers VOnLCDPALETT...

Page 342: ...nHSYNC 194 VOnINT 198 VOnLCDCONTROL 206 VOnLCDICR 199 213 VOnLCDIMSC 199 211 VOnLCDMIS 199 214 VOnLCDPALETTE 212 VOnLCDRIS 199 210 VOnLCDTIMING0 202 VOnLCDTIMING1 203 VOnLCDTIMING2 204 VOnLCDUPBASE 208 VOnLCDUPCURR 209 VOnMBEINT 198 VOnNBAINT 198 VOnVCPINT 195 198 VOnVSYNC 194 VOnVSYNC function 97 W Wait function HADWAIT 136 Watermark Video Output FIFO 197 Word combining 134 Write protection 100 Y...

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