NEC PD17062 Datasheet Download

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DATA SHEET

MOS INTEGRATED CIRCUIT

PD17062

Document No. IC-3560
(O.D. No. IC-8937)
Date Published January 1995 P
Printed in Japan

The

PD17062 is a 4-bit CMOS microcontroller for digital tuning systems. The single-chip device

incorporates an image display controller enabling a range of different displays, together with a PLL frequency

synthesizer.

The CPU has six main functions: 4-bit parallel addition, logic operation, multiple bit test, carry-flag set/

reset, powerful interrupt, and a timer.

The device contains a user-programmable image display controller (IDC) for on-screen displays. The

different displays can be controlled with simple programs.

The device also has a serial interface function, many input/output (I/O) ports controlled by powerful I/O

instructions, and 6-bit pulse width modulation (PWM) output for a 4-bit A/D converter and D/A converter.

FEATURES

4-BIT SINGLE-CHIP MICROCONTROLLER CONTAINING PLL FREQUENCY

SYNTHESIZER AND IMAGE DISPLAY CONTROLLER

• 4-bit microcontroller for digital tuning system

• Internal PLL frequency synthesizer: With prescaler

PB595

• 5 V

10%

• Low-power CMOS

• Program memory (ROM): 8K bytes (16 bits

3968

steps)

• Data memory (RAM): 4 bits

336 words

• 6 stack levels

• 35 easy-to-understand instruction sets

• Support of decimal operations

• Instruction execution time: 2

s (with an 8-MHz

crystal)

• Internal D/A converter: 6 bits

4 (PWM output)

• Internal A/D converter: 4 bits

• Internal horizontal synchronizing signal counter

• Internal commercial power frequency counter

• Internal power-failure detector and power-on reset

circuit

• Internal image display controller (IDC) (user-pro-

grammable)

Number of characters in display: Up to 99 on a

single screen

Display configuration: 14 rows

19 columns

Number of character types: 120

Character format: 10

15 dots (rimming possible)

Number of colors: 8

Character size: Four sizes in each of the horizontal

and vertical dimensions

Internal 1H circuit for preventing vertical deflection

• Internal 8-bit serial interface (One system with two

channels: three-wire or two-wire)

• Interrupt input for remote-controller signals (with

noise canceler)

• Many I/O ports

Number of I/O ports

: 15

Number of input ports : 4

Number of output ports: 8

1995

Summary of Contents for PD17062

Page 1: ... CONTROLLER 4 bit microcontroller for digital tuning system Internal PLL frequency synthesizer With prescaler µPB595 5 V 10 Low power CMOS Program memory ROM 8K bytes 16 bits 3968 steps Data memory RAM 4 bits 336 words 6 stack levels 35 easy to understand instruction sets Support of decimal operations Instruction execution time 2 µs with an 8 MHz crystal Internal D A converter 6 bits 4 PWM output ...

Page 2: ... columns Number of character types 120 user programmable Number of colors 8 Character size Vertical dimension 1 to 4 times can be set for each line Horizontal dimension 1 to 4 times can be set for each character Serial interface Serial interface 0 two wire or I2C bus compatible Serial interface 1 two wire or three wire D A converter 6 bits 4 PWM output withstand voltage of up to 12 5 V A D convert...

Page 3: ...TNC Interrupt signal input TMIN Timer event input NC No connection VCO Local oscillation input PSC Pulse swallow control output VDD Main power supply PWM0 to PWM3 Pulse width modulation output VSYNC Verticalsynchronizingsignalinput P0A0 to P0A3 Port 0A XIN Clock oscillation P0B0 to P0B3 Port 0B XOUT Clock oscillation P0C0 to P0C3 Port 0C 1 3 2 4 6 5 7 9 8 10 12 11 13 15 14 16 18 17 19 21 20 22 24 ...

Page 4: ...6 55 54 53 52 51 50 49 POB2 TMIN ADC0 POB3 HSCNT P1C2 NC NC NC P1C3 ADC1 NC VSYNC BLANK BLUE NC HSYNC P1C1 NC P0D0 ADC2 PWM2 PWM3 PWM0 NC NC VDD VCO NC EO GND PSC NC NC PWM1 NC P0D 1 ADC 3 P0D 3 ADC 5 P0D 2 ADC 4 P0C 2 NC P0C 3 NC P0A 0 SDA INT NC P0A 1 SCK P0B 0 SI P0B 1 P0A 1 SCL P0A 3 SO P0C 0 P0C 1 CE X IN X OUT NC P1A 0 P1A 1 NC P1B 3 GND P1B 1 RED GREEN P1B 2 P1B 0 P1A 3 P1A 2 PD17062GC 3BE ...

Page 5: ...ADC1 P1C2 P1C1 ADC0 PWM0 PWM1 PWM2 PWM3 P1A0 P1A1 P1A2 P1A3 P1B0 P1B1 P1B2 P1B3 P0C0 P0C1 P0C2 P0C3 INTNC XIN XOUT VDD CE GND CPU Peripheral Instruction Decoder Interrupt Controller P0C P1B P1A PWM PLL IDC Serial I O P0A P0B Hsync Counter Timer Controller RF RAM 336 4 bits Including VRAM SYSREG ALU ROM 3968 16 bits Including CROM Program Counter Stack 6 12 bits OSC Reset P0D P1C A D ...

Page 6: ... 29 5 1 STRUCTURE OF DATA MEMORY 29 5 2 FUNCTIONS OF DATA MEMORY 34 5 3 NOTES ON USING DATA MEMORY 38 6 GENERAL PURPOSE REGISTER GR 40 6 1 STRUCTURE OF THE GENERAL PURPOSE REGISTER 40 6 2 FUNCTION OF THE GENERAL PURPOSE REGISTER 40 6 3 ADDRESS GENERATION FOR GENERAL PURPOSE REGISTER AND DATA MEMORY IN INDIVIDUAL INSTRUCTIONS 42 6 4 NOTES ON USING THE GENERAL PURPOSE REGISTER 46 7 ARITHMETIC LOGIC ...

Page 7: ...ISTER 22H 81 9 16 PORT1C I O SETTING 27H 82 9 17 SERIAL I O0 STATUS REGISTER 28H 82 9 18 INTERRUPT PERMISSION FLAG 2FH 83 9 19 CROM BANK SELECTION 30H 83 9 20 IDCEN 31H 84 9 21 PLL UNLOCK FLIP FLOP DELAY CONTROL REGISTER 32H 84 9 22 P1BBIOn 35H 85 9 23 P0BBIOn 36H 85 9 24 P0ABIOn 37H 86 9 25 SETTING OF INTERRUPT REQUEST GENERATION TIMING IN SERIAL INTERFACE MODE 38H 86 9 26 SHIFT CLOCK FREQUENCY S...

Page 8: ... STOP FUNCTION 164 13 6 OPERATION OF THE DEVICE AT A HALT OR CLOCK STOP 167 14 RESET 171 14 1 RESET BLOCK CONFIGURATION 171 14 2 RESET FUNCTION 172 14 3 CE RESET 173 14 4 POWER ON RESET 177 14 5 RELATIONSHIP BETWEEN CE RESET AND POWER ON RESET 180 14 6 POWER FAILURE DETECTION 184 15 GENERAL PURPOSE PORT 189 15 1 CONFIGURATION AND CLASSIFICATION OF GENERAL PURPOSE PORT 189 15 2 FUNCTIONS OF GENERAL...

Page 9: ... REGISTER ADCCHn 236 19 6 EXAMPLE OF A D CONVERSION PROGRAM 237 20 IMAGE DISPLAY CONTROLLER 240 20 1 SPECIFICATION OVERVIEW AND RESTRICTIONS 240 20 2 DIRECT MEMORY ACCESS 243 20 3 IDC ENABLE FLAG 245 20 4 VRAM 246 20 5 CHARACTER ROM 255 20 6 BLANK R G AND B PINS 263 20 7 SPECIFYING THE DISPLAY START POSITION 264 20 8 SAMPLE PROGRAMS 268 21 HORIZONTAL SYNC SIGNAL COUNTER 274 21 1 HORIZONTAL SYNC SI...

Page 10: ...10 µPD17062 23 5 PERIPHERAL HARDWARE REGISTER 286 23 6 OTHERS 286 24 ELECTRICAL CHARACTERISTICS 287 25 PACKAGE DRAWINGS 289 26 RECOMMENDED SOLDERING CONDITIONS 291 APPENDIX DEVELOPMENT TOOLS 292 ...

Page 11: ... state the voltage can be reduced to 3 5 V When the supply voltage increases from 0 V to 4 V a power on reset occurs and the program is started from address 0 Apply an identical voltage to all pins Inputs the signal obtained by dividing the local oscillation output by the specialized prescaler Outputs the PLL error signal The signal is input through the external LPF to the local oscillation circui...

Page 12: ...t be active low The input signal can generate an interrupt Input of port 1C and A D converter P1C3 to P1C1 3 bit I O port ADC1 Input of a 4 bit A D converter Input of a 4 bit A D converter Serial interface and input for port 0B port 0A horizontal synchronizing signal counter and timer P0A3 to P0A0 4 bit I O port Each bit can be set for input or output P0B3 to P0B0 4 bit I O port Each bit can be se...

Page 13: ...55 5 6 7 8 10 12 14 22 25 37 39 40 41 42 44 56 57 Interrupt input Contains the noise canceler An interrupt can be generated at either the rising or falling edge of the input signal No connection The pins are not connected to the internal circuit of the device They can be used as desired Input ...

Page 14: ...CIRCUITS OF THE PINS P0A P0A3 SO P0A2 SCK P0B P0B1 P0B0 SI P1B P1B3 P1B2 P1B1 P1B0 P1C P1C3 ADC1 P1C2 P1C1 VDD VDD A D converter only for P1C ADC RESET signal except for P1C Read instruction only for P1C P0A P0A1 SCL P0A0 SDA I O ...

Page 15: ...C2 P0C1 P0C0 RED GREEN BLUE BLANK PSC Output PWM PWM3 PWM2 PWM1 PWM0 P1A P1A3 P1A2 P1A1 P1A0 Output P0D P0D3 ADC5 P0D2 ADC4 P0D1 ADC3 P0D0 ADC2 A D Converter High on state resistance Input ADC0 A D converter selection signal ...

Page 16: ...16 µPD17062 P0B3 HSCNT Port Horizontal synchronizing signal counter P ch N ch P0B2 TMIN Port Timer counter P ch N ch ...

Page 17: ...17 µPD17062 HSYNC VSYNC INTNC CE Hysteresis input XOUT XIN XIN XOUT EO VCO Input ...

Page 18: ...d into pages The range of page 0 is from 0000H to 07FFH while that of page 1 is from 0800H to 0F7FH The range from 0800H to 0F7FH can be used as the CROM character ROM area in which the display patterns for the IDC are stored If this area is not used as CROM it can be used as a program area The range from 0000H to 00FFH is a table reference area The area is used by the JMP AR CALL AR MOVT PUSH and...

Page 19: ...hat cannot be rewritten by the execution of an instruction In this document program memory and ROM read only memory are synonymous 2 3 PROGRAM FLOW A program stored in program memory is usually executed one address at a time starting from address 0000H If another program is to be executed upon some condition being satisfied the program flow must be branched To achieve this the branch instruction B...

Page 20: ...in an address register AR described below See also Chapter 3 2 4 1 Direct Branch A direct branch instruction uses the least significant bit of the operation code and the 11 bits of its operand 12 bits in total to specify the destination program memory address The destination of the direct branch instruction can be any address in program memory between 0000H and 0F7FH 2 4 2 Indirect Branch The indi...

Page 21: ...ging Direct branch instructions to page 0 addresses 0000H to 07FFH and page 1 addresses 0800H to 0F7FH use different operation codes as shown in Fig 2 2 The operation codes of the direct branch instructions to page 0 and page 1 are 0CH and 0DH respectively The difference arises because the direct branch instruction uses the addr operand which is only 11 bits long together with the least significan...

Page 22: ...is used the destination or the first address of the subroutine to be called must be page 0 addresses 0000H to 07FFH The instruction cannot call a subroutine whose first address is in page 1 addresses 0800H to 0F7FH The subroutine return instruction RET RETSK can be in page 1 The CALL instruction can be in page 0 or page 1 Examples 1 When the subroutine return instruction is in page 0 When the firs...

Page 23: ...OV AR1 8H CALL AR Label Label 0500H SUB1 RET 07FFH 0800H 0F7FH SUB2 SUB3 RET MOV AR0 0H MOV AR1 1H CALL AR Fig 2 4 Sample Uses of Subroutine Call Instruction a If the subroutine return instruction is in page 1 b If the first address of the subroutine is in page 1 Address Program memory Instruction CALL SUB1 Page 0 Page 1 0000H 07FFH 0800H 0F7FH CALL SUB1 Address Program memory Instruction CALL SUB...

Page 24: ... NOTES ON USING THE BRANCH INSTRUCTION AND SUBROUTINE CALL INSTRUCTION The 17K series assembler AS17K detects an error if a program memory address numeric address is directly specified in the operand of the branch instruction BR or subroutine call instruction CALL The assembler provides this function to minimize the number of bugs arising from program modification Examples 1 Instruction causing an...

Page 25: ... operand field is loaded into the program counter If a skip instruction has been executed the address of the instruction following the skip instruction is specified regardless of the contents of the skip instruction If the specified address contains a skip condition the instruction following the skip instruction is regarded as being a NOP instruction That is the NOP instruction is executed and the...

Page 26: ...address stack register The contents of the stack pointer are decremented by 1 whenever a push operation CALL MOVT or PUSH instruction or interrupt acceptance is performed or incremented by 1 whenever a pop operation RET RETSK RETI MOVT or POP instruction is performed The high order bit of the stack pointer is always set to 0 The stack pointer can indicate any of eight different values 0H to 7H How...

Page 27: ...in Fig 4 3 If an interrupt is accepted the value of the two bits of the bank register BANK and the value of the one bit of the index enable flag IXE in the system register SYSREG described later are saved to an interrupt stack register Once an interrupt return instruction RETI has been executed the contents of the interrupt stack register are returned to the bank register and the index enable flag...

Page 28: ...rupt Stack Registers MSB LSB 0H 1H BANKSK0 BANKSK1 IXESK0 IXESK1 Fig 4 4 Behavior of Interrupt Stack Registers Not defined B A Not defined A Not defined A Not defined Not defined Not defined RETI RETI Interrupt B Interrupt A VDD is applied ...

Page 29: ...hese three banks are called BANK0 BANK1 and BANK2 In each bank data is assigned an address in units of four bits The high order three bits are called the row address while the low order four bits are called the column address For example the data memory location having row address 1H and column address AH is referred to as the data memory location having address 1AH One address consists of four bi...

Page 30: ...stem register P0B 4 bits P0C 4 bits P0D 4 bits BANK0 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 P1A 4 bits System register P1B 4 bits P1C 4 bits Fixed at 0 BANK1 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 P0A 4 bits System register P0B 4 bits P0C 4 bits P0D 4 bits BANK2 The same register is allocated for each bank ...

Page 31: ...System Register 5 1 2 Structure of the Data Buffer DBF The data buffer consists of four nibbles located at addresses 0CH to 0FH of BANK0 in data memory Fig 5 3 shows the structure Fig 5 3 Structure of the Data Buffer 74H 75H 76H 77H 78H 79H 7AH 7BH 7CH 7DH 7EH 7FH Address Program status word PSWORD System register SYSREG Register symbol Address register AR Window register WR Bank register BANK Ind...

Page 32: ...r pointer in the system register Fig 5 4 shows the structure Fig 5 4 Structure of the General Purpose Register GR SYSREG 0 1 2 3 4 5 6 7 SYSREG 0 1 2 3 4 5 6 7 Row address 0 1 2 3 4 5 6 7 8 9 A B C D E F Column address BANK0 BANK1 General purpose register The same register is allocated for each bank Area specifiable as general purpose register Pointed to by general purpose register pointer RP in s...

Page 33: ...rt Registers 5 1 5 Structure of General Purpose Data Memory General purpose data memory consists of that part of memory other than the system register and the port registers of data memory General purpose data memory consists of a total of 336 words with 112 words in each of BANK0 to BANK2 5 1 6 Unmounted Data Memory As shown in Fig 5 6 nothing is assigned to bit 0 of address 72H in BANK1 of the p...

Page 34: ...nstruction is for addition to the contents of data memory address 76H Address 76H is part of the system register Because the system register always exists regardless of the bank the ADD instruction eventually adds 0001B to the contents of address 76H of the system register regardless of the bank Remark For explanation of how to code instructions see Section 5 3 1 Example 2 Operation between data m...

Page 35: ...pose register be treated as data memory For example assume that row address 0H of BANK0 is allocated as the general purpose register i e the value of the general purpose register pointer is 0 In this case if the currently selected bank is BANK0 i e the value of the bank register is 0 executing ADD 00H 1 increments by 1 the contents of address 00H of BANK0 which is allocated as the general register...

Page 36: ... Table 5 1 Data Memory Manipulation Instructions Function Instruction ADD ADDC SUB SUBC AND OR XOR SKE SKGE SKLT SKNE MOV LD ST SKT SKF Addition Subtraction Logical operation Operation Comparison Transfer Decision ...

Page 37: ...A0 b3 P1B3 b2 P1B2 b1 P1B1 b0 P1B0 b3 P1C3 b2 P1C2 b1 P1C1 b0 P1C0 Port0A Port0B Port0C Port0D Port1A Port1B Port1C P0A3 P0A2 P0A1 P0A0 P0B3 P0B2 P0B1 P0B0 P0C3 P0C2 P0C1 P0C0 P0D3 P0D2 P0D1 P0D0 P1A3 P1A2 P1A1 P1A0 P1B3 P1B2 P1B1 P1B0 P1C3 P1C2 P1C1 General purpose port data register Address Bank Symbol Bit symbol Corresponding port Pin Symbol Input or output BANK0 BANK2 BANK1 Input and output gr...

Page 38: ...FH in BANK0 is specified directly Instructions that do not cause an error M02F MEM 0 2FH Address 2FH of BANK0 is defined symbolically in MOV M02F 0001B M02F as a memory type address MOV MD 2FH 0001B Address 2FH is converted into a memory type address by using MD However the use of this type of instruction should be avoided to reduce the likelihood of bugs arising Using an assembler pseudo instruct...

Page 39: ...no change 2 Assembler behavior Normal assembly is performed No error occurs 3 Emulator IE 17K behavior If a read instruction is executed a 0 is read Executing a write instruction results in no change No error occurs M1 M2 M3 MEM MEM MEM 0 15H 1 15H 2 15H Bank Row address Column address BANK1 MOV M1 MOV M2 MOV M3 0000B 0000B 0000B Assembler built in macro instruction BANK 1 M1 M2 and M3 are defined...

Page 40: ...ter pointer of the system register The general purpose register consists of seven bits However the high order four bits are fixed to 0 so within the data memory space only row addresses 0H to 7H of BANK0 can be used as the general purpose register See Section 8 6 6 2 FUNCTION OF THE GENERAL PURPOSE REGISTER The general purpose register can be used to perform an operation or to transfer data betwee...

Page 41: ...2 3 4 5 6 7 1 Column address Row addresses 0H to 7H of BANK0 can be freely specified using the general purpose register pointer RP Row address General purpose register 16 words General purpose register allocated when RP 010B System register RP BANK0 System register BANK1 The same system register is viewed System register BANK2 General purpose register pointer RP Symbol Address Bit Function ...

Page 42: ...result being stored into the general purpose register The address of the general purpose register is generated as described above for each of the instructions listed in Table 6 1 Table 6 1 Manipulation Instructions Executed between the General Purpose Register and Data Memory Table 6 2 Address Generation for General Purpose Register and Data Memory Data memory address specified in m Instruction Ad...

Page 43: ...e contents of address 04H of BANK0 part of the general purpose register to the contents of data memory address 56H then stores the result into address 04H of the general purpose register See Fig 6 2 Fig 6 2 Execution of Instructions in Example 1 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 2 3 4 5 6 7 1 M RP 0000000B BANK0 ADD 04H 56H System register Column address General purpose register Row address ...

Page 44: ... and the row address specified in m 5 in the above example is the row address of data memory That is the data memory address is 58H see Fig 6 3 See Section 8 5 for an explanation of the indirect transfer of the general purpose register contents Fig 6 3 Execution of Instructions in Example 2 Example 3 AND RPL 0000B RP 0000000B The general purpose register is allocated in row address 0H of BANK0 MOV...

Page 45: ...rds to the register and then store them into data memory In contrast if the row address of the general purpose register is changed using the general purpose register pointer as shown in example 3 the operation can be completed simply by executing a storage instruction Fig 6 4 Execution of Instructions in Example 3 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 2 3 4 5 6 7 1 RP BANK0 0 2 3 4 5 6 7 1 BANK1 0 2 3...

Page 46: ...s for example 24H as the value specified in r when using the assembler In this case only the low order four bits are needed as the value for r so the assembler ignores value 2H which is a row address Thus executing instruction LD 24H 32H produces the same result as executing the instruction in the above example If when using the assembler the address of the general purpose register is specified di...

Page 47: ...d immediate data That is the execution of an arithmetic logical instruction that involves data memory allocated as the general purpose register and immediate data requires that the data memory be treated as data memory rather than the general purpose register 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 2 3 4 5 6 7 1 RP BANK0 RP 0000010B LD 04H 32H System register Column address General purpose register Row ...

Page 48: ...c and logic operations on the 4 bit data in the data memory and performs discrimination comparison rotation and transfer Fig 7 1 Overview of the ALU Block Data memory Data bus Program status word Address controller Temporary storage register A Temporary storage register B Indexing memory pointer Detecting a carry borrow or zero Setting decimal calculation or result storage ALU Arithmetic operation...

Page 49: ...he ALU For details of the program status word see Section 8 7 7 2 4 Decimal Conversion Circuit If the BCD flag of the program status word is set to 1 when an arithmetic operation is executed the decimal conversion circuit converts the results of the arithmetic operation to a decimal number 7 2 5 Address Controller The address controller specifies an address in data memory At the same time the circ...

Page 50: ... The result is not stored Decimal operation The result is stored Decimal operation The result is not stored Not changed Not changed Not changed Not changed Not changed Set by a carry or borrow Otherwise the flag is reset Retains the previous state Retains the previous state Retains the previous state Retains the previous state Retains the previous state Retains the previous state Retains the previ...

Page 51: ...memory row address pointer MPE Memory pointer enable flag r General purpose register column address RP General purpose register pointer Contents addressed by b3 b2 b1 b0 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b2 b1 b0 b3 b2 b1 b0 IXE MPE 0 0 0 1 1 0 1 1 RP r BANK m BANK mR r r MP BANK m BANK mR r MP r IXH IXM IX Logical OR General purpose register address specified with ...

Page 52: ...1 1100B 27 1 1011B 1 1101B 28 1 1100B 1 1010B 29 1 1101B 1 1011B 30 1 1110B 1 1100B 31 1 1111B 1 1101B Operation result Decimal addition CY CY Operation result 0 0 0000B 0 0000B 1 0 0001B 0 0001B 2 0 0010B 0 0010B 3 0 0011B 0 0011B 4 0 0100B 0 0100B 5 0 0101B 0 0101B 6 0 0110B 0 0110B 7 0 0111B 0 0111B 8 0 1000B 0 1000B 9 0 1001B 0 1001B 10 0 1010B 1 1100B 11 0 1011B 1 1101B 12 0 1100B 1 1110B 13 ...

Page 53: ...elf the result of the operation is stored and a carry borrow or zero cannot be discriminated If the CMP flag is set the result of the arithmetic operation is not stored and the CY and Z flags are set or reset as usual 7 4 2 Notes on Performing Decimal Operations A decimal operation can be carried out only when the operation result is within the following ranges 1 The result of addition is between ...

Page 54: ...pose register pointer Program status word Fig 8 1 Configuration of System Register b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 AR3 AR2 AR1 AR0 WR BANK IXH IXM MPH MPL IXL RPH RPL PSW 74H 75H 76H 77H 78H 79H 7AH 7BH 7CH 7DH 7EH 7FH 0 0 0 0 0 0 0 0 0 0 P 0 0 0 0 0 0 0 0 B C D C M P C Y Z I X E IX Addr...

Page 55: ...ipulated using the PUSH and POP instructions The PUSH instruction stores the contents of the address register in the stack specified by the current stack pointer and decrements the contents of the stack pointer by 1 The POP instruction increments the contents of the stack pointer by 1 and loads the contents of the stack specified by the current stack pointer into the address register AR3 and AR2 o...

Page 56: ...s exist at addresses 74H 7FH of all banks Executing MOV 78H 0 in BANK1 and MOV 78H 0 in BANK2 both result in writing 0 to address 78H of the system register Therefore system register manipulation is not constrained to the concept of banks When an interrupt is accepted BANK is saved Table 8 1 Specification of Data Memory Bank 8 4 MEMORY POINTER ENABLE FLAG MPE The MPE specifies whether to specify t...

Page 57: ...r 7BH and 7CH IXM IXL The index register is used to indirectly specify a data memory address The data memory row address pointer consists of 7 bits including the three low order bits of 7AH MPH and 7BH MPL This means that the seven high order bits of the index register and data memory row address pointer are shared The four high order bits of the index register i e the four high order bits of the ...

Page 58: ... with the memory pointer enable flag set to 1 the data memory row address pointer executes the instruction regarding the indirect address bank specified by the general purpose register and row address as being the value of the data memory row address pointer Table 8 2 shows the modification of data memory and the indirect address by the index register and data memory row address pointer All data m...

Page 59: ... RP Contents of general purpose register address MP Contentsofdatamemoryrowaddresspointer b3 b2 b1 b0 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b2 b1 b0 b3 b2 b1 b0 IXE MPE 0 0 0 1 1 0 1 1 RP r BANK m BANK mR R MP R BANK r BANK mR MP R Logical OR IXH R OR Logical IX ADD ADDC SUB SUBC AND OR XOR SKE SKGE SKLT SKNE SKT SKF LD ST MOV m m n4 r m m n4 m n4 m n m n4 r m r m Gener...

Page 60: ...o address 38H This means that the MOV r m instruction transfers the contents of data memory m to the same row address in the above case 3 as m and the column address in the above case 38H specified by the contents in the above case 8 of general purpose register r See Example 2 in Fig 8 3 Example 3 When the row address of the general purpose register is 0 for BANK0 MOV 0BH 0EH 0BH 0EH MOV 34H 0BH R...

Page 61: ...0 3 3 5 4 8 r r m MOV 05H 34H 0 1 2 3 4 5 6 7 8 9 A B C D E F 8 E 0 1 2 3 4 5 6 7 Column address Row address Example 1 ADD03H 11H Specifies the destination column address Specifies the source column address General purpose register Example 2 MOV 05H 34H Example 3 MOV 34H 0BH Bank Row address Column address Contents of R Same as M ...

Page 62: ...e data memory whose bank and row addresses are the values of the data memory row address pointer in the above example BANK0 row address 5 and whose column address is specified in the above case 58H of BANK0 by general purpose register r in the above case 8 See Example 1 in Fig 8 4 Compared to MPE 0 Example 2 in Section 8 5 3 the bank and row address of the data memory address in the indirect side ...

Page 63: ... 1 2 3 4 5 6 7 8 9 A B C D E F 8 E 0 1 2 3 4 5 6 7 MP 00101B Column address Specifies the destination column address Specifies the source column address General purpose register Example 1 MOV 05H 34H Bank Row address Column address Contents of R Value of MP Example 2 MOV 3AH 0BH The bank and row address are set to 000101B the value of the data memory row address pointer ...

Page 64: ...ss 03H This means that the ADD r m instruction performs the OR operation on the address in the above case 11H of BANK0 specified by m and the index register value in the above case 000000010B the result becoming the real address in the above case 13H of BANK0 Then the instruction is executed at the real address See Fig 8 5 Compared to IXE 0 Example 1 in Section 8 5 3 the address of the data memory...

Page 65: ...65 µPD17062 Fig 8 5 Data Memory Address Modification with IXE 1 0 1 2 3 4 5 6 R 0 1 2 3 4 M ADD r m Column address Row address General purpose register Specified by IX ...

Page 66: ...his flag is reset The set condition differs according to the contents of the CMP flag 7EH 7FH Index enable flag When this flag is set index modification is enabled Zero flag 1 When CMP 0 The flag is set when the arithmetic operation result is 0 2 When CMP 1 The flag is set when the result of the arithmetic operation executed at Z 1 is 0 Carry flag The carry flag is set when a carry occurs during t...

Page 67: ...heral circuit addresses are actually allocated to the high order 64 nibbles 00H 3FH and addresses 40H 7FH of the currently selected bank of data memory to the low order 64 nibbles 40H 7FH This means that 40H 7FH of each bank of data memory belongs to both the data memory address space and the register file address space In the assembler the control register file is allocated to 80H BFH ...

Page 68: ... I D C E N 0 0 P L U L S E N 1 P L U L S E N 0 P 1 B B I O 3 P 1 B B I O 2 P 1 B B I O 1 P 1 B B I O 0 P 0 B B I O 3 P 0 B B I O 2 P 0 B B I O 1 P 0 B B I O 0 P 0 A B I O 3 P 0 A B I O 2 P 0 A B I O 1 P 0 A B I O 0 Register CE pin level judge register Symbol HSYNC counter gate control register HSYNC counter gate judge register Register Symbol PLL refer ence clock select register INTNC mode select ...

Page 69: ... R R W 0 S I O 0 I M D 0 0 S I O 0 I M D 1 0 0 S I O 0 C K 1 S I O 0 C K 0 I R Q S I O 0 I R Q N C R W R W R Serial I O0 mode select register Timer 0 clock select register Interrupt level judge register Serial I O0 wait control register Interrupt edge selection register Serial I O0 status judge register Interrupt enable register Serial I O0 interrupt mode register Serial I O0 clock select register...

Page 70: ...er Base clock setting of basic timer 0 internal external Fixed at 0 Detects the carry flip flop state Fixed at 0 Detects the VSYNC pin state Fixed at 0 Detects the INTNC pin state Fixed at 0 Selects the pulse width of interrupt accept pulse width of the INTNC pin No operation Operation Pulse for timer carry flop flop set 0 10 Hz 100 ms internal 1 200 Hz 5 ms internal 2 10 Hz 100 ms internal 3 200 ...

Page 71: ...0 0 0 CE PLLRFCK3 PLLRFCK2 PLLRFCK1 PLLRFCK0 0 0 0 PLLUL 0 0 PLULSEN1 PLULSEN0 Fixed at 0 Sets the interrupt issue edge VSYNC Fixed at 0 Sets the interrupt issue edge INTNC Serial interface 0 VSYNC signal Basic timer 0 INTNC pin Serial interface 0 VSYNC signal Basic timer 0 INTNC pin Sets the in terrupt permis sion of Sets the in terrupt request of Fixed at 0 Detects the CE pin state Fixed at 1 Fi...

Page 72: ...O3 P0BBIO2 P0BBIO1 P0BBIO0 P0ABIO3 P0ABIO2 P0ABIO1 P0ABIO0 SIO0CH SB SIO0MS SIO0TX SBACK SIO0NWT SIO0WRQ1 SIO0WRQ0 Selects the pin used as an A D converter Detects the comparison result Fixed at 0 Sets I O of port 1C group I O P1B3 pin P1B2 pin P1B1 pin P1B0 pin P0B3 pin P0B2 pin P0B1 pin P0B0 pin P0A3 pin P0A2 pin P0A1 pin P0A0 pin I O setting bit I O Sets the number of communication lines Sets t...

Page 73: ...cts the contents of clock counter Detects the number of clocks I2C bus method Detects the start condition I2C bus method Fixed at 0 Sets the interrupt condition of serial interface 0 Fixed at 0 Fixed at 0 Sets the internal clock of serial interface 0 Controls the HSYNC counter gate Detects open close of the HSYNC counter Fixed at 0 0 0 0 Resets when the contents of the clock counter become 0 or 1 ...

Page 74: ...Function outline Set value 0 1 P o w e r O n S T O P C E IDC IDC DMA enable register IDC CROM bank register IDC enable register 00H R W 30H R W 31H R W 0 0 0 0 0 0 0 0 0 IDCDMAEN CROMBNK IDCEN Fixed at 0 Sets the DMA mode permission Fixed at 0 Fixed at 0 Fixed at 0 Turns the IDC display on off Selects the CROM bank Not permitted Permitted BANK0 0800H 0BFFH BANK1 0C00H 0F7FH Display on Display off ...

Page 75: ...of IDC When the IDCDMAEN flag is set the mode changes to DMA mode and IDC is enabled In DMA mode the instruction cycle is seen as 12 µs For details see Chapter 20 9 2 SP 01H SP is a pointer that addresses the stack register b3 b2 b1 b0 0 SPb2 SPb0 01H 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 SPb1 Level 6 Level 5 Level 4 Level 3 Level 2 Level 1 At reset Not to be set SP stack pointer ...

Page 76: ...tion setting Setting of serial interface clock direction Setting of serial interface mode Setting of serial interface channel 2 wire bus mode CH0 serial I O mode CH1 serial I O mode RX reception mode SI mode P0A3 used as a general purpose port 2 wire bus mode CH0 serial I O mode CH1 serial I O mode TX transmission mode SO mode P0A3 used as an SO pin 2 wire bus mode Serial I O mode Slave operation ...

Page 77: ...etting Internal Internal Internal Internal Internal External Internal External Internal Internal Internal Internal External Internal External Internal Zerocross setting Zerocross off Zerocross on 9 5 BTM0MD 09H 9 6 INTVSYN 0FH b2 The INTVSYN flag is used for reading the vertical synchronous signal level When a high level signal is input to the VSYNC pin the flag is set to 1 When a low level signal...

Page 78: ... INTVSYN INTNC 0FH 0 0 1 0 1 The VSYNC pin is low level The VSYNC pin is in the high level period The INTNC pin is low level The INTNC pin is high level b3 b1 b0 HSCGOSTT 0 12H 0 0 1 b3 b2 b1 b0 HSCGT3 HSCGT2 HSCGT0 11H HSCGT1 0 0 1 1 0 1 0 1 0 b2 Input confirmation of gate open close of horizontal synchronizing signal counter Both bits are fixed at 0 Gate close Gate open Gate open 1 69 ms interva...

Page 79: ...H PLLRFCK1 0 0 1 0 0 0 1 1 0 1 1 0 1 1 1 1 0 1 1 1 1 0 1 0 1 0 1 1 1 1 1 0 6 25 kHz 12 5 kHz 25 kHz PLL disabled Not to be set Reference frequency fr setting Fixed at 1 b3 b2 b1 b0 INTNCMD3 INTNCMD2 INTNCMD0 15H INTNCMD1 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 Edge no noise canceler 200 s 2 ms Setting of INTNC pin acceptance pulse width Fixed at 0 4 ms 400 s µ µ ...

Page 80: ...re bus mode Serial I O mode Does not wait Does not wait Waits when the clock falls with the contents of the clock counter being 8 Waits when the clock falls with the contents of the clock counter being 9 Waits when the clock falls with the contents of the clock counter being 8 after detection of the start condition Waits when the contents of the clock counter become 9 Waits when the contents of th...

Page 81: ...P0D0 ADC3 select shared with P1D1 ADC4 select shared with P0D2 ADC5 select shared with P0D3 No corresponding channel not to be set A D converter input channel select 9 14 A D CONVERTOR CONTROL 21H 9 15 PLL UNLOCK FLIP FLOP JUDGE REGISTER 22H b3 b2 b1 b0 0 0 PLLUL 22H 0 1 0 Detects the unlock flip flop state Unlock flip flop 0 PLL locked Unlock flip flop 1 PLL unlocked ...

Page 82: ...tion Detects the start condition Resets when the contents of the clock counter become 9 Detects the start condition Resets when the contents of the clock counter become 0 or 1 Sets when the contents of the clock counter become 9 Resets when the contents of the clock counter become 0 or 1 Sets when the contents of the clock counter become 8 b3 b2 b1 b0 0 0 P1CGIO 27H 0 1 0 P1C port I O setting P1C1...

Page 83: ...SYN IPNC 2FH 0 1 IPBTM0 0 1 0 1 0 1 Interrupt from the INTNC pin disabled Interrupt from the INTNC pin enabled Interrupt from the clock timer disabled Interrupt from the clock timer enabled Interrupt from the VSYNC pin disabled Interrupt from the VSYNC pin enabled Interrupt from the serial interface disabled Interrupt from the serial interface enabled b3 b2 b1 b0 0 0 CROMBNK 30H 0 1 0 CROM address...

Page 84: ... off IDC operation start display on b3 b2 b1 b0 PLULSEN3 32H 0 0 1 1 0 1 0 1 PLULSEN2 PLULSEN1 PLULSEN0 1 25 to 1 5 s or more 3 5 to 3 75 s or more 0 25 to 0 5 s or more Unlock flip flop disable always set Fixed at 0 Setting of the delay time of the reference frequency fr and divided frequency fN required for setting the unlock flip flop µ µ µ ...

Page 85: ...t b3 b2 b1 b0 P0BBIO3 P0BBIO2 P0BBIO0 36H 0 1 P0BBIO1 P0B0 I O setting 0 1 P0B1 I O setting 0 1 P0B2 I O setting 0 1 P0B3 I O setting P0B0 input port P0B0 output port P0B1 input port P0B1 output port P0B2 input port P0B2 output port P0B3 input port P0B3 output port b3 b2 b1 b0 P1BBIO3 P1BBIO2 P1BBIO0 35H 0 1 P1BBIO1 P1B0 I O setting 0 1 P1B1 I O setting 0 1 P1B2 I O setting 0 1 P1B3 I O setting P1...

Page 86: ... O setting P0A0 input port P0A0 output port P0A1 input port P0A1 output port P0A2 input port P0A2 output port P0A3 input port P0A3 output port b3 b2 b1 b0 SIO0IMD3 SIO0IMD2 SIO0IMD0 38H SIO0IMD1 0 0 0 1 1 0 1 1 Function Fixed at 0 Interrupt request generated at rising edge of the 7th bit of the shift clock Interrupt request generated at rising edge of the 8th bit of the shift clock Interrupt reque...

Page 87: ...interrupt request flag can be read and written by the program Hence if 1 is written an interrupt by software can be generated If 0 is written the interrupt hold status can be released The IRQNC flag becomes 0 upon reset b3 b2 b1 b0 SIO0CK3 SIO0CK2 SIO0CK0 39H SIO0CK1 0 0 0 1 1 0 1 1 100 kHz 200 kHz 500 kHz 1 MHz Fixed at 0 Internal clock frequency Flag name Bit position Interrupt source IRQNC b0 I...

Page 88: ...r is mapped to data memory As shown in Fig 10 1 the data buffer is allocated to addresses 0CH to 0FH of data memory BANK0 and consists of 16 bits in a 4 word 4 bit configuration Because the data buffer is mapped to data memory it can be operated by data memory instructions Fig 10 1 Data Buffer Map 0 1 2 3 4 5 6 7 8 9 A B C D E F Data buffer Data memory BANK0 BANK1 BANK2 System register 7 7 0 1 2 3...

Page 89: ...s Bit b0 of data memory address 0FH is the LSB and bit b3 of data memory address 0CH bit 3 is the MSB Fig 10 2 Data Buffer Structure b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 0CH 0DH 0EH 0FH DBF3 DBF2 DBF1 DBF0 M S B L S B Data memory Address Bit Bit Symbol Data Data buffer Data ...

Page 90: ...ble referencing is described in Section 10 3 and the peripheral hardware is described in Sections 10 4 to 10 6 Fig 10 3 Relationship Between Data Buffer Peripheral Hardware and Memory 01H 02H 03H 04H 05H 08H 40H 41H Peripheral address Data buffer Internal Table referencing Peripheral hardware Image display controller IDC A D converter Serial interface Horizontal synchronizing signal counter 6 bit ...

Page 91: ...le program is given in Section 10 3 2 MOVT DBF AR Reads the contents of the program memory addressed by the address register into the data buffer as shown below When a table reference instruction is executed the stack is used one level Because the address register AR has only eight valid bits program memory available for table reference is limited to 256 steps from address 0000H to address 00FFH S...

Page 92: ...BIO0 SET4 P0BBIO3 P0BBIO2 P0BBIO1 P0BBIO0 MOV RPL 1110B Sets general purpose register to row address 7H of BANK0 MOV AR1 DL DATA SHR 4 AND 0FH MOV AR0 DL DATA SHR 0 AND 0FH Sets address register to 0001H LOOP MOVT DBF AR Transfers the contents of the ROM specified by AR to data buffer LD P0A DBF2 Transfers the contents of data buffer to Port0A 70H LD P0B DBF1 Port0B 71H and Port0C 72H port data re...

Page 93: ... a peripheral address is allocated to each peripheral hardware unit Data transfer between the data buffer and peripheral hardware can be performed by executing a GET or PUT instruction dedicated to the peripheral register for the peripheral register The GET and PUT instructions are described below The peripheral hardware and data buffer functions are listed in Table 10 1 GET DBF p Reads the data o...

Page 94: ...e SIO0SFR 03H PUT GET 8 8 Sets the serial out data shift register and reads the serial in data Horizontal syn HSYNC HSC 04H GET 8 6 Reads the value of the chronizing signal counter data horizontal synchroni counter register zing signal counter PWM0 PWM data PWMR0 05H PUT GET 8 7 Sets the D A converter pin register 0 output signal duty PWM1 PWM data PWMR1 06H Duty D x 0 75 pin register 1 64 PWM2 PW...

Page 95: ...1 At data read the status of this extra data is Unpredictable as shown in Example 2 Example 1 PUT instruction When the valid peripheral register bits are seven bits from bit0 to bit6 When 8 bit data is written to a peripheral register the status of the eight high order bits of the data buffer contents of DBF3 and DBF2 is Don t care Of the 8 bit data in the data buffer the status of each bit that d...

Page 96: ...dictable is decided in advance for each peripheral register 10 4 3 State at Peripheral Register Reset The valid bits of each peripheral register are reset as follows DBF3 DBF2 DBF1 DBF0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Peripheral register b7 b6 b5 b4 b3 b2 b1 b0 GET Data buffer 8 Don t care Don t care 0 or unpredictable 0 or unpredictable The value of the peripheral register i...

Page 97: ...on Fig 10 4 IDC Start Position Register Functions DBF3 0CH DBF2 0DH DBF1 0EH DBF0 0FH b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 D7 D6 D5 D4 D3 D2 D1 D0 IDCORG 01H Symbol Peripheral address Peripheral hardware IDC display position setting Name Peripheral register Name Data buffer Symbol Address Bit Data Don t care Don t care Transfer data GET PUT IDC start positi...

Page 98: ...are valid Fig 10 5 A D Converter Data Register Functions DBF3 0CH DBF2 0DH DBF1 0EH DBF0 0FH b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 0 ADCR 02H A D converter comparison voltage VREF setting 0 0 0 0 1 x 15 8 VREF 0 V Fixed at 0 VREF VDD V x 0 5 15 A D converter Symbol Peripheral address Peripheral hardware Name Peripheral register Name Data buffer Symbol Addres...

Page 99: ...rial data input data is shifted sequentially from the LSB bit b0 DBF3 0CH DBF2 0DH DBF1 0EH DBF0 0FH b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 D7 D6 D5 D4 D3 D2 D1 D0 SIO0SFR 03H Serial out data write and serial in data read 1 2 3 4 5 6 7 8 MSB LSB Data output timing D7 D6 D5 D4 D3 D2 D1 D0 1 2 3 4 5 6 7 8 MSB LSB Data input timing D7 D6 D5 D4 D3 D2 D1 D0 8 Symb...

Page 100: ...H at the next input Fig 10 7 HSYNC Data Register Functions DBF3 0CH DBF2 0DH DBF1 0EH DBF0 0FH b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 HSC 04H 0 0 8 Horizontal synchronizing signal count Symbol Peripheral address Peripheral hardware Name Peripheral register Name Data buffer Symbol Address Bit Data Don t care Don t care Transfer data GET HSYNC counter data regi...

Page 101: ...H DBF1 0EH DBF0 0FH b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 0 PWMR0 05H Set the PWM output duty of each pin 0 x 63 8 Use PWM pins as D A converter Duty D x 0 75 64 PWM0 pin PWM0 data register PWMR1 06H 0 PWM1 pin PWM1 data register PWMR2 07H 0 PWM2 pin PWM2 data register PWMR3 08H 0 PWM3 pin PWM3 data register 0 0 Use PWM as 1 bit output pin Output contents of...

Page 102: ...ata memory operation instructions Fig 10 9 shows the relationship between the address registers and the data buffer Fig 10 9 Relationship Between Address Registers and Data Buffer DBF3 0CH DBF2 0DH DBF1 0EH DBF0 0FH b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 0 AR 40H Address register data write and read 0 0 0 0 F 16 Address register b15 b14 b13 b12 b11 b10 b9 b8 ...

Page 103: ...et in the swallow counter Fig 10 10 PLL Data Register DBF3 0CH DBF2 0DH DBF1 0EH DBF0 0FH b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 PLLR 41H PLL frequency synthesizer frequency division ratio 16 b15 b14 b13 b12 b11 b10 b9 b8 256 0100H x 0 0000H 216 1 0FFFFH Not to be set Frequency division ratio N N x PLL frequency synthesizer Symbol Peripheral address Periphera...

Page 104: ...returns an unpredictable value Writing to an unused address does not change its contents 2 When using an assembler An instruction that reads from a write only register generates an error An instruction that writes to a read only register generates an error An instruction that reads from or writes to an unused address generates an error 3 When using an emulator used to execute instructions by batch...

Page 105: ...eripheral addresses are predefined in the assembler as reserved words Therefore if reserved words are used a program can be written without performing symbol definition as shown in Example 3 The reserved words of peripheral registers are shown in the Symbol field in Table 10 1 and the Symbol field in Figs 10 4 to 10 10 Example 1 PUT 02H DBF The assembler does not generate an error if peripheral GE...

Page 106: ...ocks control interrupt requests from the INTNC pin timer VSYNC pin and serial interface The interrupt enable flip flop INTE sets all interrupt permissions The stack pointer address stack register program counter and interrupt stack are controlled when an interrupt is accepted The interrupt request processing block in the peripheral hardware consists of the IRQ flip flop IP flip flop and vector add...

Page 107: ...Z I X E System register Symbol Address Bit Program counter Address stack register ASR0 ASR1 ASR5 Control register IPSIO0 IRQSIO0 VAG 01H IPVSYN IRQVSYN VAG 02H IPBTM0 IRQBTM0 VAG 03H IPNC IRQNC VAG 04H Flag symbol Name Interrupt request INTREQ Interrupt permission INTPM Stack pointer SP Address Bit Serial inter face VSYNC pin Timer INTNC pin Stack pointer Flag symbol Interrupt stack Interrupt requ...

Page 108: ...rdware There are four peripheral hardware interrupt functions the INTNC pin timer VSYNC pin and serial interface Interrupt request issuance conditions can be set for each type of peripheral hardware For example the request issuance timing for the INTNC pin rising or falling edge of the signal applied to the INTNC pin can be selected See Sections 11 3 to 11 7 for details of interrupt request issuan...

Page 109: ...control register they are read and written via the window register These flags are reset to 0 at power on reset clock stop or CE reset 11 2 5 Vector Address Generator VAG When interrupts from various types of peripheral hardware are accepted the vector address generator generates the branch address vector address of the program memory for the source of the accepted interrupt Table 11 1 lists the v...

Page 110: ...pointer specifies one of six address stack registers ASR0 to ASR5 to be used In other words when an interrupt is accepted the stack pointer value is reduced by 1 and the program counter value is saved in the address stack register indicated by the stack pointer Next if exclusive return instruction RETI is executed after the interrupt processing routine the contents of the address stack register in...

Page 111: ...nput to the interrupt request block via an AND circuit as shown in Fig 11 1 The interrupt request flag is reset by the signal input to each interrupt request block and the vector address for each interrupt is output If a 1 is output from the interrupt request block at this time the interrupt acceptance signal is not transferred to the next level If two or more interrupt requests are issued togethe...

Page 112: ...o yes Yes No Yes No Yes No IRQNC IPNC 1 IRQBTM0 IPBTM0 1 IRQVSYN IPVSYN 1 IRQSIO0 IPSIO0 1 No Yes Interrupt request No Yes Interrupt request No Yes Interrupt request No Yes Interrupt request No Yes IRQNC setting IRQBTM0 setting IRQVSYN setting IRQSIO0 setting EI state Interrupt acceptance IRQNC resetting IRQBTM0 resetting IRQVSYN resetting IRQSIO0 resetting ...

Page 113: ... flip flop is set in the instruction cycle after the cycle in which the EI instruction is executed Fig 11 3 2 shows the timing chart when two or more interrupts are used If all interrupt permission flags are set when two or more interrupts are used the interrupt with the highest hardware priority is accepted first The program can be used to change the interrupt permission flags to change the hardw...

Page 114: ...en an interrupt holding period is set by the interrupt permission flag Instruction EI MOV WR 0001B POKE INTPM WR INTE INTNC pin IRQNC flag IPNC flag Interrupt acceptance Normal instruction Interrupt cycle or 12 s 1 instruction cycle 2 s Interrupt permission period Interrupt processing routine µ µ Instruction EI MOV WR 0001B POKE INTPM WR INTE INTNC pin IRQNC flag IPNC flag Interrupt processing rou...

Page 115: ...YNC pin interrupt acceptance INTNC pin interrupt holding period INTNC pin interrupt processing VSYNC pin interrupt processing VSYNC pin interrupt holding period INTNC pin interrupt acceptance Instruction EI MOV WR 0100B POKE INTPM WR INTE INTNC pin IRQNC flag IPNC flag EI IPVSYN flag IRQNC flag VSYNC pin MOV WR 0101B POKE INTPM WR INTNC pin interrupt holding period VSYNC pin interrupt acceptance I...

Page 116: ...to the accepted interrupt are transferred to the program counter In other words processing is branched to the interrupt processing routine The processing in 1 to 5 above is executed during one special instruction cycle 2 µs or 12 µs when the IDC is operating without normal instruction execution This instruction cycle is called the interrupt cycle The processing from interrupt acceptance to branchi...

Page 117: ...he contents of a register when the row address of the general purpose register is not defined at interrupt acceptance the data memory address is hard to specify If the general purpose register address is not defined when the transfer instruction is used to save the contents of the general purpose register the address to be saved also becomes undefined In this case use of the general purpose regist...

Page 118: ...egisters and index enable flags are reset to 0 after being saved in the interrupt stack 2 Data saved by software Data saved by software is not reset after being saved Program status words such as the BCD flag compare flag carry flag zero flag and memory pointer enable flags keep their preacceptance values Initialize these program status words if necessary ...

Page 119: ...nts of saved system registers Interrupt reception Interrupt processing Saves the contents of the window register in M048 Saves the contents of the general purpose register pointer in M04E Sets row address 7 of bank 0 in the general purpose register Saves the contents of required system registers Saves the contents of the required control register Restores the contents of the saved control register...

Page 120: ...gister Numbers to correspond to the numbers in the program example 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 BANK0 POKE M048 WR AR1 AR0 WR RPL BTM0CK 0 1 2 3 Column address Data memory Save area Control register Register file Row address Specify the general purpose register ...

Page 121: ...rupt edge selection register INTEDGE address 1FH of the control register The INTNC latch and INTVSYN latch correspond to the INTNC flag and INTVSYN flag respectively in the interrupt pin level judge register INTJDG address 0FH of the control register The Schmitt triggers at the INTNC and VSYNC inputs prevent pulses operations due to noise These pins do not accept pulses of 1 µs or less A minimum p...

Page 122: ...s an interrupt request See Section 11 2 for operations after interrupt request issuance Because the signals input to the INTNC and VSYNC pins are input to the INTNC and INTVSYN latches as shown in Fig 11 5 the input signal levels can be detected by reading the INTNC and INTVSYN flags Because the INTNC and INTVSYN flags are set or reset regardless of interrupts they can be used as 2 bit general pur...

Page 123: ...are two types of internal interrupts the timer interrupt and the serial interface interrupt 11 8 1 Timer Interrupt The timer interrupt function can issue interrupt requests at a specified time interval An interval of 100 ms 20 ms or 5 ms can be selected See Chapter 12 for details 11 8 2 Serial Interface Interrupt The serial interface interrupt function can issue an interrupt request when a serial ...

Page 124: ...time is called the interrupt level Note the following regarding the multiple interrupt function 1 Interrupt source priorities 2 Interrupt level restriction by an interrupt stack 3 Interrupt level restriction by the address stack register 4 System or control register saving See Sections 11 9 1 to 11 9 4 for details Fig 11 6 Example of Multiple Interrupts MAIN B D A B C Interrupt level 2 Main routin...

Page 125: ... not determined several interrupts from B will not be executed Because an interrupt is generally used for emergency processing the A B priority should be set in the program to prevent interrupt A while interrupt B is being processed and accept interrupt B while interrupt A is being processed When using the multiple interrupt function for non emergency purposes priorities need not be determined How...

Page 126: ...9 At interrupt stack the device operation is the sweep off type and the emulator operation is the rotation type Use the RET instruction as the last restoration instruction when using multiple interrupts of more than two levels RETI and RET instructions operate in the same manner except when restoring the contents of the interrupt stack ...

Page 127: ...AIN MAIN Interrupt B Interrupt stack Undefined Main routine Interrupt A Interrupt stack Undefined Undefined MAIN A MAIN B A C B A MAIN B A A A RETI RETI RETI A A A A If control is returned to the main routine at this time BANK and IXE of interrupt A are restored and the main routine operates abnormally Undefined Undefined Main routine Interrupt A Interrupt B Interrupt C Undefined ...

Page 128: ...ndex enable flag BANK0 and IXE 0 in this example in the main routine that permits interrupt A This processing enables the use of RET instructions for multiple interrupts of three levels after specifying the bank register and index enable flag of the main routine If the bank register and index enable flag at interrupt A are exactly the same as those of the main routine the RETI instruction can be u...

Page 129: ...is Used If the RETI instruction is used on the emulator the contents of the bank register and index enable flag of interrupt B are restored MAIN MAIN A B A C B A MAIN B B B B RETI RETI RET A A A A Undefined Undefined Main routine Interrupt A Interrupt B Interrupt C Undefined ...

Page 130: ...ling only two levels of the multiple interrupts shown in Fig 11 10 can be used Fig 11 10 Address Stack Register Operation ASR0 ASR1 ASR2 ASR3 ASR4 ASR5 ASR6 ASR7 Undefined Undefined Undefined Undefined Undefined MAIN Undefined Undefined Undefined Undefined SUB1 MAIN Undefined Undefined Undefined SUB2 SUB1 MAIN Undefined Undefined SUB3 SUB2 SUB1 MAIN Undefined AAA SUB3 SUB2 SUB1 MAIN SUB4 AAA SUB3 ...

Page 131: ... figure below shows an example program and flowchart for this processing Flowchart Program example EI RETI EI EI DI MOV POKE BANK1 POKE PEEK POKE MOV POKE PEEK POKE PEEK POKE PEEK POKE PEEK WR INTPM 0111B WR WR INTPM WR 0100B WR WR M3 WR INTPM M2 WR M1 WR INTPM WR M3 WR RPL WR M1 WR M2 WR INTPM VSYNC INTNC and timer interrupt permission built in macro Bank specification Window register saving Inte...

Page 132: ...ed control should be returned with the INTNC pin interrupt inhibited In permit VSYNC interrupt with a lower priority than the timer interrupt Then use the EI instruction to permit all interrupts Because processing in and must be executed with an interrupt inhibited the VSYNC interrupt with the highest priority is also inhibited during this processing In and save and restore the contents of the sys...

Page 133: ... Fig 12 1 12 1 2 Timer Interrupt Block Configuration The timer interrupt block consists of selector B an interrupt control block an interrupt permission register INTPM at address 2FH which is a control register and an interrupt request register INTREQ at address 3FH as shown in Fig 12 1 Fig 12 1 Timer Configuration 09H 2FH 3FH 17H b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 B T M 0 Z X B T M 0...

Page 134: ...ster The timer mode select register is used to specify the time base mode internal timer mode or external timer mode for selectors A and B The internal timer mode uses pulses generated by dividing the device s operating frequency 8 MHz The external timer mode uses 50 or 60 Hz supplied at the P0B2 TMIN pin The timer mode select register is again used to specify whether to divide the frequency of th...

Page 135: ... 200 Hz 50 Hz fTMIN 6 Hz 10 Hz fTMIN 5 Hz Control register Register Address Bit Flag symbol Timer mode select BTM0CK Selection of frequency time of the timer carry FF set pulse Selection of frequency time of the timer interrupt pulse Internal timer Internal timer Internal timer Internal timer External timer Internal timer External timer Internal timer Internal timer Internal timer Internal timer I...

Page 136: ... a program used to read the BTM0CY flag When using the timer carry FF observe the following point A power on reset disables the timer carry FF from being bet It cannot be set until the PEEK instruction is issued to read the content of the BTM0CY flag 0 is read in when the BTM0CY flag is read accessed for the first time after a power on reset Once it is reset the timer carry FF is set to 1 at inter...

Page 137: ...NEXT Process B Performs process B and branches to LOOP BR LOOP This program performs process A at intervals of one second Note the following point 1 when creating this program 1 The time interval at which the BTM0CY flag is checked must be less than the time interval at which the timer carry FF is set to 1 This is because if it takes 100 ms or longer to perform process B it is impossible to detect...

Page 138: ...ked is tCHECK and the time interval 100 ms or 5 ms at which timer carry FF is set is tSET The relationship between these two intervals must be as follows tCHECK tSET Under this condition as shown in Fig 12 4 the timer error that depends on the timing when the BTM0CY flag is checked is as follows 0 error tCHECK Fig 12 4 Timer Error That Depends on the Time Interval at Which the BTM0CY Flag Is Check...

Page 139: ...INITFLG NOT BTM0ZX NOT BTM0CK2 NOT BTM0CK1 NOT BTM0CK0 Built n macro Process A Specifies the timer carry FF set pulse as 10 Hz 100 ms SET1 BTM0CK0 Built in macro Specifies the timer carry FF set pulse as 200 Hz 5 ms Process A CLR1 BTM0CK0 Built in macro Specifies the timer carry FF set pulse as 10 Hz 100 ms With this coding the timer carry FF set pulse is switched as shown below SET1 BTM0CK0 CLR1 ...

Page 140: ... about the phase difference of each pulse Fig 12 5 Timer Error That Occurs When the Timer Carry FF Setting Time Interval Is Switched from A to B a Timer error of tSET b Timer error of tCHECK tSET tSET 0 SKT1 BTM0CY Internal pulse A Internal pulse B Timer carry FF set pulse BTM0CY flag True timer interval Actual timer interval Time interval switched here If the BTM0CY flag is checked right after th...

Page 141: ...o update the timer and the time interval at which the BTM0CY flag is checked must be less than the timer carry FF setting time interval 2 If a created program needs a timer that operates at constant intervals regardless of a CE reset once a power on reset occurs the program must correct the timer at each CE reset 3 A check of the BTM0CY flag takes precedence over a reset sync signal for a CE reset...

Page 142: ...imer update process time tSET Time interval at which the timer carry FF is set An example follows Example Timer update process and BTM0CY flag check time interval START Program address 0000H INITFLG NOT BTM0ZX NOT BTM0CK2 NOT BTM0CK1 NOT BTM0CK0 Built in macro Specifies the timer carry FF setting time interval as 100 ms TIMER SKT1 BTM0CY flag Built in macro Tests the BTM0CY flag BR AAA Branches to...

Page 143: ...ent must continue to operate even at a CE reset Reading the BTM0CY flag for a power failure check could reset the BTM0CY flag to 0 thus losing a chance of detecting a set 1 state of the flag To skirt the above problem it is necessary to update the timer for time measurement at a CE reset that occurs because of power failure See also Section 14 6 for details about a power failure check Example Corr...

Page 144: ...gram at 0000H When the BTM0CY flag is checked at point E a backup CE reset is detected because the BTM0CY flag is already set to 1 As seen from the timing chart if the clock is not updated by 100 ms at point E the clock loses 100 ms each time a CE reset occurs If process A power failure check takes longer than 100 ms at point E the program loses twice a chance of detecting when the BTM0CY flag is ...

Page 145: ...uction cycle is 2µs 1 500 kHz a program that checks the BTM0CY flag once at every 500 instructions reads the BTM0CY flag at every 1 ms 2µs 500 Under this condition whichever timer interval set pulse 5 ms or 100 ms is selected a CE reset will not occur for ever once the setting and checking of the BTM0CY flag occur at the same time To be specific avoid creating a cyclic program that satisfies the f...

Page 146: ...steps BR LOOP Because the BTM0CY flag read instruction at in this program is executed at every 500 instructions once the BTM0CY flag happens to be set at the timing of the instruction at a CE reset will not occur forever In addition because the instruction execution time is 12µs 1 83 33 kHz during the operation of the IDC do not create a cyclic program that meets the following condition tSET 83 33...

Page 147: ...nship Between the Timer Interrupt Pulse and the IRQBTM0 Flag IRQBTM0 IPBTM0 INTE FF EI DI Timer interrupt pulse The negative going edge of the timer interrupt pulse sets the IRQBTM0 flag The EI instruction is executed but the interrupt request is not accepted because the IPBTM0 flag is not set The timer interrupt request is accepted at the same time the IPBTM0 flag is set Timer interrupt request a...

Page 148: ...imer interrupt pulse as 5 ms MOV M1 0000B Clears the content of M1 to 0 SET1 IPBTM0 Enables a timer interrupt EI Enables all types of interrupts LOOP Process B BR LOOP This program performs process A at every 80 ms At this point note the following Accepting an interrupt request causes a DI state automatically and the IRQBTM0 flag is set to 1 even in the DI state In other words if process A takes 5...

Page 149: ... flag occurs These timer error types are illustrated in Fig 12 9 Fig 12 9 Timer Interrupt Error 1 2 a When a timer interrupt is enabled IRQBTM0 IPBTM0 INTE FF EI DI tSET EI EI EI SET1 IPBTM0 Timer interrupt pulse Interrupt pending Interrupt request accepted Interrupt request accepted Interrupt request accepted At point an interrupt request is accepted immediately when the IPBTM0 flag is set to ena...

Page 150: ...ow Therefore an interrupt occurs when the interrupt pulse goes low at point When the timer interrupt pulse is switched to A at point the timer interrupt pulse goes low and the interrupt request is accepted immediately c When the IRQBTM0 flag is manipulated EI EI EI IRQBTM0 IPBTM0 INTE FF EI DI Timer interrupt pulse Interrupt accepted SET1 IRQBTM0 Interrupt accepted CLR1 IRQBTM0 No interrupt accept...

Page 151: ...BTM0CK1 NOT BTM0CK0 Built in macro Specifies the timer interrupt time and timer carry FF setting time interval as 250 and 100 ms respectively SET1 IPBTM0 Built in macro EI Enables the timer interrupt Process A BR AAA The program in this example performs the clock process at every one second while performing process A If the CE pin goes from a low to a high as shown in Fig 12 10 a a CE reset occurs...

Page 152: ...t Fig 12 10 Timing Chart a b CE pin Timer carry FF set pulse Timer interrupt pulse Timer interrupt Because the timer carry FF set pulse goes high a CE reset occurs here thus skipping detection of a timer interrupt once CE pin Timer carry FF set pulse Timer interrupt pulse Timer interrupt Timer interrupt Delay 10 ms in this case CE reset Because there is a delay of 10 ms between the negative going ...

Page 153: ...imer carry FF and the P0D0 ADC2 to P0D3 ADC5 pins It controls the operation of the CPU program counter instruction decoder and ALU block The clock stop control block controls the 8 MHz crystal oscillator CPU system register and control register Fig 13 1 Standby Block Configuration ALU Halt block Interrupt block Timer carry FF Halt control circuit HALT h P0D3 ADC5 pin P0D2 ADC4 pin P0D1 ADC3 pin P0...

Page 154: ...urrent drain The clock stop function uses a dedicated instruction STOP s instruction to stop the 8 MHz crystal oscillator in order to reduce the current drain in the device To use these functions it is necessary to specify a device operation mode at the CE pin Section 13 3 explains the device operation mode specified at the CE pin Sections 13 4 and 13 5 describe the halt and clock stop functions R...

Page 155: ... Driving the CE pin from a low to a high can reset the device CE reset There is another type of reset which is a power on reset It occurs when supply voltage VDD is turned on See Chapter 14 for details 13 3 3 Signal Inputs to the CE Pin The CE pin does not accept a high or low level with a duration of less than 187 5 µs to prevent malfunction due to noise The input level of a signal supplied to th...

Page 156: ...the timer carry FF interrupt and key entry The operand h of the HALT h instruction specifies a condition timer carry FF interrupt or key entry to release the halt state The HALT h instruction is always effective regardless of the input level at the CE pin Sections 13 4 1 to 13 4 5 explain the halt state and halt release conditions 13 4 1 Halt State The CPU is entirely at a stop in the halt state I...

Page 157: ... is reset If the operand h is 0000B no halt release condition is specified Under this condition the halt state is released by resetting power on or CE reset the device Sections 13 4 3 to 13 4 6 explain the timer carry FF interrupt and key entry as halt release conditions Fig 13 3 Halt Release Conditions b3 b2 b1 b0 0 1 HALT h 4 bits Operand bits Specify a condition to release the halt state The ha...

Page 158: ...ons in using a general purpose output port as a key source signal P0D3 ADC5 P0D2 ADC4 P0D1 ADC3 P0D0 ADC2 Latch Switch A General purpose output port The HALT 0001B instruction must be executed after the general purpose output port for key source signal input is raised to a high If an alternate switch like switch A in the above figure is used a high level is always applied to the P0D0 ADC2 pin when...

Page 159: ...t is disconnected from the input latch and connected to the internal A D converter input If a pin happens to be at a high level when it is selected for an A D converter the latch circuit is held at a high If the HALT 0001B instruction is executed under the above condition the halt state is released immediately because the input latch is at a high To solve the above problem specify the input port s...

Page 160: ...t port Latch Microprocessor or the like General purpose output port The P0D0 ADC2 to P0D3 ADC5 pins can be used a general purpose input port with a built in pull down resistor This configuration of the P0D0 ADC2 to P0D3 ADC5 pins enables a microprocessor to be used to release the halt state as shown above ...

Page 161: ... can therefore release the halt state at constant intervals An example of using the HALT 0010B instruction follows Example HLTTMR DAT 0010B Defines a symbol INITFLG NOT BTM0ZX NOT BTM0CK2 NOT BTM0CK1 NOT BTM0CK0 Built in macro Specifies the timer carry FF setting time interval as 100 ms LOOP1 MOV M1 0110B LOOP2 HALT HLTTMR Specifies the timer carry FF as a halt release condition SKT1 BTM0CY Built ...

Page 162: ...errupt request to be accepted besides issuing the interrupt request it is necessary to enable all interrupts EI instruction and the interrupt that corresponds to the issued interrupt request to set the interrupt permission flag If interrupts are not enabled no interrupt request is accepted and therefore the halt state is not released even if an interrupt request is issued If an interrupt request i...

Page 163: ...is sample program releases the halt state and performs process B when a timer interrupt request is accepted When an interrupt request at the INTNC pin is issued the program performs process A It also performs process C each time the halt state is released If an INTNC pin interrupt is requested exactly at the same time with a timer interrupt during the halt state the program performs process A for ...

Page 164: ...top state and cautions to be taken in using the clock stop instruction 13 5 1 Clock Stop State In the clock stop state all operations of the device including CPU and peripheral hardware operations are stopped because the crystal oscillator stops During the clock stop state the power failure detector does not operate even if the supply voltage VDD is lowered to about 2 2 V This makes possible a low...

Page 165: ...on is not used operation is as follows 0 tSET Program starts at address 0 CE reset CE reset is applied in synchronization with the setting of the timer carry FF after the CE pin has been raised to high level 5 V 0 V VDD CE pin Crystal oscillation XOUT pin STOP 0 instruction Approx 50 ms Program starts at address 0 CE reset 5 V 0 V VDD CE pin Clock oscillation XOUT pin If a clock stop instruction i...

Page 166: ...at If the CE pin is at a low the clock stop instruction STOP XTAL at is executed after process A is finished If the CE pin goes high during execution of the STOP XTAL instruction at as shown below the STOP XTAL instruction is treated as a no operation NOP If the program does not contain the branch instruction BR 1 at program control is passed to the main process possibly resulting in a malfunction...

Page 167: ...ied in the control register during the halt state During the clock stop state however the peripheral hardware operates according to the initial value set in the control register See Chapter 9 for the initial value for the control register Let s study the following example Example When the P0A0 SDA and P0A1 SCL pins of port 0A are specified as output ports and the P0A2 SCK and P0A3 SO pins are used...

Page 168: ...e State CE pin low level Halt Clock stop Clock stop Halt CE pin high level Program counter System register Peripheral hardware register Control register Timer A D converter D A converter Serial interface General purpose input output port General purpose input port General purpose output port IDC Initialized to 0000H and stops InitializedNote Holds the previous state InitializedNote Stops operating...

Page 169: ...ally during high level output or pulled up during low level output the current drain will increase The state that exists before the execution of the halt instruction continues 1 When the port is specified as output If the pin pulled down externally during high level output or pulled up externally during low level output the current drain increases Be careful especially for N channel open drain out...

Page 170: ...essary to take the same cautions as for the general purpose output port The pin becomes floating The current drain varies with the waveform of the oscillation output of the clock oscillator The larger the amplitude the current drain becomes lower The oscillation amplitude of the oscillator varies depending on its crystal and load capacitance evaluation is required The IDC is disabled Each pin beha...

Page 171: ...failure detection circuit and a reset control circuit The CE reset block consists of a circuit that detects the rising edge of the signal input to the CE pin and a reset control circuit Fig 14 1 Reset Block XOUT XIN VDD CE Power on clear signal POC Reset signal IRES RES RESET STOP instruction R S Q Selector Timer carry FF Timer FF block Power failure detection block Scaler BTM0CY flag read STOP in...

Page 172: ...ed by reset signals IRES RES and RESET output from the reset control circuit in Fig 14 1 Table 14 1 shows the IRES RES and RESET signal and power on reset and CE reset relationship The reset control circuit also operates when the clock stop instruction STOP described in Chapter 13 is executed Sections 14 3 and 14 4 describe CE reset and power on reset respectively Section 14 5 describes the relati...

Page 173: ...ely Section 14 3 3 describes the cautions at CE reset 14 3 1 CE Reset When Clock Stop STOP Instruction Not Used Fig 14 2 shows the reset operation When clock stop STOP instruction is not used the timer mode selection register of the control registers is not initialized Therefore after the CE pin becomes high level the RESET signal is output and reset is applied at the rising edge of the timer carr...

Page 174: ...he clock itself stops the device stops operating When the CE pin rises to high level the clock stop state is released and oscillation begins The IRES signal halts release by timer carry FF When the timer carry FF set pulse rises after the CE pin rises the halt state is released and the program starts from address 0 Since the timer carry FF set pulse is initialized to 100 ms CE reset is applied 50 ...

Page 175: ...low Example 1 LCTUNE Initial reception The last channel is received The channel indicated by the contents of M1 and M2 is received MAIN Main processing Channel change The changed channel is assigned to general purpose registers R1 and R2 ST M1 R1 The last channel is rewritten ST M2 R2 BR MAIN In this example if the last channel is 12H then the data memory contents of M1 and M2 will be 1H and 2H re...

Page 176: ... by the contents of M1 and M2 is received MAIN Main processing Channel change The changed channel is assigned to general purpose registers R1 and R2 SET1 FLG1 FLG1 is set while rewriting the last channel ST M1 R1 The channel is rewritten ST M2 R2 CLR1 FLG1 BR MAIN In this example FLG1 is set when rewriting the last channel in and This allows data to be rewritten in again even if CE reset is applie...

Page 177: ...F set signal Since the RESET signal has initialized the timer carry FF set signal to 100 ms 50 ms after VDD exceeds the power on clear voltage reset is applied and the program starts from address 0 This operation is shown in Fig 14 4 At power on reset the program counter stack system register and control registers are initialized when the power on clear signal is output For the initial values see ...

Page 178: ...on Reset in Clock Stop State Fig 14 5 b shows power on reset in the clock stop state As shown in Fig 14 5 b when VDD drops below 2 2 V the power on clear signal is output and device operation stops However since the device is in the clock stop state its operation apparently does not change When VDD rises to 3 5 V or greater after a 50 ms halt the program starts from address 0000H 14 4 3 Power on R...

Page 179: ...address 0 Halt state 50 ms Power on clear voltage 3 5 V 5 V Clock stop Device operation stopped XOUT VDD CE Power on clear signal Power on clear release Oscillation start Power on reset Program starts from address 0 Halt state 50 ms 2 2 V Power on clear voltage 3 5 V STOP 0000B Normal operation L 5 V 0 V Device operation stopped XOUT VDD CE Power on clear signal Power on clear release Oscillation ...

Page 180: ...imultaneously Fig 14 6 a shows the reset operation Power on reset starts the program from address 0000H 14 5 2 When CE Pin Raised in Forced Halt State Caused by Power on Reset Fig 14 6 b shows the reset operation Power on reset starts the program from address 0000H as inSection 14 5 1 14 5 3 When CE Pin Raised after Power on Reset Fig 14 6 c shows the reset operation Power on reset starts the prog...

Page 181: ...on reset Program start Power on clear voltage 3 5 V Halt state 50ms Normal operation Timer carry FF set pulse 5 V 0 V VDD CE Power on reset Program start Power on clear voltage 3 5 V Halt state 50 ms Normal operation Timer carry FF set pulse Opera tion stopped 0 V VDD CE Timer carry FF set pulse Power on reset Program start Power on clear voltage 3 5 V Halt state 50 ms Normal operation CE reset Pr...

Page 182: ...l continues to be output and the program does not run Since the device output port outputs an undefined value the supply current increases according to the situation reducing the back up time with a battery considerably Fig 14 7 Caution When VDD Raised 5 V 0 V Operation stopped XOUT VDD CE Power on clear signal Timer carry FF set pulse 3 5 V 2 2 V Opera tion stopped Halt state 50 ms Normal operati...

Page 183: ... or greater at this time power on reset is applied The same caution is necessary when VDD is dropped Fig 14 8 Return from Clock Stop State 5 V 0 V XOUT VDD CE Power on clear signal Timer carry FF set pulse 3 5 V 2 2 V CE low processing Normal operation Back up Back up caused by clock stop Power on clear voltage Halt state 50 ms CE reset Program start STOP 0000B At this point the power on clear vol...

Page 184: ...0CY flag is not set to 1 That is when the power on clear signal is output at power on reset the program starts in the state in which the BTM0CY flag is reset and the setting disabled state is set until a BTM0CY read instruction is executed thereafter Once a BTM0CY read instruction is executed the BTM0CY flag is set at each rising edge of the timer carry FF set pulse thereafter When reset is applie...

Page 185: ...r on reset Normal operation CE reset Rising edge of timer carry FF set pulse Clock stop BTM0CY flag setting disabled state Normal operation Normal operation CE reset wait Clock oscillation start Forced halt 50 ms SKT1 BTM0CY or SKF1 BTM0CY SKT1 BTM0CY or SKF1 BTM0CY Normal operation CE reset Rising edge of timer carry FF set pulse Clock stop Normal operation Normal operation CE reset wait Clock os...

Page 186: ...r failure detected with BTM0CY flag 5 V 0 V VDD CE Timer carry FF set pulse BTM0CY Fig 14 12 operation Timer time switching STOP 0000B 5 V 0 V VDD CE Timer carry FF set pulse BTM0CY SKT1 BTM0CY instruction Timer time switching STOP Fig 14 12 operation 1 0 3 1 0 4 1 BTM0CY 0 Power failure BTM0CY 1 No power failure BTM0CY 1 No power failure 2 2 ...

Page 187: ...g point 3 Power failure detection timing When clock counting etc is performed with the BTM0CY flag the flag must be read for power failure detection before the next rising edge of the timer carry FF set pulse after a program starts from address 0000H This is because when the timer carry FF set time is set to 5 ms for instance and power failure detection is performed 6 ms after the program starts o...

Page 188: ...SKT1 BTM0CY BR MAIN Clock updating Operation example 5 V 0 V VDD CE Timer carry FF set pulse 50 ms 50 ms Power failure detection Power failure detection CE reset CE reset When the processing time of is too long a CE reset is applied When the processing time of is 100 ms or longer a CE reset is applied midway through processing CE reset may be applied immediately depending on the timer carry FF set...

Page 189: ...eneral purpose port pins For example Port0A consists of pin P0A3 to pin P0A0 As stated in Table 15 1 general purpose ports are classified into I O shared ports I O ports input only ports input ports and output only ports output ports I O ports are classified into bit I O ports which allow I O to be specified in 1 bit 1 pin units and group I O ports in which I O can be specified in 3 bit 3 pin unit...

Page 190: ...General purpose ports Classification of general purpose ports Target ports Data setting method I O shared port Bit I O Port0A Port register Port0B Port1B Group I O Port1C Port register Input only port Port0D Port register Output only port Port0C Port register Port1A ...

Page 191: ... independently according to the contents of the corresponding control register Sections 15 2 1 to 15 2 4 describe the functions of the port register and outline the functions of each port 15 2 1 General Purpose Port Data Register Port Register The port register sets output data for each general purpose port and reads input data Since the port register is mapped into data memory it can be manipulat...

Page 192: ...et by P0B data memory address 71H of BANK0 or BANK2 of the port register The I O data of P1B is set by P1B data memory address 71H of BANK1 of the port register And the I O data of P1C is set by P1C data memory address 72H of BANK1 of the port register See Table 15 2 For details see Section 15 3 15 2 3 General Purpose Input Port P0D P0D input data is read by P0D data memory address 73H of BANK0 or...

Page 193: ...B3 P1B2 P1B1 P1B0 P1C3 P1C2 P1C1 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 P0A3 P0A2 P0A1 P0A0 P0B3 P0B2 P0B1 P0B0 P0C3 P0C2 P0C1 P0C0 P0D3 P0D2 P0D1 P0D0 P1A3 P1A2 P1A1 P1A0 P1B3 P1B2 P1B1 P1B0 P1C3 P1C2 P1C1 70H 71H 72H 73H 70H 71H 72H P0A P0B P0C P0D P1A P1B P1C BANK0 BANK2 BANK1 Port Symbol I O Pin Data setting method Port register data memory Bank Add...

Page 194: ...I O of the bit I O port P0A P0B P1B can be set in 1 bit 1 pin units I O of the group I O port P0C can be set in 3 bit 3 pin units Output data is set and input data is read when a data write instruction or data read instruction is executed in the corresponding port register Section 15 3 3 describes the I O selection register of each port Sections 15 3 4 and 15 3 5 explain the use of an input port a...

Page 195: ...O 3 P 1 B B I O 2 P 1 B B I O 1 P 1 B B I O 0 b3 b2 b1 b0 P 0 B B I O 3 P 0 B B I O 2 P 0 B B I O 1 P 0 B B I O 0 b2 b1 b0 P 0 A B I O 3 P 0 A B I O 2 P 0 A B I O 1 P 0 A B I O 0 b3 27H 35H 36H 37H R W R W R W R W Read write Power on Clock stop CE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Register Flag symbol Port1C group I O selection P1CGPIO Port1B b...

Page 196: ...tch are overwritten 15 3 5 To Use an I O Port P0A P0B P1B P1C as an Output Port Select the pin to be used as an output port by using the I O selection register of each port P1C can be set to I O in 3 bit 3 pin units only The pin specified as an output port outputs the contents of the output latch from each pin Output data can be set by executing an instruction to write the contents of the port reg...

Page 197: ...ove the CLR1 instruction overwrites the contents of the output latch of the P0A0 pin with 0 15 3 7 State of I O Port P0A P0B P1B P1C at Reset 1 At power on reset All I O ports are set as input ports Since the contents of the output latch are indefinite the output latch must be initialized by the program before the ports can be switched to output ports 2 At CE reset All I O ports are set as input p...

Page 198: ... port register remains as is 15 4 3 Notes on Using Input Port P0D P0D is internally pulled down when being used as a general purpose port 15 4 4 State of Input Port P0D upon Reset 1 At power on reset All I O ports are set as general purpose input ports 2 At CE reset All I O ports are set as general purpose input ports 3 At clock stop All I O ports are set as general purpose input ports The RESET s...

Page 199: ... Output Ports P0C P1A 1 and 2 below show the configuration of the output ports 1 P0C P0C3 P0C2 P0C1 P0C0 pins 2 P1A P1A3 P1A2 P1A1 P1A0 pins VDD Output latch Port register 1 bit Write instruction Read instruction Output latch Port register 1 bit Write instruction Read instruction ...

Page 200: ...tput latch are read 15 5 3 State of Output Ports P0C P1A at Reset 1 At power on reset The contents of the output latch are output Since the contents of the output latch are indefinite indefinite values are output until the output latch is initialized by the program 2 At CE reset The contents of the output latch are output Since the contents of the output latch are retained the output data remains ...

Page 201: ...e Register The two wire hardware supported bus mode is for the single master Therefore this mode does not support any arbitration function Arbitration must be done by the software Note The two wire bus mode can be used as an I2C bus Table 16 1 External Pins for Serial Interface 16 1 SERIAL INTERFACE MODE REGISTER The serial interface mode register specifies the operation mode of the serial interfa...

Page 202: ... SD OUT CK IN Serial I O SO EXT CLK 0 0 1 1 SD OUT OUT PORT Serial I O SO INT CLK SOFT CLK 0 1 0 0 SD IN CK OUT Serial I O SI INT CLK 0 1 0 1 OUT PORT CK OUT CLK OUT 1OUT PORT 0 1 1 SD OUT CK OUT Serial I O SO INT CLK 1 0 0 0 0 SD IN CK IN BUS SLAVE RX 1 0 0 0 1 SD IN OUT PORT BUS MASTER RX SOFT CLK 1 0 0 1 0 OUT PORT IN PORT 1OUT PORT 1IN PORT 1 0 0 1 1 OUT PORT OUT PORT 2OUT PORT 1 0 1 0 SD OUT ...

Page 203: ...I INT CLK SOFT CLK 1IN PORT 0 0 0 1 1 0 OUT PORT OUT PORT IN PORT 2OUT PORT 1IN PORT 0 0 0 1 1 1 OUT PORT OUT PORT OUT PORT 3OUT PORT 0 0 1 0 0 SD IN CK IN SD OUT Serial I O SI SO EXT CLK 0 0 1 0 1 OUT PORT CK IN SD OUT Serial I O SO EXT CLK 1OUT PORT 0 0 1 1 0 SD IN OUT PORT SD OUT Serial I O SI SO INT CLK SOFT CLK 0 0 1 1 1 OUT PORT OUT PORT SD OUT SerialI O SO INT CLK SOFT CLK 1OUT PORT 0 1 0 0...

Page 204: ...nnels is used as a general purpose port Table 16 4 Channel Setting of Serial Interface 16 1 2 SB The SB flag specifies the serial interface protocol When the SB flag is set to 0 serial I O mode is specified When the SB flag is set to 1 two wire bus mode is specified Since CH1 does not support two wire bus mode the SB flag must be set to 0 when CH1 is used Table 16 5 Specification of Serial Interfa...

Page 205: ... upon specifying CH0 serial I O mode SI mode the SDA pin is in input mode is specified If the SIO0TX flag becomes 1 upon specifying CH0 serial I O mode SO mode the SDA pin is in output mode is specified When the CH1 serial I O mode is specified the SIO0TX flag specifies whether the SO pin is to be used as a serial interface When the SIO0TX flag is set to 1 the SO pin is used as an SO pin When the ...

Page 206: ...eset to 0 1 In two wire bus mode a At power on reset b When a STOP instruction is executed and the system is clock stopped c When a start condition is detected d When the serial interface operation mode is switched from two wire bus mode to serial I O mode 2 In serial I O mode a At power on reset b When a STOP instruction is executed and the system clock is stopped c When data is written into the ...

Page 207: ...e system to determine whether other devices are communicating 16 3 2 SBSTT Serial Bus Start Test Flag The SBSTT flag mapped to b1 of the status register detects the start condition in two wire bus mode The SBSTT flag is valid only when two wire bus mode is selected by setting the SB flag of the serial mode register When the start condition is detected the SBSTT flag is set to 1 When the contents o...

Page 208: ...8 When the contents of the clock counter become 0 or 1 the SIO0SF8 flag is reset to 0 An operation to read the presettable shift register must be performed while the SIO0SF8 flag is set to 1 The SIO0SF8 flag is not influenced by the contents of the serial mode register Fig 16 3 SIO0SF8 and SIO0SF9 Operations 6 7 8 9 1 2 3 4 5 6 7 8 9 SCL SCK Bit counter SIO0SF8 SIO0SF9 ...

Page 209: ... wait register are reset to 0 at power on reset and when the system clock is stopped by executing a STOP instruction Fig 16 4 Configuration of Wait Register 16 4 1 SIO0WRQ1 and SIO0WRQ0 Serial I O Wait Request Flag The SIO0WRQ1 and SIO0WRQ0 flags reserve specify the timing at which the serial interface hardware is forced to wait The µPD17062 expands the concept of waiting from slave operations in ...

Page 210: ... counter at set to 8 the first time after detection of the start condition This means that in this mode the slave operation waits before the ninth clock for acknowledgment of transmission of the slave address rises While the slave operation waits in this mode the contents of the presettable shift register PSR are read to determine whether the address is mapped to the local station Testing the SIO0...

Page 211: ...e shift clock set to the high level in serial I O mode If serial I O mode is specified the clock counter is reset to 0 by performing a data write operation on the wait register For this reason if data wait mode is specified then acknowledge wait mode is respecified the clock counter starts counting after being reset to 0 and the shift clock stops at the high level when the clock counter reaches 9 ...

Page 212: ...e The operation of SBACK varies with the operation mode of the serial interface The following describes the operation of SBACK 1 For reception in two wire bus mode SIO0TX 0 In this case the data set in the SBACK flag is automatically output to the SDA pin at the acknowledge output timing The contents of the SBACK flag can be changed only by executing POKE instruction on the wait register For this ...

Page 213: ...one after the 9th bit of 1 byte is set but before the 9th bit of the next data is set Normally waiting is instigated at the falling edge of the 9th bit Therefore the SBACK flag must be read at this time Data can be written into the SBACK flag by executing a POKE instruction even during transmission 3 In serial I O mode In this case the contents of the SBACK flag are not influenced by the shift clo...

Page 214: ...f the 9th bit clock The PSR operates as described above not only when using the hardware of the serial interface of the µPD17062 also when using internal or external clock but also when the clock is generated by the software with the port P0A0 also used as the shift clock pin set as an output port During transmission data output to the SDA pin is again read into the PSR synchronously with the rise...

Page 215: ...IMD are read 0 is read from each bit Fig 16 6 Configuration of Serial Interface Interrupt Source Register RF 38H Table 16 9 Functions of Serial Interface Interrupt Source Register SIO0IMD1 SIO0IMD0 Function 0 0 An interrupt request is generated when the 7th bit of the shift clock rises 0 1 An interrupt request is generated when the 8th bit of the shift clock falls 1 0 An interrupt request is gener...

Page 216: ...e internal clock of the serial interface The shift clock frequency register is mapped to address 39H of the register file Fig 16 7 shows the configuration of the shift clock frequency register The register is not mapped to the two high order bits of the shift clock frequency register If the two high order bits of the shift clock frequency register are read 0 is read from each bit Fig 16 7 Configur...

Page 217: ... µPD17062 sets the D A outputs in the output data latches PWMRs These latches PWMR0 PWMR1 PWMR2 and PWMR3 are mapped at addresses 05H 06H 07H and 08H respec tively They can be read and write accessed via the DBF Table 17 1 lists the correspondence between the PWMR addresses and the PWM pins Table 17 1 PWMR Addresses and the Corresponding Pins Each PWMR consists of 7 bits Fig 17 1 shows the configu...

Page 218: ...Output from the PWM Pin b3 b2 b1 b0 b3 b2 b1 b0 b6 b5 b4 b3 b2 b1 b0 0 1 PWMR DBF1 0EH DBF0 0FH The PWM pin is used as a D A converter The PWM pin is used as a one bit output port through mode which outputs the content of b5 t 64 s t n 0 75 s where n is a value specified in the PWMR µ µ ...

Page 219: ...ctly speaking a PLL frequency synthesizer is configured by connecting these blocks with an external lowpass filter LPF and voltage controlled oscillator VCO See Sections 18 3 to 18 5 for details of these blocks Fig 18 1 PLL Frequency Synthesizer Block Diagram Note External circuit VCO PSC EO Register Data buffer Unlock detection block Programmable divider PD Phase comparator DET φ Charge pump Refe...

Page 220: ...through the data buffer DBF See Section 18 3 2 Reference frequency generator RFG The reference frequency generator generates a reference frequency that the phase comparator φ DET uses for reference purposes A reference frequency can be selected using the PLL reference mode select register at address 13H See Section 18 4 3 Phase comparator φ DET and unlock detection block The phase comparator compa...

Page 221: ... shown in Fig 18 2 the programmable divider consists of a swallow counter and programmable counter Fig 18 2 Programmable Divider Configuration 0CH 0DH 0EH 0FH DBF3 DBF2 DBF1 DBF0 M S B L S B 16 12 4 PSC VCO Data buffer DBF Address Symbol Data PLL data register 12 bits 4 bits Swallow counter 4 bits Programmable counter 12 bits fN To DET φ 1 2 frequency divider PLL disable signal ...

Page 222: ...h a division value by setting it in the PLL data register PLLR at address 41H through the data buffer DBF Writing to and reading from the PLL data register are performed with the PUT PLLR DBF and GET DBF PLLR instructions respectively A division value is called an N value The following expression represents the frequency fN of a signal generated in the programmable divider using the value N in the...

Page 223: ...ncy synthesizer The reference frequency fr can be selected from 6 25 12 5 and 25 kHz Selection of the reference frequency fr is performed using the PLL reference mode select register at address 13H Section 18 4 2 describes the configuration and functions of the PLL reference mode select register Fig 18 3 Reference Frequency Generator RFG Configuration 13H b3 b2 b0 b1 P L L R F C K 3 P L L R F C K ...

Page 224: ...isable mode Fig 18 4 PLL Reference Mode Select Register Configuration and Functions b3 b2 b1 b0 P L L R F C K 3 P L L R F C K 2 P L L R F C K 1 P L L R F C K 0 13H Read write R W except PLLRFCK1 which is read only 0 0 1 0 0 0 1 1 0 1 1 0 1 1 1 1 0 1 1 1 1 0 1 0 1 0 1 1 1 1 1 0 6 25 kHz 12 5 kHz 25 kHz 1 1 1 1 1 1 1 1 CE Register Address Flag symbol PLL reference mode select PLRFMODE Specify the re...

Page 225: ...he phase comparator to the error output pin EO pin The unlock detection block consists of a delay control circuit and unlock flip flop FF It detects the unlock state of the PLL frequency synthesizer Sections 18 5 2 18 5 3 and 18 5 4 explain the operation of the phase comparator charge pump and unlock detection block respectively Fig 18 5 Configuration of the Phase Comparator Charge Pump and Unlock...

Page 226: ...est signal DW If the divider output frequency fN is lower than the reference frequency fr the phase comparator outputs an up request If fN is higher than fr the phase comparator outputs a down request Fig 18 6 shows the relationship among the reference frequency fr divider output frequency fN up request UP and down request DW In the PLL disable mode neither up nor down request is output The up and...

Page 227: ... 18 6 Relationship among fr fN UP and DW Signals 1 When fN is lagging behind fr 2 When fN is leading fr 3 When fN is in phase with fr 4 When fN is lower than fr fr fN UP DW H fr fN UP DW H fr fN UP DW H H fr fN UP DW H ...

Page 228: ...ts this low signal as unlock state When the unlock state is detected the unlock flip flop FF is set 1 The state of the unlock FF is detected using the PLL unlock FF judge register at address 22H The unlock FF is set at intervals of the then selected reference frequency fr The unlock FF is reset when the PLL unlock FF judge register is read accessed with a PEEK instruction The unlock FF must be che...

Page 229: ...to the window register at intervals larger than the period of the reference frequency Fig 18 7 Configuration and Functions of the PLL Unlock FF Judge Register PLLULJDG Remark The PLLULJDG is reset when it is read accessed with a PEEK instruction Register Flag symbol b3 b2 b1 b0 P L L U L 22H R Address Read write Upon reset Power on Clock stop CE 0 0 0 1 Detects the state of the unlock FF Unlock FF...

Page 230: ... of the PLL Unlock FF Delay Control Register PLULSEN P L U L S E N 3 Register Flag symbol b3 b2 b1 b0 P L U L S E N 1 P L U L S E N 0 32H R W Address Read write 0 Upon reset Power on Clock stop CE 0 0 0 0 1 1 0 1 1 1 25 1 5 s or more 3 5 3 75 s or more 0 25 0 5 s or more Unlock FF disabled Always to be set 0 0 0 0 Hold Sets the delay time between the reference fr and division frequency fN signals ...

Page 231: ...served it returns to the previous state after the CE pin goes low selecting the PLL disable mode then back to a high If it is necessary to select the PLL disable mode at a CE reset the PLL reference mode select register should be initialized by program The PLL frequency synthesizer is disabled at a power on reset Table 18 1 Operation of Each Block During the PLL Disable Mode Block CE pin low or PL...

Page 232: ...ws N fUCO P fr where fUCO Frequency input to the VCO pin fr Reference frequency P Prescaler frequency division ratio 3 Example of setting the PLL data The following example shows how to specify the data required to receive channel 02 of the West Europe TV system assuming that the prescaler used here is the µPB595 and that the frequency division ratio P is 8 Receive frequency 48 25 MHz Reference fr...

Page 233: ...stor string based D A converter and comparator The D A converter is set with data using a 4 bit register ADCR mapped at peripheral address 02H The result of comparison is judged according to the ADCCMP flag in the register file Fig 19 1 A D Converter Configuration ADCCH ADCCH ADCCH AD 2 1 0 CCMP ADCR D A converter Channel selector RF 21H ADCCH R W ADCCMP R Comparator ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 ...

Page 234: ...D when the ADCR is set with 0001B The following expression represents the reference voltage VREF that the D A converter outputs when the ADCR is set with value n decimal VREF VDD 2n 1 where 15 n 1 32 Table 19 1 D A Converter Reference Voltage ADCR 4 0 1 2 13 14 15 Selector 1 2R R R R R R 3 2R VDD D A output reference voltage Set data ADCR Reference voltage VREF Hexadecimal Binary VDD VDD 5 V 0 000...

Page 235: ...imilarly when the PUT ADCR DBF instruction is executed the data in the DBF0 is sent to the ADCR the DBF1 may contain any data The ADCR is undefined at power on At a clock stop and CE reset it retains the previous data 19 4 COMPARISON REGISTER ADCCMP The ADCCMP is a register that holds the output of a comparator which compares an input voltage at the ADC pin with the reference voltage VREF It is ma...

Page 236: ...is mapped at the upper 3 bits of the register file at address 21H Table 19 2 lists the relationships between the ADCCHn and the actually selected pins Table 19 2 ADC Pin Selection When using P1C3 ADC1 as the A D converter specify the P1C as an input port The P0D0 ADC2 to P0D3 ADC5 pins are internally equipped with pull down resistors but the pull down resistors are disconnected when they are selec...

Page 237: ... PUT ADCR DBF Sets reference voltage SKT1 ADCCMP Judges comparison result CLR1 DBF0B3 DBF0B3 0 SET1 DBF0B2 DBF0B2 1 PUT ADCR DBF Sets reference voltage SKT1 ADCCMP Judges comparison result CLR1 DBF0B2 DBF0B2 0 SET1 DBF0B1 DBF0B1 1 PUT ADCR DBF Sets reference voltage SKT1 ADCCMP Judges comparison result CLR1 DBF0B1 DBF0B1 0 SET1 DBF0B0 DBF0B0 1 PUT ADCR DBF Sets reference voltage SKT1 ADCCMP Judges...

Page 238: ...CR DBF ADCCMP DBF0B3 0 DBF0B2 1 ADCR DBF ADCCMP 1 0 1 0 DBF0B2 0 DBF0B1 1 1 Sets DBF data Begins AD conversion Judges comparison result DBF0B3 0 DBF0B2 1 Judges comparison result Sets reference voltage Sets reference voltage DBF0B2 0 DBF0B1 1 ...

Page 239: ... µPD17062 END ADCR DBF ADCCMP DBF0B1 0 DBF0B0 1 ADCR DBF ADCCMP 1 0 1 0 DBF0B0 0 DBF0B0 0 DBF0B1 0 DBF0B0 1 1 Sets reference voltage Judges comparison result Sets reference voltage Judges comparison result ...

Page 240: ...s used per row The maximum number of characters that can be displayed on one screen varies with the number of times control data is used Using the control data three times per row amounts to that it is possible to specify the color three times per row 2 Variable display position range 19 characters 14 rows The display area is defined for the TV screen as follows 3 Up to 8 colors including black an...

Page 241: ...d up to 120 character patterns can be specified however up to 64 character patterns in the same CROMBANK can be displayed on one screen simultaneously No rimming Rimming Rounding Reverse video Color specification by R G and B Blank black Background TV screen 0 0 0 0 H 0 0 F F H 0 1 0 0 H 0 7 F F H 0 8 0 0 H 0 B F F H 0 C 0 0 H 0 F 7 F H ROM MAP CROMBANK0 64 fonts CROMBANK1 56 fonts Characters defi...

Page 242: ...cter positions Note 2 8 Character pattern data is allocated in program memory If there is only a small amount of character pattern data the CROM area can also be used as a program area 9 Character data is allocated in the data memory space The character data can be transferred read and written in the same manner as ordinary data in data memory Notes 1 Up to three control data items can be specifie...

Page 243: ...nd the DMA mode can be specified only for critical sections of the program In this case during five instruction cycles for IDC data transfer only the clock operates and the µPD17062 does nothing During the DMA mode the ROM address for five instructions out of the six is not pointed to by the program counter Instead it is pointed to by the CROM address pointer and the RAM address is pointed to by t...

Page 244: ...of the 17K series assembler They set or reset a one bit flag If they are written in a source program as shown at 1 they are expanded during assembly as shown at 2 PEEK OR POKE WR 80H WR 0010B 80H WR 1 SET1 IDCDMAEN 2 CLR1 IDCDMAEN PEEK AND POKE WR 80H WR 1101B 80H WR Instruction cycle 2 s Instruction cycle 12 s Instruction cycle 2 s µ µ µ ...

Page 245: ...DCEN flag must be set to 1 begin displaying when the vertical sync signal Vsync is high vertical flyback time Vsync low level after the IDCDMAEN flag RF at 00H 1 is turned on b Do not write data to VRAM when the IDCEN flag is 1 display turned on Sample program SET1 IDCDMAEN Sets the DMA mode CLR1 IDCEN If the display is on when VRAM data is to be specified reset the IDCEN turn off the display Sets...

Page 246: ... are each mapped at 112 nibbles of data memory total of 224 nibbles or 224 4 bits That is up to 112 VRAM data items can be specified Fig 20 1 VRAM Configuration VRAM data consists of 8 bits Of the 8 bits the upper 2 bits are the ID field The ID field indicates the type of VRAM data The lower 6 bits are the data field The data field contains the display data or control data 0 1 2 3 4 5 6 7 8 9 A B ...

Page 247: ...field indicate b9 to b4 of the CROM address CROM consists of BANK0 and BANK1 Note that even if the 6 bit VRAM data is the same the CROM address varies according to the value of the CROMBNK b0 at 30H If the data field contains a value of 0 000000B the CROM address is 080 H 10000000 B or 0C0 H 11000000 B Specifying the BANK of CROM selects 080 H or 0C0 H Table 20 4 lists the CROM addresses that the ...

Page 248: ...EH 0CH 08C0H 08CEH 0CC0H 0CCEH 2CH 0AC0H 0ACEH 0EC0H 0ECEH 0DH 08D0H 08DEH 0CD0H 0CDEH 2DH 0AD0H 0ADEH 0ED0H 0EDEH 0EH 08E0H 08EEH 0CE0H 0CEEH 2EH 0AE0H 0AEEH 0EE0H 0EEEH 0FH 08F0H 08FEH 0CF0H 0CFEH 2FH 0AF0H 0AFEH 0EF0H 0EFEH 10H 0900H 090EH 0D00H 0D0EH 30H 0B00H 0B0EH 0F00H 0F0EH 11H 0910H 091EH 0D10H 0D1EH 31H 0B10H 0B1EH 0F10H 0F1EH 12H 0920H 092EH 0D20H 0D2EH 32H 0B20H 0B2EH 0F20H 0F2EH 13H 0...

Page 249: ...s to the above example 1 CROMBNK 0 Display CH appears on the screen The control data used in this case is control data 1 2 CROMBNK 1 Display VO appears on the screen The control data used in this case is control data 1 0 1 2 3 4 5 6 7 8 9 A B 8 0 0 0 0 1 4 0 0 1 CROM data VRAM data 0 8 0 0 H 0 8 0 F H 0 8 1 0 H 0 8 1 F H 0 C 0 0 H 0 C 0 F H 0 C 1 0 H 0 C 1 F H C H V O Control data 1 Control data 2...

Page 250: ...cates a carriage return to BANK1 or BANK2 If the ID field contains 01B it indicates a carriage return to BANK1 and if the ID field contains 11B it indicates a carriage return to BANK2 The carriage return data consists of 6 bits the upper 3 bits of which point to the row address of VRAM and the lower 3 bits of which point to the upper 3 bits of the VRAM column address The lowest bit of the VRAM col...

Page 251: ...1 50 51 52 53 54 55 56 57 2 58 59 5A 5B 5C 5D 5E 5F 3 60 61 62 63 64 65 66 67 4 68 69 6A 6B 6C 6D 6E 6F 5 70 71 72 73 74 75 76 77 6 BANK1 0 1 2 3 4 5 6 7 8 9 A B C D E F C0 C1 C2 C3 C4 C5 C6 C7 0 C8 C9 CA CB CC CD CE CF 1 D0 D1 D2 D3 D4 D5 D6 D7 2 D8 D9 DA DB DC DD DE DF 3 E0 E1 E2 E3 E4 E5 E6 E7 4 E8 E9 EA EB EC ED EE EF 5 F0 F1 F2 F3 F4 F5 F6 F7 6 BANK1 ...

Page 252: ... in VRAM and selects control data in CROM The 6 bits of the data field correspond to b9 to b4 of the CROM address Similarly to the pattern select data the control data select data also requires that a CROM bank be specified A CROM bank is specified using CROMBNK b0 at 30H in the register file Fig 20 5 Relationship between the Control Data and CROM Address b7 b6 b5 b4 b3 b2 b1 b0 1 0 b11 1 b0 1 1 1...

Page 253: ...FH 0E9FH 8AH 08AFH 0CAFH AAH 0AAFH 0EAFH 8BH 08BFH 0CBFH ABH 0ABFH 0EBFH 8CH 08CFH 0CCFH ACH 0ACFH 0ECFH 8DH 08DFH 0CDFH ADH 0ADFH 0EDFH 8EH 08EFH 0CEFH AEH 0AEFH 0EEFH 8FH 08FFH 0CFFH AFH 0AFFH 0EFFH 90H 090FH 0D0FH B0H 0B0FH 0F0FH 91H 091FH 0D1FH B1H 0B1FH 0F1FH 92H 092FH 0D2FH B2H 0B2FH 0F2FH 93H 093FH 0D3FH B3H 0B3FH 0F3FH 94H 094FH 0D4FH B4H 0B4FH 0F4FH 95H 095FH 0D5FH B5H 0B5FH 0F5FH 96H 096...

Page 254: ...ould be set at VRAM addresses sequentially starting at the lowest address so that the corresponding display begins at the upper left corner of the screen b Control data can be used up to three times on each row c The character pattern data that is modified by the control data begins after the control data select data The horizontal start position data and vertical start position data correspond to...

Page 255: ...sists of 16 bits 15 steps The data of 10 horizontal dots corresponds to one CROM step 15 steps at addresses 0H to EH in CROM form one character pattern data item The structure of character pattern data varies according to whether the corresponding character has rimming Fig 20 6 shows the configuration of the character pattern data The highest bit selects whether there is rimming Set the bit to 0 w...

Page 256: ...fined Character pattern data 1 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Character pattern data Rim data b9 b0 b15 b9 b0 0 H 1 H 2 H 3 H 4 H 5 H 6 H 7 H 8 H 9 H A B C D E 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 1 1 0 0 1 1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0...

Page 257: ...1 1 1 1 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 1 0 0 0 1 0 1 0 1 0 0 0 0 0 1 0 0 1 0 0 1 1 0 0 0 1 1 1 0 0 1 0 0 0 1 1 0 0 1 0 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 1 0 0 0 1 0 1 1 0 0 0 1 1 1 0 0 0 1 1 0 1 0 1 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 0 0 0 1 1 0 0 1 0 1 0 0 0 1 1 1 1 0 0 0 0 0 1 1 0 b15 b9 b0 b14 b9 b0 b13 b12 b11 b10 0 0 0 0 0 0 0 0 1 rimming ROM ad...

Page 258: ...trol code Any control data can be specified using data in VRAM 1 Horizontal size data b14 and b13 of control data The horizontal size data determines the horizontal size of each image of a character Each character has four image sizes up to three sizes per row Table 20 7 lists details of the horizontal size data Table 20 7 Horizontal Size Setting 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b...

Page 259: ...g to the LSB and therefore it takes a value from 0H to FH Value 0H corresponds to column 0 and value FH to column 15 The number of character positions left blank between two characters on the same row is specified by the horizontal position data In other words the position of the next character is specified by the number in hexadecimal of blank character positions after the current character posit...

Page 260: ...is specified by the vertical position data In other words the position of the next character is specified by the number in hexadecimal of blank rows after the current row In Fig 20 10 for example the vertical position data of A and that of B are 6H and 1H respectively Similarly the vertical position data of D is 0H Remark The term number of rows used in the above description applies when the verti...

Page 261: ...pin Table 20 9 lists the correspondence between the color data and the output pins Table 20 10 summarizes the relationships between the color data setting and output colors Table 20 9 Color Data Table 20 10 Character Color Color data Character color R G B 0 0 0 Black 0 0 1 Blue 0 1 0 Green 0 1 1 Cyan 1 0 0 Red 1 0 1 Magenta 1 1 0 Yellow 1 1 1 White b2 b1 b0 R G B ...

Page 262: ...ern written in the second operand specifies whether to use rimming in the display pattern 0 No rimming 1 Rimming If the expression does not evaluate to 0 or 1 an error is reported b The display pattern definition consists of 10 characters and can include three different characters O and blank If the display pattern is specified with any other character type or more then 10 characters an error is r...

Page 263: ...mming is not specified the BLANK signal is the same as the character pattern signal generated by ORing the R G and B signals If rimming is specified the BLANK signal output from the BLANK pin is a waveform enveloping the character pattern signal Fig 20 11 IDC Output Waveform a When rimming is not specified b When rimming is specified Pattern signal R G and B pins Blank signal BLANK pin Pattern sig...

Page 264: ...on setting register consists of a 4 bit vertical start position setting register and a 4 bit horizontal start position setting register The IDC start position setting register is mapped at peripheral address 01H It can be read and write accessed using the GET and PUT instructions Note that the IDC start position setting register should not be written to when the IDCEN flag is 1 Fig 20 12 IDC Start...

Page 265: ...pression applies Horizontal start position 4 25 µs 250 ns horizontal start position setting data In Fig 20 13 position A corresponds to the horizontal position setting data 0H When the horizontal position setting data is changed to 1 the start position shifts to the right by 250 ns one dot of the minimum size character that is position B The solid lines indicate the screen when the horizontal posi...

Page 266: ...amely the following expression applies Vertical start position 17 H 1 H vertical start position setting data In Fig 20 14 position A corresponds to the vertical position setting data 0H When the vertical position setting data is changed to 1 the start position shifts down by 1 H that is position B The solid lines indicate the screen when the vertical position setting data is 0 and the dotted lines...

Page 267: ...ition number of horizontal scan lines depends on the state of the VSYNC and HSYNC signals supplied to the µPD17062 as shown in Fig 20 15 In other words the first HSYNC signal that comes after the VSYNC signal rises is counted as 1 H Fig 20 15 Counting the Vertical Start Position VSYNC HSYNC HSYNC Each circled number corresponds to the number of scan lines ...

Page 268: ...umn Row 0 Row 5 4 3 2 1 0 1 2 3 4 5 6 7 0 1 2 VRAM0 VRAM1 VRAM2 VRAM3 VRAM4 VRAM5 VRAM6 VRAM7 8 9 A B C D E F 0 1 2 VRAM8 VRAM9 VRAMA VRAMB VRAMC VRAMD VRAME VRAMF VRAM map BANK2 VRAM0 MEM 2 00H VRAM1 MEM 2 01H VRAM2 MEM 2 02H VRAM3 MEM 2 03H VRAM4 MEM 2 04H VRAM5 MEM 2 05H VRAM6 MEM 2 06H VRAM7 MEM 2 07H VRAM8 MEM 2 08H VRAM9 MEM 2 09H VRAMA MEM 2 0AH VRAMB MEM 2 0BH VRAMC MEM 2 0CH VRAMD MEM 2 0...

Page 269: ... VRAM2 0 Specifies display character data C MOV VRAM3 0CH MOV VRAM4 0 Specifies display character data H MOV VRAM5 0DH MOV VRAM6 1000B Specifies control code 2 MOV VRAM7 0001B MOV VRAM8 0 Specifies display character data 0 MOV VRAM9 0 MOV VRAMA 0 Specifies display character data 2 MOV VRAMB 2 MOV VRAMC 0100B CR carriage return MOV VRAMD 0000B MOV VRAME 0100B CR carriage return MOV VRAMF 0000B LOOP...

Page 270: ...3 0 8 0 5 0 1 8 3 0 8 0 6 0 1 8 3 0 8 0 7 0 1 8 3 0 8 0 8 0 1 8 3 0 8 0 9 0 1 8 3 0 8 0 A 0 1 8 3 0 8 0 B 0 1 8 3 0 8 0 C 0 1 C 7 0 8 0 D 0 0 F E 0 8 0 E 0 0 7 C 0 8 0 F 0 5 8 A DCP 0 DCP 0 DCP 0 DCP 0 DCP 0 DCP 0 DCP 0 DCP 0 DCP 0 DCP 0 DCP 0 DCP 0 DCP 0 DCP 0 DCP 0 DW OOOOO OOOOOOO OOO OOO OO OO OO OO OO OO OO OO OO OO OO OO OO OO OO OO OOO OOO OOOOOOO OOOOO CD1 0000010110001010B Control data 1 ...

Page 271: ...al size standard and vertical size standard Horizontal position column 1 and vertical position row 0 Color green G and rimming no 1 OOOO OOOO OO OO OOOOOO OOOOOO 2 0 8 2 0 0 0 0 0 0 8 2 1 0 0 7 C 0 8 2 2 0 0 F E 0 8 2 3 0 1 C 7 0 8 2 4 0 1 8 3 0 8 2 5 0 0 0 3 0 8 2 6 0 0 0 7 0 8 2 7 0 0 0 E 0 8 2 8 0 0 3 8 0 8 2 9 0 0 E 0 0 8 2 A 0 1 C 0 0 8 2 B 0 1 8 0 0 8 2 C 0 1 8 0 0 8 2 D 0 1 F F 0 8 2 E 0 1 ...

Page 272: ... 8 C 2 0 0 F F 0 8 C 3 0 1 C 0 0 8 C 4 0 1 8 0 0 8 C 5 0 1 8 0 0 8 C 6 0 1 8 0 0 8 C 7 0 1 8 0 0 8 C 8 0 1 8 0 0 8 C 9 0 1 8 0 0 8 C A 0 1 8 0 0 8 C B 0 1 8 0 0 8 C C 0 1 C 0 0 8 C D 0 0 F F 0 8 C E 0 0 7 F 0 8 C F 0 0 0 0 DCP 0 DCP 0 DCP 0 DCP 0 DCP 0 DCP 0 DCP 0 DCP 0 DCP 0 DCP 0 DCP 0 DCP 0 DCP 0 DCP 0 DCP 0 DW OO 0000000000000000B C OOO OOO OOOOOOO OOOOO OOO OO OO OO OO OO OO OO OOO OOOOOOO OO...

Page 273: ... D 8 0 1 F F 0 8 D 9 0 1 8 3 0 8 D A 0 1 8 3 0 8 D B 0 1 8 3 0 8 D C 0 1 8 3 0 8 D D 0 1 8 3 0 8 D E 0 1 8 3 0 8 D F 0 0 0 0 DCP 0 DCP 0 DCP 0 DCP 0 DCP 0 DCP 0 DCP 0 DCP 0 DCP 0 DCP 0 DCP 0 DCP 0 DCP 0 DCP 0 DCP 0 DW OO 0000000000000000B H OO OO OO OOOOOOOOO OOOOOOOOO OO OO OO OO OO OO NO USE OO OO ROM ADDRESS OO OO OO OO OO OO OO OO OO OO OO OO ...

Page 274: ...ate control register After passing through the gate the amplifier output is counted in the 6 bit HSYNC counter When the gate is closed the HSYNC counter stops counting and sets 1 in the test gate open register The HSYNC counter is a read only register Reading the HSYNC counter finds out how many pulses are counted when the gate is open Dividing the number of pulses by the time during which the gat...

Page 275: ...o turns off the bias input to the horizontal sync signal counter and therefore it should be selected when the port is used This mode is selected at a power on reset and a clock stop 21 2 2 Gate Open Mode When the gate open mode is entered the gate opens and causes the HSYNC counter to start counting the input signal after it is reset When the HSYNC counter overflows it goes back to 0 In this mode ...

Page 276: ...with the Hsync input is open Note that when the 1 69 ms gate mode is selected the HSCGOSTT becomes high when the input data is set even if there is no gate clock 21 4 EXAMPLE OF USING THE HORIZONTAL SYNC SIGNAL The following example is a program that uses the horizontal sync signal counter When the 1 69 ms gate is open CLR1 P0BBIO3 Sets P0B3 in input mode PEEK WR 0B6H AND WR 0111B POKE 0B6H WR LOO...

Page 277: ...n4 0 1 0 1 5 XOR r m XOR m n4 0 1 1 0 6 OR r m OR m n4 INC AR INC IX MOVT DBF AR BR AR CALL AR RET RETSK EI DI 0 1 1 1 7 RETI PUSH AR POP AR GET DBF p PUT p DBF PEEK WR rf POKE rf WR RORC r STOP s HALT h NOP 1 0 0 0 8 LD r m ST m r 1 0 0 1 9 SKE m n4 SKGE m n4 1 0 1 0 A MOV r m MOV m r 1 0 1 1 B SKNE m n4 SKLT m n4 1 1 0 0 C BR addr page 0 CALL addr page 0 1 1 0 1 D BR addr page 1 MOV m n4 1 1 1 0...

Page 278: ... address pointer MPE Memory pointer enable flag m Data memory address specified by mR and mC mR Data memory row address high order mC Data memory column address low order n Bit position four bits n4 Immediate data four bits PAGE Page Bits 12 and 11 of the program counter PC Program counter p Peripheral address pH Peripheral address three high order bits pL Peripheral address four low order bits r ...

Page 279: ...1000 01010 11010 11101 00111 Operand mR mR mR mR 000 000 mR mR mR mR mR mR mR mR mR mR mR mR mR mR mR mR 000 mR mR mR mR mR 000 mC mC mC mC 1001 1000 mC mC mC mC mC mC mC mC mC mC mC mC mC mC mC mC 0111 mC mC mC mC mC 0001 r n4 r n4 0000 0000 r n4 r n4 r n4 r n4 r n4 n n n4 n4 n4 n4 r r r r r n4 0000 Operation r r m m m n4 r r m CY m m n4 CY AR AR 1 IX IX 1 r r m m m n4 r r m CY m m n4 CY r r m m ...

Page 280: ...00111 00111 000 000 rfR rfR pH pH 000 000 000 001 100 000 001 010 011 100 0000 0000 rfC rfC pL pL 0000 0000 0000 0000 0000 0000 0000 s h 0000 Operation Operand addr addr 1101 1100 0011 0010 1011 1010 0100 0101 1110 1110 1110 1111 1111 1111 1111 1111 Interrupt Others SP SP 1 ASR AR AR ASR SP SP 1 WR rf rf WR DBF p p DBF PC10 0 addr PAGE 0 PC10 0 addr PAGE 1 PC AR SP SP 1 ASR PC PC11 0 PC10 0 addr S...

Page 281: ...rand Operation n Built in SKTn flag 1 flag n if flag 1 to flag n all 1 then skip 1 n 4 SKFn flag 1 flag n if flag 1 to flag n all 0 then skip 1 n 4 SETn flag 1 flag n flag 1 to flag n 1 1 n 4 CLRn flag 1 flag n flag 1 to flag n 0 1 n 4 NOTn flag 1 flag n if flag n 0 then flag n 1 1 n 4 if flag n 1 then flag n 0 INITFLG NOT flag 1 if description NOT flag n then flag n 0 1 n 4 NOT flag n if descript...

Page 282: ...ister Bank register Bits 10 to 8 of the index register high Bits 6 to 4 of the memory pointer Memory pointer enable flag Bits 7 to 4 of the index register Bits 3 to 0 of the memory pointer Bits 3 to 0 of the index register Bits 6 to 3 of the register pointer Bits 2 to 0 of the register pointer Program status word BCD operation flag Compare flag Carry flag Zero flag Index enable flag Read write Des...

Page 283: ...3 of port 0D P0D2 FLG 0 73H 2 RNote Bit 2 of port 0D P0D1 FLG 0 73H 1 RNote Bit 1 of port 0D P0D0 FLG 0 73H 0 RNote Bit 0 of port 0D P1A3 FLG 1 70H 3 R W Bit 3 of port 1A P1A2 FLG 1 70H 2 R W Bit 2 of port 1A P1A1 FLG 1 70H 1 R W Bit 1 of port 1A P1A0 FLG 1 70H 0 R W Bit 0 of port 1A P1B3 FLG 1 71H 3 R W Bit 3 of port 1B P1B2 FLG 1 71H 2 R W Bit 2 of port 1B P1B1 FLG 1 71H 1 R W Bit 1 of port 1B P...

Page 284: ... Hsync counter gate open flag PLLRFCK3 FLG 0 93H 3 R W PLL reference clock selection flag PLLRFCK2 FLG 0 93H 2 R W PLL reference clock selection flag PLLRFCK1 FLG 0 93H 1 R W PLL reference clock selection flag PLLRFCK0 FLG 0 93H 0 R W PLL reference clock selection flag INTNCMD3 FLG 0 95H 3 R W INTNC pin status flag dummy INTNCMD2 FLG 0 95H 2 R W INTNC pin status flag INTNCMD1 FLG 0 95H 1 R W INTNC...

Page 285: ...n flag P1BBIO0 FLG 0 0B5H 0 R W P1B0 I O selection flag P0BBIO3 FLG 0 0B6H 3 R W P0B3 I O selection flag P0BBIO2 FLG 0 0B6H 2 R W P0B2 I O selection flag P0BBIO1 FLG 0 0B6H 1 R W P0B1 I O selection flag P0BBIO0 FLG 0 0B6H 0 R W P0B0 I O selection flag P0ABIO3 FLG 0 0B7H 3 R W P0A3 I O selection flag P0ABIO2 FLG 0 0B7H 2 R W P0A2 I O selection flag P0ABIO1 FLG 0 0B7H 1 R W P0A1 I O selection flag P...

Page 286: ...T 05H R W PWM data register 0 PWMR1 DAT 06H R W PWM data register 1 PWMR2 DAT 07H R W PWM data register 2 PWMR3 DAT 08H R W PWM data register 3 AR DAT 40H R W Address register PLLR DAT 41H R W PLL data register AR_EPA1 DAT 8040H CALL BR MOVT instruction operand EPA bit is on AR_EPA0 DAT 4040H CALL BR MOVT instruction operand EPA bit is off 23 6 OTHERS Symbol Attribute Value Description DBF DAT 0FH...

Page 287: ...40 to 85 when IDC has stopped Storage temperature Vstg 55 to 125 C RECOMMENDED OPERATION RANGE Ta 40 to 85 C Parameter Symbol Conditions Min Typ Max Unit Supply voltage VDD1 Ta 20 to 70 C when CPU PLL and IDC are operating 4 5 5 0 5 5 V VDD2 When CPU and PLL are operating IDC is not operating 4 5 5 0 5 5 V VDD3 When only CPU is operating PLL and IDC are not operating 4 0 5 0 5 5 V Data hold voltag...

Page 288: ...perating PLL and IDC are not operating 4 0 5 0 5 5 V Supply current IDD4 When only CPU is operating PLL and IDC are not 1 0 3 0 mA operating and HALT instruction is being used 20 instructions are executed at 5 ms intervals Data hold voltage VDDR When the timer FF power failure detection method is used 3 0 5 5 V When crystal oscillation has stopped Data hold current IDDR When crystal oscillation ha...

Page 289: ...ition N 0 17 0 007 A 44 46 MAX 1 751 MAX B 1 78 MAX 0 070 MAX F 0 85 MIN 0 033 MIN G 3 2 0 3 0 126 0 012 J 5 72 MAX 0 226 MAX K 15 24 T P 0 600 T P C 1 778 T P 0 070 T P D 0 50 0 10 0 020 0 004 0 005 H 0 51 MIN 0 020 MIN I 4 31 MAX 0 170 MAX L 13 2 0 520 M 0 25 0 010 0 004 0 003 0 10 0 05 M R M I H G F D N C B K P48C 70 600B 1 R 0 15 0 15 2 ltem K to center of leads when formed parallel L A J 1 24...

Page 290: ... 005 inch of its true position T P at maximum material condition D 17 2 0 2 0 677 0 008 0 125 0 075 0 005 0 003 A 17 2 0 2 0 677 0 008 I 0 13 0 005 P 2 7 0 106 S R 3 0 MAX 5 5 0 119 MAX 5 5 C 14 0 0 2 0 551 0 009 0 008 B 14 0 0 2 0 551 0 009 0 008 H 0 35 0 10 0 014 0 004 0 005 M 0 15 0 006 0 004 0 003 L 0 8 0 2 0 031 0 009 0 008 0 10 0 05 48 49 64 1 16 32 17 33 M B D F G H J I P N L K M detail of ...

Page 291: ...eflow processes 2 Exposure limit Note 7 days 20 hours of pre baking is required at 125 C afterward Cautions 1 Do not start reflow soldering the device if its temperature is higher than the room temperature because of a previous reflow soldering 2 Do not use water for flux cleaning before a second reflow soldering Terminal temperature 300 C or less Heat time 3 seconds or less for each side of devic...

Page 292: ...SE board for the µPD17002 and µPD17062 It is used solely for evaluating the system It is also used for debugging in combination with the in circuit emulator The EP 17002CU is an emulation probe for the 48 pin shrink DIP 600 mil It is used to connect the SE board and the target system The EP 17002GC is an emulation probe for the 64 pin QFP 14 14 mm It is used with EV 9400GC 64Note 3 to connect the ...

Page 293: ...rograms by using a personal computer and the in circuit emulator OS Part number Description Distribution media Host machine Software PC 9800 series IBM PC AT PC 9800 series IBM PC AT PC 9800 series IBM PC AT Name MS DOS PC DOS Windows MS DOSTM PC DOS TM MS DOS PC DOS Remark The following table lists the versions of the operating systems described in the above table Note MS DOS versions 5 00 and 5 ...

Page 294: ...294 µPD17062 MEMO ...

Page 295: ...y be caused by noise This allows current to flow in the CMOS device resulting in a malfunction Use a pull up or pull down resistor to hold a fixed input level Since unused pins may function as output pins at unexpected times each unused pin should be separately connected to the VDD or GND pin through a resistor If handling of unused pins is documented follow the instructions in the document Status...

Page 296: ...ated entirely To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device customer must incorporate sufficient safety measures in its design such as redundancy fire containment and anti failure features NEC devices are classified into the following three quality grades Standard Special and Specific The Specific quality grade applies only to dev...

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