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Circuit Description
NEC-FA150ATUA
8. E
2
PROM (Circuit diagram MAIN PWB 4/6)
Data transfer between I308 (24LC32) and CPU (I306) is effected through the IIC bus SCL (pin 80) and SDA (pin
81) of I306. The data to be transferred to each device are stored in I308.
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I303 control data.
9. CPU circuit (Circuit diagram MAIN PWB 4/6)
I306 (M30620FGMGP) functions as the CPU.
The source voltage for the device is 3.3V and the system clock frequency is 10MHz.
9.1 Detection of POWER switch status
The CPU identifies the ON status of the two power supplies. The identification is made when the power supply
is turned off. For example, if the power supply is turned off with the POWER switch, the POWER switch must be
turned on when activating the power supply again. If the power supply is turned off by pulling out the power
cord, then this power supply can be turned on by connecting the power cord, without pressing the POWER
switch.
9.2 Display mode identification
9.2.1 Functions
(1) Display mode identification
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The display mode of input signal is identified based on Table 1, and according to the frequency and polarity
(HPOL, VPOL) of horizontal or vertical sync signal, presence of the horizontal or vertical sync signal, and the
discrimination signal (HSYNC_DETECT, VSYNC_DETECT).
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When the mode has been identified through the measurement of horizontal and vertical frequencies, the total
number of lines is determined with a formula of Horizontal frequency / Vertical frequency = Total number
of lines. Final identification can be made by examining the coincidence of the obtained figure with the
number of lines for the mode identified from the frequency.
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When the detected frequency if the sync signal has changed, the total number of lines should be counted even
through it identified frequency in the same mode. Then, it is necessary to examine whether the preset value for
the vertical display position has exceeded the total number of lines. If exceeded, a maximum value should be
set up.
(2) Power save mode.
The power save mode is assumed when the horizontal / vertical signals are as specified below.
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If there is no horizontal sync signal input or below 10KHz.
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If there is no vertical sync signal input or below 10Hz.