NEC MuPD754202 Datasheet Download

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PD754202, 754202(A)

Instruction

Number

Addressing

Mnemonic

Operand

of machine

Operation

Skip condition

group

of bytes

cycles

area

Interrupt

IME (IPS.3)

←

control
instructions

×××

←

IME (IPS.3)

←

×××

←

Input/output

Note 1

A, PORTn

←

PORTn

(n = 3, 6, 7, 8)

instructions

OUT

Note 1

PORTn, A

PORTn

←

(n = 3, 6, 8)

CPU control

HALT

Set HALT Mode (PCC.2

←

instructions

STOP

Set STOP Mode (PCC.3

←

NOP

No Operation

Special

SEL

RBn

RBS

←

(n = 0-3)

instructions

MBn

MBS

←

(n = 0, 15)

GETI

Notes 2, 3

taddr

• When TBR instruction

*10

10–0

←

(taddr)

2–0

+ (taddr+1)

• When TCALL instruction

(SP–4) (SP–1) (SP–2)

←

0, PC

10–0

(SP–3)

←

MBE, RBE, 0, 0

10–0

←

(taddr)

2–0

+ (taddr+1)

←

SP–4

• When instruction other than TBR and

Depending on

TCALL instructions

the reference

(taddr) (taddr+1) instruction is executed.

instruction

• When TBR instruction

*10

10–0

←

(taddr)

2–0

+ (taddr+1)

• When TCALL instruction

(SP–6) (SP–3) (SP–4)

←

10–0

(SP–5)

←

0, 0, 0, 0

(SP–2)

←

, MBE, RBE

10–0

←

(taddr)

2–0

+ (taddr+1)

←

SP–6

• When instruction other than TBR and

Depending on

TCALL instructions

the reference

(taddr) (taddr+1) instruction is executed.

instruction

Notes 1.

While the IN instruction and OUT instruction are being executed, MBS must be set to 0, or MBE must

be set to 1 and MBS must be set to 15.

The TBR and TCALL instructions are the table definition assembler pseudo instructions of the GETI

instruction.

The above operations in the shaded boxes can be performed only in the Mk II mode. The other

operations can be performed only in the Mk I mode.

– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –

– – – – – – – – – – – – –

– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –

– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –

– – – – – – – – – – – – –

– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –

– – – – – – – – – – – – –

Summary of Contents for MuPD754202

Page 1: ...Low voltage operation VDD 1 8 to 6 0 V On chip memory Program memory ROM 2048 8 bits Data memory RAM 128 4 bits Variable instruction execution time useful for high speed operation and power save 0 95 1 91 3 81 15 3 µs at 4 19 MHz operation 0 67 1 33 2 67 10 7 µs at 6 0 MHz operation Compact package 20 pin plastic shrink SOP 300 mil 0 65 mm pitch APPLICATIONS Automotive electronics such as keyless ...

Page 2: ...00 mil 1 27 mm pitch Special µPD754202GS A GJG 20 pin plastic shrink SOP 300 mil 0 65 mm pitch Special Remark indicates the ROM code suffix Differences between µPD754202 and µPD754202 A Part Number µPD754202 µPD754202 A Item Quality grade Standard Special Please refer to Quality Grades on NEC Semiconductor Devices Document No C11531E published by NEC Corporation to know the specification of qualit...

Page 3: ...t output 9 Software specifiable on chip pull up resistor connection Total 13 Timer 4 channels 8 bit timer counter 3 channels Usable as 16 bit timer counter Basic interval timer watchdog timer 1 channel Bit sequential buffer BSB 16 bits Vectored interrupt External 1 Internal 4 Test input External 1 key return reset function provided System clock oscillation circuit Ceramic crystal oscillation circu...

Page 4: ... 13 5 MEMORY CONFIGURATION 14 6 PERIPHERAL HARDWARE FUNCTION 17 6 1 Digital I O Port 17 6 2 Clock Generator 17 6 3 Basic Interval Timer Watchdog Timer 19 6 4 Timer Counter 20 6 5 Bit Sequential Buffer 24 7 INTERRUPT FUNCTION AND TEST FUNCTION 25 8 STANDBY FUNCTION 27 9 RESET FUNCTION 28 9 1 Configuration and Operation Status of Reset Function 28 9 2 Watchdog Flag WDF Key Return Flag KRF 32 10 MASK...

Page 5: ...5 µPD754202 754202 A APPENDIX A µPD754202 75F4264 FUNCTION LIST 58 APPENDIX B DEVELOPMENT TOOLS 59 APPENDIX C RELATED DOCUMENTS 62 ...

Page 6: ...C Internally Connected INT0 External Vectored Interrupt KR4 to KR7 Key Return 4 to 7 KRREN Key Return Reset Enable P30 to P33 Port 3 P60 to P63 Port 6 P70 to P73 Port 7 P80 Port 8 PTO0 to PTO2 Programmable Timer Output 0 to 2 RESET Reset VDD Positive Power Supply VSS Ground X1 X2 System Clock Ceramic Crystal 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 RESET X1 X2 VSS IC VDD P60 P61 INT0 P62...

Page 7: ...BT RESET INTT0 TOUT INTT1 INTT2 PTO0 P30 PTO1 P31 PTO2 P32 INT0 P61 KR4 P70 KR7 P73 ALU PROGRAM COUNTER PROGRAM MEMORY ROM 2048 8 BITS DECODE AND CONTROL CY SP 8 SBS BANK GENERAL REG DATA MEMORY RAM 128 4 BITS PORT3 4 PORT6 4 PORT7 4 PORT8 1 BIT SEQ BUFFER 16 P30 P33 P60 P63 P70 P73 P80 CLOCK DIVIDER SYSTEM CLOCK GENERATOR STAND BY CONTROL fX 2N X1 X2 Φ CPU CLOCK IC V DD VSS RESET 4 KRREN ...

Page 8: ...hmitt trigger input Programmable 4 bit input output port PORT3 This port can be specified input output bit wise On chip pull up resistor can be specified by software in 4 bit units Programmable4 bitinput outputport PORT6 This port can be specified input output bit wise On chip pull up resistor can be specified by software in 4 bit units Noise eliminator can be selected on P61 INT0 4 bit input port...

Page 9: ...to P73 Falling edge detection testable input Input B A KRREN Input Key return reset enable Input B When KRREN high level in STOP mode reset signal is generated at falling edge of KRn X1 Input System clock oscillation crystal ceramic connection pin X2 If using an external clock input to X1 and reverse input to X2 RESET Input System reset input low level active B A Pull up resistor can be incorporat...

Page 10: ...ch IN OUT VDD P ch output disable data P U R enable Type D Type A IN OUT VDD P U R Mask Option IN VDD P U R P U R enable P ch IN OUT Type D Type B output disable data P U R Pull Up Resistor P U R Pull Up Resistor P U R Pull Up Resistor Schmitt trigger input with hysteresis characteristics CMOS standard input buffer Push pull output that can be placed in output high impedance both P ch and N ch off...

Page 11: ...2 PTO2 P33 P60 P61 INT0 P62 P63 P70 KR4 Connect to VDD P71 KR5 P72 KR6 P73 KR7 P80 Input state Independently connect to VSS or VDD via a resistor Output state Leave open KRREN When this pin is connected to VDD internal reset signal is gener ated at the falling edge of the KRn pin in the STOP mode When this pin is connected to VSS internal reset signal is not generated even if the falling edge of K...

Page 12: ...for subroutine instructions BRA addr1 instruction Not available Available CALLA addr1 instruction CALL addr instruction 3 machine cycles 4 machine cycles CALLF faddr instruction 2 machine cycles 3 machine cycles Caution The Mk II mode supports a program area exceeding 16 Kbytes for the 75X and 75XL Series Therefore this mode is effective for enhancing software compatibility with products that have...

Page 13: ...gram When using the Mk II mode it must be initialized to 0000B Figure 4 1 Stack Bank Select Register Format SBS3 SBS2 SBS1 SBS0 3 2 1 0 Symbol SBS Address F84H 0 0 0 1 0 Memory bank 0 Other than above setting prohibited 0 must be set in the bit 2 position Stack area specification Mk II mode Mk I mode Mode switching specification Caution Because SBS 3 is set to 1 after a RESET signal is generated t...

Page 14: ...table wherein the program start address and values set for the RBE and MBE by the vectored interrupts are written Interrupt service can start from any address Addresses 0020H to 007FH Table area referenced by the GETI instructionNote Note The GETI instruction realizes a 1 byte instruction on behalf of any 2 byte instruction 3 byte instruction or two 1 byte instructions It is used to decrease the n...

Page 15: ...rt address high order 3 bits INT0 start address low order 8 bits MBE RBE INTT0 start address high order 3 bits INTT0 start address low order 8 bits MBE RBE INTT1 INTT2 start address high order 3 bits INTT1 INTT2 start address low order 8 bits GETI instruction reference table 0000H 0001H 0002H 0003H 0004H 0005H 0006H 0007H 0008H 0009H 000AH 000BH 000CH 000DH 0020H 007FH 0080H 07FFH CALLF faddr inst...

Page 16: ...gure 5 2 Data Memory Map 000H 01FH 020H 07FH 080H 0FFH F80H FFFH 128 4 Not incorporated 128 4 96 4 32 4 0 15 General purpose register area Stack area Data area static RAM 128 4 Peripheral hardware area Data memory Memory bank ...

Page 17: ...PORT7 4 bit input 4 bit input only port Also used for KR4 to KR7 pins On chip pull up resistor can be specified by mask option bit wise PORT8 1 bit I O Can be set to input or output mode bit wise 6 2 Clock Generator The clock generator provides the clock signals to the CPU and peripheral hardware Its configuration is shown in Figure 6 1 The operation of the clock generator is set with the processo...

Page 18: ...o one machine cycle of the instruction X1 X2 System clock oscillator Oscillation stops 1 2 1 41 16 fX Divider 1 4 Φ HALT F F S R Q S R Q STOP F F PCC0 PCC1 PCC2 PCC3 PCC2 PCC3 clear HALTNote STOPNote Wait release signal from BT Reset signal Standby release signal from interrupt control circuit PCC 4 Basic interval timer BT Timer counter INT0 noise eliminator 1 1 to 1 4096 CPU INT0 noise eliminator...

Page 19: ...ounts the wait time when the standby mode is released d Reads the contents of counting Figure 6 2 Basic Interval Timer Watchdog Timer Block Diagram Note Instruction execution From clock generator fX 25 fX 27 fX 29 fX 212 MPX BTM3 BTM2 BTM1 BTM0 BTM 4 SET1Note Internal bus 8 1 Basic interval timer 8 bit frequency divider Clear BT Wait release signal when standby is released Set Clear 3 WDTM SET1Not...

Page 20: ...ration b Square wave output of any frequency to PTO0 PTO2 pins c Count value read function The timer counter can operate in the following four modes as set by the mode register Table 6 2 Mode List Mode Channel Channel 0 Channel 1 Channel 2 TM11 TM10 TM21 TM20 8 bit timer counter mode 0 0 0 0 PWM pulse generator mode 0 0 0 1 16 bit timer counter mode 1 0 1 0 Carrier generator mode 0 0 1 1 Remark Av...

Page 21: ...lear Count register 8 T0 8 8 Comparator 8 Modulo register 8 TMOD0 TOUT F F Reset TOE0 PORT3 0 PMGA bit 0 T0 enable flag P30 output latch Port 3 input output mode Output buffer P30 PTO0 INTT0 IRQT0 set signal RESET IRQT0 clear signal Internal bus Match f x 2 4 f x 2 6 f x 2 8 f x 2 10 Note Instruction execution Caution Always set bits 0 and 1 to 0 when setting data to TM0 ...

Page 22: ... bit timer counter mode Selector Match Reset TOUT F F TOE1 PORT3 1 PMGA bit 1 T1 enable flag P31 output latch Port 3 input output mode Output buffer P31 PTO1 INTT1 IRQT1 set signal RESET IRQT1 clear signal Timer counter channel 2 match signal When 16 bit timer counter mode Timer counter channel 2 comparator When 16 bit timer counter mode Timer counter channel 2 reload signal Internal bus f x 2 5 f...

Page 23: ...2 Reload Overflow Carrier generator mode PORT3 2 PMGA bit 2 P32 output latch Port 3 input output mode Output buffer P32 PTO2 Timer counter channel 1 clock input INTT2 IRQT2 set signal RESET IRQT2 clear signal Timer counter channel 1 match signal When 16 bit timer counter mode Timer counter channel 1 clear signal When 16 bit timer counter mode Timer counter channel 1 match signal When carrier gener...

Page 24: ... sequence therefore it is useful when processing large data bit wise Figure 6 6 Bit Sequential Buffer Format Remarks 1 In the pmem L addressing the specified bit moves corresponding to the L register 2 In the pmem L addressing the BSB can be manipulated regardless of MBE MBS specification Address Bit Symbol L register L FH L CH L BH L 8H L 7H L 4H L 3H L 0H DECS L INCS L BSB3 BSB2 BSB1 BSB0 3 2 1 ...

Page 25: ...he interrupt enable flag IE and interrupt master enable flag IME Can set any interrupt start address Multiple interrupts wherein the order of priority can be specified by the interrupt priority select register IPS Test function of interrupt request flag IRQ An interrupt generated can be checked by software Release the standby mode The interrupt to be released can be selected by the interrupt enabl...

Page 26: ...2 IRQ2 KR4 P70 KR7 P73 Falling edge detector Note 2 Key return reset circuit IM2 IME IPS IST1 IST0 Decoder VRQn Priority control circuit Standby release signal Selector Vector table address generator Notes 1 Noise eliminator Standby release is disabled when noise eliminator is selected 2 The INT2 pin is not available Interrupt request flag IRQ2 is set at the KRn pin falling edge when IM20 1 and IM...

Page 27: ...ops Operable watchdog timer BT mode The IRQBT is set in the reference time interval WT mode Reset signal generation by BT overflow Timer counter Operation stops Operable External interrupt The INT0 is not operableNote The INT2 is operable at the falling edge of KRn CPU Operation stops Release signal Reset signal Reset signal Interrupt request signal sent from Interrupt request signal sent from int...

Page 28: ...a falling edge signal from KRn in the STOP mode When any of these reset signals is input an internal reset signal is generated The configuration is shown in Figure 9 1 Figure 9 1 Configuration of Reset Function VDD Mask option KRREN RESET Q R S Q S R Q S R Instruction STOP mode KRF WDF Watchdog timer overflow Internal reset signal Instruction VDD Mask option P70 KR4 P71 KR5 P72 KR6 P73 KR7 Interna...

Page 29: ...ure 9 2 Reset Operation by RESET Signal Generation Note The following 2 time modes can be specified with mask option 217 fx 21 8 ms at 6 0 MHz operation 31 3 ms at 4 19 MHz operation 215 fx 5 46 ms at 6 0 MHz operation 7 81 ms at 4 19 MHz operation Operation mode or standby mode WaitNote RESET signal generated Operation mode HALT mode Internal reset operation ...

Page 30: ...to memory s address 0000H to the RBE and bit 7 to the MBE the RBE and bit 7 to the MBE Stack pointer SP Undefined Undefined Stack bank select register SBS 1000B 1000B Data memory RAM Held Undefined General purpose register X A H L D E B C Held Undefined Bank select register MBS RBS 0 0 0 0 Basic interval Counter BT Undefined Undefined timer watchdog Mode register BTM 0 0 timer Watchdog timer enabl...

Page 31: ...ster IPS 0 0 INT0 2 mode registers IM0 IM2 0 0 0 0 Digital port Output buffer Off Off Output latch Cleared 0 Cleared 0 I O mode registers PMGA PMGC 0 0 Pull up resistor setting register POGA POGB 0 0 Bit sequential buffer BSB0 BSB3 Held Undefined Table 9 1 Hardware Status After Reset 3 3 RESET signal RESET signal RESET signal RESET signal Hardware generation by key generation in the generation by ...

Page 32: ...signal Figure 9 3 shows the WDF operation in generating each signal and Figure 9 4 shows the KRF operation in generating each signal Table 9 2 WDF and KRF Contents Correspond to Each Signal External RESET Reset signal Reset signal WDF clear KRF clear Hardware signal generation generation by watch generation by the instruction instruction dog timer overflow KRn input execution execution Watchdog fl...

Page 33: ...e Internal reset operation STOP mode Internal reset operation Internal reset operation HALT mode Operation mode STOP mode HALT mode Operation mode STOP instruction execution Reset signal generation by the KRn input External RESET signal generation STOP instruction execution KRF clear instruction execution Reset signal generation by the KRn input ...

Page 34: ...tor in 1 bit units 3 Connection of a 100 kΩ typ pull up resistor in 1 bit units Mask option of RESET pin Pull up resistors can be connected to these pins 1 No pull up resistor connection 2 Connection of a 100 kΩ typ pull up resistor Standby function mask option The wait time after RESET signal can be selected 1 217 fx 21 8 ms fx 6 0 MHz operation 31 3 ms fx 4 19 MHz operation 2 215 fx 5 46 ms fx 6...

Page 35: ...bels that can be described for fmem and pmem For details see µPD754202 User s Manual U11132E Expression Description method format reg X A B C D E H L reg1 X B C D E H L rp XA BC DE HL rp1 BC DE HL rp2 BC DE rp XA BC DE HL XA BC DE HL rp 1 BC DE HL XA BC DE HL rpa HL HL HL DE DL rpa1 DE DL n4 4 bit immediate data or label n8 8 bit immediate data or label mem 8 bit immediate data or labelNote bit 2 ...

Page 36: ...ister pair DE DE extended register pair HL HL extended register pair PC Program counter SP Stack pointer CY Carry flag bit accumulator PSW Program status word MBE Memory bank enable flag RBE Register bank enable flag PORTn Port n n 3 6 7 8 IME Interrupt master enable flag IPS Interrupt priority selection register IE Interrupt enable flag RBS Register bank selection register MBS Memory bank selecti...

Page 37: ...sed 2 In 2 MB 0 independently of how MBE and MBS are set 3 In 4 and 5 MB 15 independently of how MBE and MBS are set 4 6 to 11 indicate the areas that can be addressed 4 Explanation of number of machine cycles column S denotes the number of machine cycles required by skip operation when a skip instruction is executed The value of S varies as follows When no skip is made S 0 When the skipped instru...

Page 38: ... rpa1 2 XA HL 2 2 XA HL 1 HL A 1 1 HL A 1 HL XA 2 2 HL XA 1 A mem 2 2 A mem 3 XA mem 2 2 XA mem 3 mem A 2 2 mem A 3 mem XA 2 2 mem XA 3 A reg 2 2 A reg XA rp 2 2 XA rp reg1 A 2 2 reg1 A rp 1 XA 2 2 rp 1 XA XCH A HL 1 1 A HL 1 A HL 1 2 S A HL then L L 1 1 L 0 A HL 1 2 S A HL then L L 1 1 L FH A rpa1 1 1 A rpa1 2 XA HL 2 2 XA HL 1 A mem 2 2 A mem 3 XA mem 2 2 XA mem 3 A reg1 1 1 A reg1 XA rp 2 2 XA ...

Page 39: ...A A HL 1 carry XA rp 2 2 S XA XA rp carry rp 1 XA 2 2 S rp 1 rp 1 XA carry ADDC A HL 1 1 A CY A HL CY 1 XA rp 2 2 XA CY XA rp CY rp 1 XA 2 2 rp 1 CY rp 1 XA CY SUBS A HL 1 1 S A A HL 1 borrow XA rp 2 2 S XA XA rp borrow rp 1 XA 2 2 S rp 1 rp 1 XA borrow SUBC A HL 1 1 A CY A HL CY 1 XA rp 2 2 XA CY XA rp CY rp 1 XA 2 2 rp 1 CY rp 1 XA CY AND A n4 2 2 A A n4 A HL 1 1 A A HL 1 XA rp 2 2 XA XA rp rp 1...

Page 40: ... 1 CY 1 manipulation instruction CLR1 CY 1 1 CY 0 SKT CY 1 1 S Skip if CY 1 CY 1 NOT1 CY 1 1 CY CY Memory bit SET1 mem bit 2 2 mem bit 1 3 manipulation instructions fmem bit 2 2 fmem bit 1 4 pmem L 2 2 pmem7 2 L3 2 bit L1 0 1 5 H mem bit 2 2 H mem3 0 bit 1 1 CLR1 mem bit 2 2 mem bit 0 3 fmem bit 2 2 fmem bit 0 4 pmem L 2 2 pmem7 2 L3 2 bit L1 0 0 5 H mem bit 2 2 H mem3 0 bit 0 1 SKT mem bit 2 2 S ...

Page 41: ... CY CY v fmem bit 4 CY pmem L 2 2 CY CY v pmem7 2 L3 2 bit L1 0 5 CY H mem bit 2 2 CY CY v H mem3 0 bit 1 Branch BRNote 1 addr PC10 0 addr 6 instructions Select appropriate instruction among BR addr BRCB caddr and BR addr according to the assembler being used addr1 PC10 0 addr1 11 Select appropriate instruction among BR addr BRA addr1 BRCB caddr and BR addr1 according to the assembler being used a...

Page 42: ...SP 5 0 0 0 0 PC10 0 0 faddr SP SP 6 RETNote 1 3 PC10 0 SP 2 0 SP 3 SP 2 MBE RBE 0 0 SP 1 SP SP 4 MBE RBE SP 4 0 0 0 0 SP 1 PC10 0 SP 2 0 SP 3 SP 2 SP SP 6 RETSNote 1 3 S MBE RBE 0 0 SP 1 Unconditional PC10 0 SP 2 0 SP 3 SP 2 SP SP 4 then skip unconditionally 0 0 0 0 SP 1 PC10 0 SP 2 0 SP 3 SP 2 MBE RBE SP 4 SP SP 6 then skip unconditionally RETINote 1 3 MBE RBE 0 0 SP 1 PC10 0 SP 2 0 SP 3 SP 2 PSW...

Page 43: ...0 0 taddr 2 0 taddr 1 SP SP 4 When instruction other than TBR and Depending on TCALL instructions the reference taddr taddr 1 instruction is executed instruction 3 When TBR instruction 10 PC10 0 taddr 2 0 taddr 1 4 When TCALL instruction SP 6 SP 3 SP 4 PC10 0 SP 5 0 0 0 0 SP 2 MBE RBE PC10 0 taddr 2 0 taddr 1 SP SP 6 3 When instruction other than TBR and Depending on TCALL instructions the referen...

Page 44: ...All pins total 90 mA Operating ambient TA 40 to 85 C temperature Storage temperature Tstg 65 to 150 C Caution If any of the parameters exceeds the absolute maximum ratings even momentarily the quality of the product may be impaired The absolute maximum ratings are values that may physically damage the products Be sure to use the products within the ratings Capacitance TA 25 C VDD 0 V Parameter Sym...

Page 45: ...llation frequency is 4 19 MHz fX 6 0 MHz at 1 8 V VDD 2 7 V set the processor clock control register PCC to a value other than 0011 If the PCC is set to 0011 the rated machine cycle time of 0 95 µs is not satisfied 3 The oscillation stabilization time is the time required for oscillation to stabilize after application of VDD or after the STOP mode has been released Caution When using the oscillati...

Page 46: ...Kyocera Corp KBR 1000F Y 1 0 100 100 1 8 6 0 KBR 2 0MS 2 0 68 68 2 0 KBR 4 19MKC 4 19 1 8 Capacitor incorporated KBR 4 19MSB 33 33 PBRC4 19A PBRC4 19B Capacitor incorporated KBR 6 0MKC 6 0 KBR 6 0MSB 33 33 PBRC6 00A PBRC6 00B Capacitor incorporated Note If using Murata s CSB1000J 1 0 MHz as the ceramic resonator a limited resistor Rd 2 2 kΩ is required see figure below If using any other recommend...

Page 47: ... 8 V VDD 2 7 V 0 0 1 VDD V VIL2 Ports 6 8 KRREN 2 7 V VDD 6 0 V 0 0 2 VDD V RESET 1 8 V VDD 2 7 V 0 0 1 VDD V VIL3 X1 0 0 1 V High level output voltage VOH VDD 4 5 to 6 0 V IOH 1 0 mA VDD 1 0 V VDD 1 8 to 6 0 V IOH 100 µA VDD 0 5 V Low level output voltage VOL VDD 4 5 to 6 0 V Port 3 IOL 15 mA 0 6 2 0 V Ports 6 8 0 4 V IOL 1 6 mA VDD 1 8 to 6 0 V IOL 400 µA 0 5 V High level input leak ILIH1 VIN VD...

Page 48: ... VDD 3 0 V 10 Note 3 0 23 1 0 mA IDD2 C1 C2 22 pF HALT VDD 5 0 V 10 0 64 3 0 mA mode VDD 3 0 V 10 0 20 0 9 mA IDD3 X1 0 V VDD 1 8 to 6 0 V 5 µA STOP TA 25 C 1 µA mode VDD 3 0 V 10 0 1 3 µA TA 40 to 0 1 1 µA 40 C Notes 1 Does not include current fed to on chip pull up resistor 2 When processor clock control register PCC is set to 0011 during high speed mode 3 When PCC is set to 0000 during low spee...

Page 49: ... 1 machine cycle 1 8 V VDD 2 7 V 0 95 64 0 µs Interrupt input high and tINTH tINTL INT0 IM02 0 Note 2 µs low level widths IM02 1 10 µs KR4 KR7 10 µs RESET low level width tRSL 10 µs Notes 1 The CPU clock Φ cycle time minimum instruction execution time is determined by the oscillation frequency of the con nected resonator and external clock and the processor clock control register PCC The figure on...

Page 50: ...tXH 1 fX VDD 0 1 V 0 1 V X1 input VIH MIN VIL MAX VIH MIN VIL MAX VOH MIN VOL MAX VOH MIN VOL MAX AC Timing Test Points Excluding X1 Input Clock Timing Interrupt Input Timing RESET Input Timing INT0 KR4 7 tINTL tINTH RESET tRSL ...

Page 51: ... unstable operation at oscillation start 2 217 fx and 215 fx can be selected with mask option 3 Depends on setting of basic interval timer mode register BTM see table below BTM3 BTM2 BTM1 BTM0 Wait Time When fX 4 19 MHz When fX 6 0 MHz 0 0 0 220 fX Approx 250 ms 220 fX Approx 175 ms 0 1 1 217 fX Approx 31 3 ms 217 fX Approx 21 8 ms 1 0 1 215 fX Approx 7 81 ms 215 fX Approx 5 46 ms 1 1 1 213 fX App...

Page 52: ...a Retention Timing Standby release signal on releasing STOP mode by interrupt signal STOP mode Data retention mode Execution of STOP instruction VDD Standby release signal interrupt request tWAIT tSREL HALT mode Operation mode ...

Page 53: ... IDD vs VDD System clock 6 0 MHz crystal resonator 0 1 2 3 4 5 6 7 8 0 001 0 005 0 01 0 05 0 1 0 5 1 0 5 0 10 X1 X2 6 0 MHz 22 pF 22 pF PCC 0011 PCC 0010 PCC 0001 PCC 0000 HALT mode System clock Crystal resonator Supply Voltage VDD V Supply Current I DD mA TA 25 C ...

Page 54: ...ck 4 19 MHz crystal resonator 0 1 2 3 4 5 6 7 8 0 001 0 005 0 01 0 05 0 1 0 5 1 0 5 0 10 System clock HALT mode X1 X2 4 19 MHz 22 pF 22 pF PCC 0011 PCC 0010 PCC 0001 PCC 0000 Crystal resonator Supply Voltage VDD V Supply Current I DD mA TA 25 C ...

Page 55: ... 031 MAX 0 004 0 004 0 071 MAX 0 061 0 303 0 012 0 220 0 043 0 005 0 050 T P P20GM 50 300B C 4 P 3 3 7 NOTE Each lead centerline is located within 0 12 mm 0 005 inch of its true position T P at maximum material condition D 0 40 0 016 0 10 0 05 K 0 20 0 008 0 10 0 05 L 0 6 0 2 0 024 0 10 3 7 3 0 004 0 008 0 009 0 004 0 002 0 004 0 003 A C D G P detail of lead end F E B H I L K M J N M 1 10 11 20 ...

Page 56: ... T P 2 0 MAX 1 7 8 1 0 3 0 575 MAX 0 276 MAX 0 005 0 003 0 079 MAX 0 319 0 012 0 240 0 008 0 023 MAX NOTE L M 0 12 0 5 0 2 1 0 0 2 6 1 0 2 0 005 0 020 0 008 0 009 Each lead centerline is located within 0 12 mm 0 005 inch of its true position T P at maximum material condition 0 039 0 067 0 026 T P 0 15 0 10 0 05 0 006 0 004 0 002 N 0 10 0 004 0 012 0 004 0 005 0 30 0 10 0 125 0 075 0 009 0 008 C ...

Page 57: ...in plastic SOP 300 mil 1 27 mm pitch µPD754202GS A GJG 20 pin plastic shrink SOP 300 mil 0 65 mm pitch Soldering Method Soldering Conditions Symbol Infrared reflow Package peak temperature 235 C Reflow time 30 seconds or below IR35 00 2 at 210 C or higher Number of reflow processes Twice or less VPS Package peak temperature 215 C Reflow time 40 seconds or below VP15 00 2 at 200 C or higher Number ...

Page 58: ...be specified by software Total 13 System clock oscillator Ceramic crystal oscillator Boot time after reset 217 fX or 215 fX 215 fX selected by mask option Timer 4 channels 8 bit timer counter 3 channels can be used for 16 bit timer counter Basic interval timer watchdog timer 1 channel A D converter None 8 bit resolution 2 channels successive approximation register Operable VDD 1 8 V or higher Prog...

Page 59: ...er 3 30 to 5 inch 2HD µS5A10RA75X Ver 6 2Note IBM PC ATTM and Refer to 3 5 inch 2HC µS7B13RA75X compatible machines OS for IBM PC 5 inch 2HC µS7B10RA75X Device file Host machine Part number OS Supply media product name PC 9800 Series MS DOS 3 5 inch 2HD µS5A13DF754202 Ver 3 30 to 5 inch 2HD µS5A10DF754202 Ver 6 2Note IBM PC AT and Refer to 3 5 inch 2HC µS7B13DF754202 compatible machines OS for IBM...

Page 60: ...the host machine efficient debugging can be made IE 75300 R EM Emulation board for evaluating the application systems that use a µPD754202 It must be used with the IE 75000 R or IE 75001 R EP 754144GS R Emulation probe for the µPD754202 It must be connected to IE 75000 R or IE 75001 R and IE 75300 R EM It is supplied with the 20 pin flexible boards EV 9500GS 20 compatible with 20 pin plastic shrin...

Page 61: ...orted OS Version PC DOSTM Ver 5 02 to Ver 6 3 J6 1 VNote to J6 3 VNote MS DOS Ver 5 0 to Ver 6 22 5 0 VNote to J6 2 VNote IBM DOSTM J5 02 VNote Note Only English mode is supported Caution Ver 5 0 or later have the task swap function but it cannot be used for this software ...

Page 62: ...00 R EM User s Manual U11354J U11354E EP 754144GS R User s Manual U10695J U10695E Software RA75X Assembler Package User s Manual Operation EEU 731 EEU 1346 Language EEU 730 EEU 1363 Other related documents Document Name Document Number Japanese English IC Package Manual C10943X Semiconductor Device Mounting Technology Manual C10535J C10535E Quality Grades on NEC Semiconductor Devices C11531J C1153...

Page 63: ...63 µPD754202 754202 A MEMO ...

Page 64: ...nnection for CMOS device inputs can be cause of malfunction If no connection is provided to the input pins it is possible that an internal input level may be generated due to noise etc hence causing malfunction CMOS device behave differently than Bipolar or NMOS devices Input levels of CMOS devices must be fixed high or low by using a pull up or pull down circuitry Each unused pin should be connec...

Page 65: ...ds Tel 040 2445845 Fax 040 2444580 NEC Electronics France S A Velizy Villacoublay France Tel 01 30 67 58 00 Fax 01 30 67 58 99 NEC Electronics France S A Spain Office Madrid Spain Tel 01 504 2787 Fax 01 504 2860 NEC Electronics Germany GmbH Scandinavia Office Taeby Sweden Tel 08 63 80 820 Fax 08 63 80 388 Regional Information Some information contained in this document may vary from country to cou...

Page 66: ... be eliminated entirely To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device customers must incorporate sufficient safety measures in its design such as redundancy fire containment and anti failure features NEC devices are classified into the following three quality grades Standard Special and Specific The Specific quality grade applies ...

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