I²C-bus autosync deflection controller for PC monitors
TDA4857
67
When the protection mode is active, several pins of the
TDA4857 are forced into a defined state:
HDRV (horizontal driver output) is floating
BDRV (B+ control driver output) is floating
HUNLOCK (indicates, that the frequency-to-voltage con-
verter is out of lock) is floating (HIGH-level via external
pull-up resistor)
CLBL provides a continuous blanking signal
The capacitor at HPLL2 is discharged.
If the soft start procedure is activated via the I²C-bus, all of
these actions will be performed in a well defined sequence.
Power dip recognition
In standby mode the I²C-bus will only answer with an
acknowledge, when data is sent to control register with
subaddress 1AH. This register contains the standby and
soft start control bit.
If the I²C-bus master transmits data to another register, an
aknowledge is given after the chip address and the
subaddress; an acknowledge is not given after the data.
This indicates that only in soft start mode data can be stored
into normal registers.
If the supply voltage dips under 8.1 V the TDA4857 leaves
normal operation mode and changes into standby mode.
The microcontroller can check this state by sending data
into a register with the subaddress 0XH. The acknowledge
will only be given on the data if the TDA4857 is active.
Due to this behavior the start-up of the TDA4857 is defined
as follows. The first data that is transferred to the TDA4857
must be sent to the control register with subaddress 1AH.
Any other subaddress will not lead to an acknowledge. This
is a limitation in checking the I²C-busses of the monitor dur-
ing start-up.
Table 3 Activation of protection mode
ACTIVATION
RESET
Low supply voltage at pin10 increase supply voltage;
reload registers;
soft start via I²C-bus
Power dip, below 8.1 V
reload registers;
soft start via I²C-bus or via
supply voltage
X-ray protection XRAY
(pin 2) triggered
reload registers;
soft start via I²C-bus
HPLL2 (pin 30) externally
pulled to ground
release pin 30
Summary of Contents for MultiSync 75F-3
Page 56: ...DDC Flow Chart 53 ...
Page 57: ...Master I C Flow Chart 54 ...
Page 58: ...Master I C restart mode Flow Chart 55 ...
Page 59: ...Slave I C Flow Chart 56 ...
Page 61: ...BLOCK DIAGRAM I C bus autosync deflection controller for PC monitors TDA4857 58 ...
Page 71: ...I C bus autosync deflection controller for PC monitors TDA4857 68 APPLICATION INFORMATION ...
Page 77: ...74 8 Monolithic triple 13 5nS CRT driver ...
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