External Reset
A low level on the RESET/3.3V pin will generate reset.
Illegal address Reset
When the address bus of CPU goes to illegal address, a reset pulse will be generated.
The illegal address is defined as $0040h~$007Fh, $0300h~$0FFEh and $1000h~$7FFFh.
Low VDD Voltage Reset
When VDD is below 3.9V, an internal reset signal is generated. The reset signal will last 2.048 ms after
the voltage is higher than 3.9V.
Watchdog Timer Reset
If a time-out happens when watchdog timer is enabled, a reset pulse is generated. Please refer watchdog
timer section for more information.
RESET/3V3
Watchdog Timer Reset
Low VDD Reset
Illegal Address Reset
2.048ms
Timer
LATCH
CPU
Peripheral
Circuits
R
VDD
Address
6MHz
Fig. 1 Reset Signals
48
Summary of Contents for MultiSync 75F-3
Page 56: ...DDC Flow Chart 53 ...
Page 57: ...Master I C Flow Chart 54 ...
Page 58: ...Master I C restart mode Flow Chart 55 ...
Page 59: ...Slave I C Flow Chart 56 ...
Page 61: ...BLOCK DIAGRAM I C bus autosync deflection controller for PC monitors TDA4857 58 ...
Page 71: ...I C bus autosync deflection controller for PC monitors TDA4857 68 APPLICATION INFORMATION ...
Page 77: ...74 8 Monolithic triple 13 5nS CRT driver ...
Page 78: ...75 ...
Page 79: ...76 ...
Page 80: ...77 ...
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