NEC mPD789022 User Manual Download

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CHAPTER 12 RESET FUNCTION

User's Manual U11919EJ3V0UM00

177

Table 12-1. Hardware Status after Reset

Hardware

State after Reset

Program counter (PC)

Note 1

The contents of reset vector

tables (0000H and 0001H)

are set.

Stack pointer (SP)

Undefined

Program status word (PSW)

02H

Data memory

Undefined

Note 2

RAM

General-purpose register

Undefined

Note 2

Ports (P0 to P5) (Output latch)

00H

Port mode registers (PM0 to PM5)

FFH

Pull-up resistor option register (PUO)

00H

Processor clock control register (PCC)

02H

Oscillation settling time select register (OSTS)

04H

Timer counter (TM20)

0000H

Compare register (CR20)

FFFFH

Mode control register (TMC20)

00H

16-bit timer

Capture register (TCP20)

Undefined

Timer counter (TM00)

00H

Compare register (CR00)

00H

8-bit timer/event counter

Mode control register (TMC00)

00H

Timer clock select register (TCL2)

00H

Watchdog timer

Mode register (WDTM)

00H

Mode register (CSIM00)

00H

Asynchronous serial interface mode register (ASIM00)

00H

Asynchronous serial interface status register (ASIS00)

00H

Baud rate generator control register (BRGC00)

00H

Transmit shift register (TXS00)

FFH

Serial interface

Receive buffer register (RXB00)

Undefined

Request flag registers (IF0, IF1)

00H

Mask flag registers (MK0, MK1)

FFH

External interrupt mode register (INTM0)

00H

Interrupt

Key return mode register (KRM00)

00H

Notes 1. During reset input and oscillation settling time wait, only the PC contents among the hardware

statuses become undefined.

All other hardware remains unchanged after reset.

2. In post-reset values are retained in the standby mode.

Summary of Contents for mPD789022

Page 1: ... µ µ µPD789024 µ µ µ µPD789025 µ µ µ µPD789026 µ µ µ µPD78F9026A µ µ µ µPD789026 Subseries 8 Bit Single Chip Microcontrollers 1998 Printed in Japan Document No U11919EJ3V0UMJ1 3rd edition Date Published October 2000 N CP K 1996 1999 ...

Page 2: ...User s Manual U11919EJ3V0UM00 2 MEMO ...

Page 3: ...16 BIT TIMER 93 CHAPTER 7 8 BIT TIMER EVENT COUNTER 105 CHAPTER 8 WATCHDOG TIMER 115 CHAPTER 9 SERIAL INTERFACE 00 121 CHAPTER 10 INTERRUPT FUNCTIONS 149 CHAPTER 11 STANDBY FUNCTION 167 CHAPTER 12 RESET FUNCTION 175 CHAPTER 13 µ µ µ µPD78F9026A 179 CHAPTER 14 INSTRUCTION SET 185 APPENDIX A DEVELOPMENT TOOLS 195 APPENDIX B EMBEDDED SOFTWARE 205 APPENDIX C REGISTER INDEX 207 APPENDIX D REVISION HIST...

Page 4: ...ng a pull up or pull down circuitry Each unused pin should be connected to VDD or GND with a resistor if it is considered to have a possibility of being an output pin All handling related to the unused pins must be judged device by device and related specifications governing the devices 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note Power on does not necessarily define initial status of MOS de...

Page 5: ...defects in NEC semiconductor products customers must incorporate sufficient safety measures in their design such as redundancy fire containment and anti failure features NEC semiconductor products are classified into the following three quality grades Standard Special and Specific The Specific quality grade applies only to semiconductor products developed based on a customer designated quality ass...

Page 6: ...n of unused pins in Table 2 1 p 99 Addition of cautions on rewriting CR20 to Section 6 4 1 p 106 Addition of cautions on rewriting CR00 to Section 7 2 1 p 109 Addition of description of operation to Section 7 4 1 p 111 Addition of description of operation to Section 7 4 2 p 112 Addition of description of operation to Section 7 4 3 pp 180 to 183 Change of flash writer from Flashpro II to Flashpro I...

Page 7: ...tronics Germany GmbH Duesseldorf Germany Tel 0211 65 03 02 Fax 0211 65 03 490 NEC Electronics UK Ltd Milton Keynes UK Tel 01908 691 133 Fax 01908 670 290 NEC Electronics Italiana s r l Milano Italy Tel 02 66 75 41 Fax 02 66 75 42 99 NEC Electronics Germany GmbH Benelux Office Eindhoven The Netherlands Tel 040 2445845 Fax 040 2444580 NEC Electronics France S A Velizy Villacoublay France Tel 01 30 6...

Page 8: ...User s Manual U11919EJ3V0UM00 8 MEMO ...

Page 9: ...on Instruction set Instruction description How to Read This Manual It is assumed that the readers of this manual have general knowledge on electric engineering logic circuits and microcontrollers To understand the overall functions of the µPD789026 Subseries Read this manual in the order of the TABLE OF CONTENTS How to read register formats The name of a bit whose number is encircled is reserved f...

Page 10: ...bly Language U11599E U11599J RA78K0S Assembler Package Structured Assembly Language U11623E U11623J Operation U11816E U11816J CC78K0S C Compiler Language U11817E U11817J SM78K0S System Simulator Windows TM Based Reference U11489E U11489J SM78K Series System Simulator External Part User Open Interface Specifications U10092E U10092J ID78K0S Integrated Debugger Windows Based Reference U12901E U12901J...

Page 11: ... Device C11531E C11531J NEC Semiconductor Device Reliability Quality Control System C10983E C10983J Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge ESD C11892E C11892J Semiconductor Device Quality Control Reliability Handbook C12769J Guide for products Related to Microcomputer Other Companies U11416J Caution The related documents listed above are subject to change with...

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Page 13: ...40 to P47 Port 4 36 2 2 6 P50 to P53 Port 5 37 2 2 7 RESET 37 2 2 8 X1 X2 37 2 2 9 NC 37 2 2 10 VDD 37 2 2 11 VSS 37 2 2 12 VPP µPD78F9026A only 37 2 2 13 IC mask ROM model only 38 2 3 Pin Input Output Circuits and Connection of Unused Pins 39 CHAPTER 3 CPU ARCHITECTURE 41 3 1 Memory Space 41 3 1 1 Internal program memory space 46 3 1 2 Internal data memory internal high speed RAM space 47 3 1 3 S...

Page 14: ...on of Port Functions 83 4 4 1 Writing to I O port 83 4 4 2 Reading from I O port 83 4 4 3 Arithmetic operation of I O port 83 CHAPTER 5 CLOCK GENERATION CIRCUIT 85 5 1 Function of Clock Generation Circuit 85 5 2 Configuration of Clock Generation Circuit 85 5 3 Register Controlling Clock Generation Circuit 86 5 4 System Clock Oscillation Circuits 87 5 4 1 System clock oscillation circuit 87 5 4 2 D...

Page 15: ...f Watchdog Timer 119 8 4 1 Operation as watchdog timer 119 8 4 2 Operation as interval timer 120 CHAPTER 9 SERIAL INTERFACE 00 121 9 1 Serial Interface 00 Functions 121 9 2 Serial Interface 00 Configuration 121 9 3 Serial Interface 00 Control Register 125 9 4 Serial Interface 00 Operation 132 9 4 1 Operation stop mode 132 9 4 2 Asynchronous serial interface UART mode 134 9 4 3 3 wire serial I O mo...

Page 16: ... SET 185 14 1 Operation 185 14 1 1 Operand identifiers and writing methods 185 14 1 2 Description of Operation column 186 14 1 3 Description of Flag column 186 14 2 Operation List 187 14 3 Instructions Listed by Addressing Type 192 APPENDIX A DEVELOPMENT TOOLS 195 A 1 Language Processing Software 197 A 2 Flash Memory Writing Tools 198 A 3 Debugging Tools 199 A 3 1 Hardware 199 A 3 2 Software 200 A...

Page 17: ...4 Data to be Saved to Stack Memory 55 3 15 Data to be Restored from Stack Memory 55 3 16 General Purpose Register Configuration 56 4 1 Port Types 69 4 2 Block Diagram of P00 to P07 71 4 3 Block Diagram of P10 to P17 72 4 4 Block Diagram of P20 73 4 5 Block Diagram of P21 74 4 6 Block Diagram of P22 75 4 7 Block Diagram of P30 to P32 76 4 8 Block Diagram of P40 to P47 77 4 9 Block Diagram of P50 78...

Page 18: ... Operation Timing with Rising Edge Specified 111 7 6 Square Wave Output Timing 113 7 7 8 Bit Timer Counter 00 Start Timing 114 7 8 External Event Counter Operation Timing 114 8 1 Block Diagram of Watchdog Timer 116 8 2 Timer Clock Select Register 2 Format 117 8 3 Watchdog Timer Mode Register Format 118 9 1 Block Diagram of Serial Interface 00 122 9 2 Block Diagram of Baud Rate Generator 123 9 3 Se...

Page 19: ...ion Execution 163 10 14 Example of Nesting 164 11 1 Oscillation Settling Time Select Register Format 168 11 2 Releasing HALT Mode by Interrupt 170 11 3 Releasing HALT Mode by RESET Input 171 11 4 Releasing STOP Mode by Interrupt 173 11 5 Releasing STOP Mode by RESET Input 174 12 1 Block Diagram of Reset Function 175 12 2 Reset Timing by RESET Input 176 12 3 Reset Timing by Overflow in Watchdog Tim...

Page 20: ...e of 8 Bit Timer Event Counter 00 105 7 3 Configuration of 8 Bit Timer Event Counter 00 106 7 4 Interval Time of 8 Bit Timer Event Counter 00 109 7 5 Square Wave Output Range of 8 Bit Timer Event Counter 00 112 8 1 Inadvertent Loop Detection Time of Watchdog Timer 115 8 2 Interval Time 115 8 3 Configuration of Watchdog Timer 116 8 4 Inadvertent Loop Detection Time of Watchdog Timer 119 8 5 Interva...

Page 21: ...ode Operating Status 169 11 2 Operation after Release of HALT Mode 171 11 3 STOP Mode Operating Status 172 11 4 Operation after Release of STOP Mode 174 12 1 Hardware Status after Reset 177 13 1 Differences between µPD78F9026A and Mask ROM Models 179 13 2 Communication Modes 180 13 3 Major Flash Memory Programming Functions 181 13 4 Setting Example When Using PG FP3 183 14 1 Operand Identifiers an...

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Page 23: ...struction execution time from high speed 0 4 µs with 5 0 MHz system clock to slow 1 6 µs with 5 0 MHz system clock I O port 34 lines Serial interface 1 channel 3 wire serial I O mode UART mode selection Timer 3 channels 16 bit timer 1 channel 8 bit timer event counter 1 channel Watchdog timer 1 channel Vectored interrupt 10 Supply voltage VDD 1 8 to 5 5 V Operating ambient temperature TA 40 C to 8...

Page 24: ...nk DIP 600 mil Mask ROM µPD789025GB 3BS MTX 44 pin plastic QFP 10 10 mm resin thickness 2 7 mm Mask ROM µPD789025GB 8ES 44 pin plastic LQFP 10 10 mm resin thickness 1 4 mm Mask ROM µPD789026CU 42 pin plastic shrink DIP 600 mil Mask ROM µPD789026GB 3BS MTX 44 pin plastic QFP 10 10 mm resin thickness 2 7 mm Mask ROM µPD789026GB 8ES 44 pin plastic LQFP 10 10 mm resin thickness 1 4 mm Mask ROM µPD78F9...

Page 25: ...2 P51 TO2 P50 TI0 TO0 P32 INTP2 CPT2 P31 INTP1 P30 INTP0 P22 RxD SI0 P21 TxD SO0 P20 ASCK SCK0 P07 P06 P05 P04 P03 P02 P01 P00 VDD1 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 VSS0 X1 X2 IC VPP P40 KR0 P41 KR1 P42 KR2 P43 KR3 P44 KR4 P45 KR5 P46 KR6 P47 KR7 P10 P11 P12 P13 P14 P15 P16 P17 VSS1 Caution Connect the IC pin directly to VSS0 or VSS1 Remark An item in parentheses appl...

Page 26: ...9026AGB 8ES 1 2 3 4 5 6 7 8 9 10 11 P12 P11 P10 P47 KR7 P46 KR6 P45 KR5 P44 KR4 P43 KR3 P42 KR2 P41 KR1 P40 KR0 NC IC V PP X2 X1 V SS0 V DD1 RESET P53 P52 P51 TO2 P50 TI0 TO0 33 32 31 30 29 28 27 26 25 24 23 P03 P04 P05 P06 P07 P20 ASCK SCK0 P21 TxD SO0 P22 RxD SI0 P30 INTP0 P31 INTP1 P32 INTP2 CPT2 P13 P14 P15 P16 P17 V SS1 V DD1 NC P00 P01 P02 44 43 42 41 40 39 38 37 36 35 34 12 13 14 15 16 17 1...

Page 27: ...ial Clock INTP0 to INTP2 Interrupt from Peripherals SI0 Serial Input KR0 to KR7 Key Return SO0 Serial Output NC Non connection TI0 Timer Input P00 to P07 Port 0 TO0 TO2 Timer Output P10 to P17 Port 1 TxD Transmit Data P20 to P22 Port 2 VDD0 VDD1 Power Supply P30 to P32 Port 3 VPP Programming Power Supply P40 to P47 Port 4 VSS0 VSS1 Ground P50 to P53 Port 5 X1 X2 Crystal ...

Page 28: ...ng the subsystem clock to the PD789026 30 pin 30 pin 30 pin 30 pin PD789124A PD789134A PD789217AY PD789197AY PD789177 PD789167 30 pin 30 pin PD789104A PD789114A With built in EEPROM in the PD789104A Device developed by enhancing the A D function of the PD789146 Device developed by enhancing the A D funciton of the PD789427 With built in UART bus and dot LCD 80 pin 80 pin 88 pin Device developed by...

Page 29: ...µPD789146 8 K to 16 K 4 ch EEPROM on chip µPD789134A 4 ch µPD789124A 4 ch RC oscillation µPD789114A 4 ch General compact A D µPD789104A 2 K to 8 K 1 ch 1 ch 1 ch 4 ch 1 ch UART 1 ch 20 1 8 V Inverter control µPD789842 8 K to 16 K 3 ch Note 1 ch 1 ch 8 ch 1 ch UART 1 ch 30 4 0 V µPD789830 24 K 1 ch 30 2 7 V µPD789417A 7 ch 43 µPD789407A 12 K to 24 K 3 ch 7 ch 1 ch UART 1 ch µPD789457 4 ch µPD789447...

Page 30: ...1 SERIAL INTERFACE 00 SI0 RxD P22 SCK0 ASCK P20 INTERRUPT CONTROL SYSTEM CONTROL INTP0 P30 to INTP2 CPT2 P32 KR0 P40 to KR7 P47 X1 X2 RESET PORT0 P00 to P07 PORT1 P10 to P17 PORT2 P20 to P22 PORT3 WATCHDOG TIMER P30 to P32 PORT4 P40 to P47 PORT5 P50 to P53 Remarks 1 The internal ROM and internal high speed RAM capacities differ depending on the product 2 An item in parentheses applies to the µPD78...

Page 31: ...Watchdog timer 1 channel Timer output 2 Maskable Internal 5 External 4 Vectored interrupt source Non maskable Internal 1 Power supply voltage VDD 1 8 to 5 5 V Operating ambient temperature TA 40 C to 85 C Package 44 pin plastic QFP 10 10 mm resin thickness 2 7 mm 44 pin plastic LQFP 10 10 mm resin thickness 1 4 mm 42 pin plastic shrink DIP 600 mil 44 pin plastic QFP 10 10 mm resin thickness 2 7 mm...

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Page 33: ...its When used as input port on chip pull up resistor can be connected by setting of the pull up resistor option register PUO LEDs can be driven directly Input SI0 RxD P30 INTP0 P31 INTP1 P32 Input output Port 3 3 bit I O port I O specifiable in 1 bit units When used as input port on chip pull up resistor can be connected by setting of the pull up resistor option register PUO LEDs can be driven dir...

Page 34: ... data input Input P22 SI0 TxD Output Asynchronous serial interface serial data output Input P21 SO0 TO2 Output 16 bit timer TM20 output Input P51 CPT2 Input 16 bit timer capture edge input Input P32 INTP2 TI0 Input External count clock input to 8 bit timer TM00 Input P50 TO0 TO0 Output 8 bit timer TM00 output Input P50 TI0 X1 Input X2 System clock oscillation crystal connection RESET Input System ...

Page 35: ...n to input output the data and clock of the serial interface This port can drive LEDs directly Port 2 can be specified in the following operation modes in bit wise 1 Port mode In this mode port 2 functions as a 3 bit I O port Port 2 can be set in the input or output mode in 1 bit units by using the port mode register 2 PM2 When the port is used as an input port an on chip pull up resistor can be u...

Page 36: ...ns as the external interrupt input a INTP0 to INTP2 These pins input external interrupt for which effective edges rising edge falling edge and both the rising and falling edges can be specified b CPT2 This is a capture edge input pin 2 2 5 P40 to P47 Port 4 These pins constitute an 8 bit I O port In addition they also function as key return signal detection This port can drive LEDs directly Port 4...

Page 37: ...r input output a TI0 This is the external clock input pin for 8 bit timer event counter b TO0 This is an 8 bit timer output pin C TO2 This is a 16 bit timer output pin 2 2 7 RESET This pin inputs an active low system reset signal 2 2 8 X1 X2 These pins are used to connect a crystal resonator for system clock oscillation To supply an external clock input the clock to X1 and input the inverted signa...

Page 38: ...n the normal operating mode directly connect the IC pin to the VSS0 or VSS1 pin with as short a wire as possible If a potential difference is generated between the IC pin and VSS0 or VSS1 pin due to a long wiring length between these pins or external noise is superimposed on the IC pin the user program may not run correctly Connect the IC pin directly to the VSS0 or VSS1 pin VSS0 or VSS1 IC Keep s...

Page 39: ...ng of Unused Pins Pin Name I O Circuit Type Input Output Recommended Connection for Unused Pins P00 to P07 P10 to P17 5 X P20 ASCK SCK0 8 J P21 TxD SO0 5 X P22 RxD SI0 P30 INTP0 P31 INTP1 P32 INTP2 CPT2 P40 KR0 to P47 KR7 P50 TI0 TO0 8 J P51 TO2 P52 P53 5 X Input output Input Connect these pins to the VDD0 VDD1 VSS0 or VSS1 pin via respective resistors Output Leave these pins open RESET 2 Input NC...

Page 40: ... of Pin Input Output Circuits Schmitt triggered input with hysteresis characteristics Type 2 IN VDD P ch IN OUT VDD0 P ch N ch Pullup enable Output data Output disable Type 8 J IN OUT VDD0 P ch VDD0 P ch N ch Pullup enable Output data Output disable Type 5 X Port read VSS0 ...

Page 41: ... show the memory maps Figure 3 1 Memory Map µ µ µ µPD789022 FFFFH FF00H FEFFH FE00H FDFFH 1000H 0FFFH 0000H 0FFFH 0000H 0080H 007FH 0040H 003FH 002CH 002BH Data Memory Space Program Memory Space Special Function Registers 256 8 bits Internal High Speed RAM 256 8 bits Reserved Internal ROM 4 096 8 bits Program Area CALLT Table Area Program Area Vector Table Area ...

Page 42: ...FFH FF00H FEFFH FE00H FDFFH 2000H 1FFFH 0000H 1FFFH 0000H 0080H 007FH 0040H 003FH 002CH 002BH Data Memory Space Program Memory Space Special Function Registers 256 8 bits Internal High Speed RAM 256 8 bits Reserved Internal ROM 8 192 8 bits Program Area CALLT Table Area Program Area Vector Table Area ...

Page 43: ...FFH FF00H FEFFH FD00H FCFFH 3000H 2FFFH 0000H 2FFFH 0000H 0080H 007FH 0040H 003FH 002CH 002BH Data Memory Space Program Memory Space Special Function Registers 256 8 bits Internal High Speed RAM 512 8 bits Reserved Internal ROM 12 288 8 bits Program Area CALLT Table Area Program Area Vector Table Area ...

Page 44: ...FFH FF00H FEFFH FD00H FCFFH 4000H 3FFFH 0000H 3FFFH 0000H 0080H 007FH 0040H 003FH 002CH 002BH Data Memory Space Program Memory Space Special Function Registers 256 8 bits Internal High Speed RAM 512 8 bits Reserved Internal ROM 16 384 8 bits Program Area CALLT Table Area Program Area Vector Table Area ...

Page 45: ...FF00H FEFFH FD00H FCFFH 4000H 3FFFH 0000H 3FFFH 0000H 0080H 007FH 0040H 003FH 002CH 002BH Data Memory Space Program Memory Space Special Function Registers 256 8 bits Internal High Speed RAM 512 8 bits Reserved Internal Flash Memory 16 384 8 bits Program Area CALLT Table Area Program Area Vector Table Area ...

Page 46: ...ated to the internal program memory space 1 Vector table area A 44 byte area of addresses 0000H to 002BH is reserved as a vector table area This area stores program start addresses to be used when branching by the RESET input or an interrupt request generation Of a 16 bit program address the low order 8 bits are stored in an even address and the high order 8 bits are stored in an odd address Table...

Page 47: ...lowing capacity on each product The internal high speed RAM can also be used as a stack memory Table 3 3 Internal High Speed RAM Capacity Part Number Capacity µPD789022 µPD789024 256 8 bits µPD789025 µPD789026 µPD78F9026A 512 8 bits 3 1 3 Special function register SFR area Special function registers SFRs of on chip peripheral hardware are allocated to an area of FF00H to FFFFH see Table 3 4 ...

Page 48: ... the functions of the special function registers SFR and other registers Figures 3 6 through 3 10 show the data memory addressing modes Notes 1 With µPD789022 or µPD789024 2 With µPD789025 µPD789026 or µPD78F9026A Figure 3 6 Data Memory Addressing µ µ µ µPD789022 FFFFH 1000H 0FFFH 0000H FF00H FEFFH FF20H FF1FH FE20H FE1FH Special Function Registers SFR 256 8 bits Internal High Speed RAM 256 8 bits...

Page 49: ... µ µPD789024 FFFFH 2000H 1FFFH 0000H FF00H FEFFH FF20H FF1FH FE20H FE1FH Special Function Registers SFR 256 8 bits Internal High Speed RAM 256 8 bits Reserved Internal ROM 8 192 8 bits SFR Addressing Short Direct Addressing Direct Addressing Register Indirect Addressing Based Addressing FE00H FDFFH ...

Page 50: ...µ µPD789025 FFFFH 3000H 2FFFH 0000H FF00H FEFFH FF20H FF1FH FE20H FE1FH Special Function Registers SFR 256 8 bits Internal High Speed RAM 512 8 bits Reserved Internal ROM 12 288 8 bits SFR Addressing Short Direct Addressing Direct Addressing Register Indirect Addressing Based Addressing FD00H FCFFH ...

Page 51: ...µ µPD789026 FFFFH 4000H 3FFFH 0000H FF00H FEFFH FF20H FF1FH FE20H FE1FH Special Function Registers SFR 256 8 bits Internal High Speed RAM 512 8 bits Reserved Internal ROM 16 384 8 bits SFR Addressing Short Direct Addressing Direct Addressing Register Indirect Addressing Based Addressing FD00H FCFFH ...

Page 52: ...78F9026A FFFFH 4000H 3FFFH 0000H FD00H FCFFH FF00H FEFFH FF20H FF1FH FE20H FE1FH Special Function Registers SFR 256 8 bits Internal High Speed RAM 512 8 bits Reserved Internal Flash Memory 16 384 8 bits SFR Addressing Short Direct Addressing Direct Addressing Register Indirect Addressing Based Addressing ...

Page 53: ...f bytes of the instruction to be fetched When a branch instruction is executed immediate data or register contents is set RESET input sets the reset vector table values at addresses 0000H and 0001H to the program counter Figure 3 11 Program Counter Configuration 2 Program status word PSW The program status word is an 8 bit register consisting of various flags to be set reset by instruction executi...

Page 54: ...rce This flag is reset to 0 upon DI instruction execution or interrupt acknowledgment and is set to 1 upon EI instruction execution b Zero flag Z When the operation result is zero this flag is set to 1 It is reset to 0 in all other cases c Auxiliary carry flag AC If the operation result has a carry from bit 3 or a borrow at bit 3 this flag is set to 1 It is reset to 0 in all other cases d Carry fl...

Page 55: ...ntents undefined be sure to initialize the SP before instruction execution Figure 3 14 Data to be Saved to Stack Memory Figure 3 15 Data to be Restored from Stack Memory 0 15 SP14 SP15 SP SP13 SP12 SP11 SP10 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 Interrupt PSW PC15 to PC8 PC15 to PC8 PC7 to PC0 Lower Half Register Pairs SP SP _ 2 SP _ 2 CALL CALLT Instructions PUSH rp Instruction SP _ 1 SP SP SP ...

Page 56: ... 8 bit registers in pairs can be used as a 16 bit register AX BC DE and HL They can be written in terms of functional names X A C B E D L H AX BC DE and HL and absolute names R0 to R7 and RP0 to RP3 Figure 3 16 General Purpose Register Configuration a Absolute Names b Functional Names R0 15 0 7 0 16 Bit Processing 8 Bit Processing RP3 RP2 RP1 RP0 R1 R2 R3 R4 R5 R6 R7 X 15 0 7 0 16 Bit Processing 8...

Page 57: ... operand sfr This manipulation can also be specified with an address 16 bit manipulation Writes a symbol reserved with assembler for the 16 bit manipulation instruction operand When specifying an address write an even address Table 3 4 lists the special function register The meanings of the symbols in this table are as follows Symbol Indicates the addresses of the incorporated special function reg...

Page 58: ...Ο FF21H Port mode register 1 PM1 Ο Ο FF22H Port mode register 2 PM2 Ο Ο FF23H Port mode register 3 PM3 Ο Ο FF24H Port mode register 4 PM4 Ο Ο FF25H Port mode register 5 PM5 Ο Ο FFH FF42H Timer clock select register 2 TCL2 R W Ο 00H FF50H 8 bit compare register 00 CR00 W Ο Undefined FF51H 8 bit timer counter 00 TM00 R Ο FF53H 8 bit timer mode control register 00 TMC00 Ο Ο FF5BH 16 bit timer mode co...

Page 59: ... IF0 Ο Ο FFE1H Interrupt request flag register 1 IF1 Ο Ο 00H FFE4H Interrupt mask flag register 0 MK0 Ο Ο FFE5H Interrupt mask flag register 1 MK1 Ο Ο FFH FFECH External interrupt mode register 0 INTM0 Ο FFF5H Key return mode register 00 KRM00 Ο Ο FFF7H Pull up resistor option register PUO Ο Ο FFF9H Watchdog timer mode register WDTM Ο Ο 00H FFFAH Oscillation settling time select register OSTS Ο 04...

Page 60: ... 1 Relative addressing Function The value obtained by adding 8 bit immediate data displacement value jdisp8 of an instruction code to the start address of the following instruction is transferred to the program counter PC and branched The displacement value is treated as signed two s complement data 128 to 127 and bit 7 becomes a sign bit In other words the range of branch in relative addressing i...

Page 61: ...n word is transferred to the program counter PC and branched This function is carried out when the CALL addr16 or BR addr16 instruction is executed CALL addr16 and BR addr16 instructions can branch to all the memory spaces Illustration In case of CALL addr16 or BR addr16 instruction 15 0 PC 8 7 7 0 CALL or BR Low Addr High Addr ...

Page 62: ...r5 instruction is executed This instruction can refer to the address stored in the memory table 40H to 7FH and branch to all the memory spaces Illustration 15 1 15 0 PC 7 0 Low Addr High Addr Memory Table Effective Address 1 Effective Address 0 1 0 0 0 0 0 0 0 0 8 7 8 7 6 5 0 0 0 0 1 7 6 5 1 0 ta4 0 Instruction Code 3 3 4 Register addressing Function Register pair AX contents to be specified with ...

Page 63: ...ring instruction execution 3 4 1 Direct addressing Function The memory indicated by immediate data in an instruction word is directly addressed Operand format Identifier Description addr16 Label or 16 bit immediate data Example MOV A FE00H When setting addr16 to FE00H Instruction Code 0 0 1 0 1 0 0 1 OP Code 0 0 0 0 0 0 0 0 00H 1 1 1 1 1 1 1 0 FEH Illustration 7 0 OP Code addr16 Low addr16 High Me...

Page 64: ...re register of the timer event counter are mapped and these SFRs can be manipulated with a small number of bytes and clocks When 8 bit immediate data is at 20H to FFH bit 8 of an effective address is set to 0 When it is at 00H to 1FH bit 8 is set to 1 See Illustration Operand format Identifier Description saddr Label or FE20H to FF1FH immediate data saddrp Label or FE20H to FF1FH immediate data ev...

Page 65: ...d This addressing is applied to the 240 byte spaces FF00H to FFCFH and FFE0H to FFFFH However the SFR mapped at FF00H to FF1FH can also be accessed with short direct addressing Operand format Identifier Description sfr Special function register name Example MOV PM0 A When selecting PM0 for sfr Instruction Code 1 1 1 0 0 1 1 1 0 0 1 0 0 0 0 0 Illustration 15 0 SFR Effective Address 1 1 1 1 1 1 1 8 ...

Page 66: ...format is executed When an 8 bit register is specified one of the eight registers is specified with 3 bits in the instruction code Operand format Identifier Description r X A C B E D L H rp AX BC DE HL r and rp can be written with absolute names R0 to R7 and RP0 to RP3 as well as function names X A C B E D L H AX BC DE and HL Example MOV A C When selecting the C register for r Instruction Code 0 0...

Page 67: ...o be accessed is specified with the register pair specification code in the instruction code This addressing can be carried out for all the memory spaces Operand format Identifier Description DE HL Example MOV A DE When selecting register pair DE Instruction Code 0 0 1 0 1 0 1 1 Illustration 15 0 8 D 7 E 0 7 7 0 A DE The contents of addressed memory are transferred Memory address specified by regi...

Page 68: ...the memory spaces Operand format Identifier Description HL byte Example MOV A HL 10H When setting byte to 10H Instruction Code 0 0 1 0 1 1 0 1 0 0 0 1 0 0 0 0 3 4 7 Stack addressing Function The stack area is indirectly addressed with the stack pointer SP contents This addressing method is automatically employed when the PUSH POP subroutine call and RETURN instructions are executed or the register...

Page 69: ...e ports shown in Figure 4 1 enabling various methods of control Alternate functions are provided in addition to the digital I O port function For more information on these alternate functions see Chapter 2 Figure 4 1 Port Types Port 2 P20 P22 P30 P32 P40 P47 P50 P53 P00 P07 P10 P17 Port 3 Port 0 Port 1 Port 4 Port 5 ...

Page 70: ...en used as input port on chip pull up resistor can be connected by setting of the pull up resistor option register PUO LEDs can be driven directly Input SI0 RxD P30 INTP0 P31 INTP1 P32 Input output Port 3 3 bit I O port I O specifiable in 1 bit units When used as input port on chip pull up resistor can be connected by setting of the pull up resistor option register PUO LEDs can be driven directly ...

Page 71: ...port with output latch Port 0 can be specified in the input or output mode in 1 bit units by using the port mode register 0 PM0 When using P00 to P07 pins as input port pins on chip pull up resistors can be connected in 8 bit units by using the pull up resistor option register PUO RESET input sets port 0 to input mode Figure 4 2 shows the block diagram of port 0 Figure 4 2 Block Diagram of P00 to ...

Page 72: ...put port pins on chip pull up resistors can be connected in 8 bit units by using the pull up resistor option register PUO RESET input sets port 1 to input mode Figure 4 3 shows the block diagram of port 1 Figure 4 3 Block Diagram of P10 to P17 Internal Bus WRPUO RD WRPORT WRPM Output Latch P10 to P17 PM10 to PM17 Selector PUO1 VDD0 P ch P10 to P17 PUO Pull up resistor option register PM Port mode ...

Page 73: ...ed as the data I O and clock I O pins of the serial interface RESET input sets port 2 to input mode Figures 4 4 through 4 6 show the block diagrams of port 2 Caution When using the pins of port 2 as the serial interface the I O mode and output latch must be set according to the function to be used For details of the settings see Table 9 2 Figure 4 4 Block Diagram of P20 Internal Bus VDD0 P ch P20 ...

Page 74: ...M00 74 Figure 4 5 Block Diagram of P21 Internal Bus WRPUO RD WRPORT WRPM Output Latch P21 PM21 Selector PUO2 VDD0 P ch P21 TxD SO0 Alternate Function PUO Pull up resistor option register PM Port mode register RD Port 2 read signal WR Port 2 write signal ...

Page 75: ...M00 75 Figure 4 6 Block Diagram of P22 Internal Bus WRPUO RD WRPORT WRPM Output Latch P22 PM22 Selector PUO2 VDD0 P ch P22 RxD SI0 Alternate Function PUO Pull up resistor option register PM Port mode register RD Port 2 read signal WR Port 2 write signal ...

Page 76: ... by using the pull up resistor option register PUO The pins of this port are also used as the external interrupt input and capture edge input RESET input sets port 3 to input mode Figure 4 7 shows the block diagram of port 3 Figure 4 7 Block Diagram of P30 to P32 Internal Bus WRPUO RD WRPORT WRPM Output Latch P30 to P32 PM30 to PM32 Selector PUO3 VDD0 P ch P30 INTP0 P31 INTP1 P32 INTP2 CPT2 Altern...

Page 77: ...o used as the key return input RESET input sets port 4 to input mode Figure 4 8 shows the block diagram of port 4 Caution When using port 4 for the key return function it is necessary to set key return mode register 00 For details of the settings see Section 10 3 5 Figure 4 8 Block Diagram of P40 to P47 WRKRM00 Internal Bus VDD0 P40 KR0 to P47 KR7 WRPUO RD WRPORT WRPM PUO4 Alternate Function Outpu...

Page 78: ...ected in 4 bit units by using the pull up resistor option register PUO The pins of this port are also used as the data I O pins of the timer RESET input sets port 5 to input mode Figures 4 9 through 4 11 show the block diagrams of port 5 Figure 4 9 Block Diagram of P50 Internal Bus VDD0 P ch P50 TI0 TO0 WRPUO RD WRPORT WRPM PUO5 Alternate Function Output Latch P50 PM50 Alternate Function Selector ...

Page 79: ...UM00 79 Figure 4 10 Block Diagram of P51 Internal Bus VDD0 P ch P51 TO2 WRPUO RD WRPORT WRPM PUO5 Output Latch P51 PM51 Alternate Function Selector PUO Pull up resistor option register PM Port mode register RD Port 5 read signal WR Port 5 write signal ...

Page 80: ...V0UM00 80 Figure 4 11 Block Diagram of P52 and P53 Internal Bus WRPUO RD WRPORT WRPM PUO5 Ouput Latch P52 P53 PM52 PM53 VDD0 P ch P52 P53 Selector PUO Pull up resistor option register PM Port mode register RD Port 5 read signal WR Port 5 write signal ...

Page 81: ...t input when the port function output mode is specified and the output level is changed the interrupt request flag is set When the output mode is used therefore the interrupt mask flag should be set to 1 beforehand Table 4 3 Port Mode Register and Output Latch Settings when Using Alternate Functions Alternate Function Pin Name Name Input Output PM P P30 INTP0 Input 1 P31 INTP1 Input 1 INTP2 Input ...

Page 82: ...or 8 bit memory manipulation instruction RESET input clears PUO to 00H Figure 4 13 Pull Up Resistor Option Register Format PMmn 0 Output mode output buffer ON Input mode output buffer OFF 1 Pmn Pin Input Output Mode Selection m 0 1 4 n 0 to 7 m 2 3 n 0 to 2 m 5 n 0 to 3 PM07 PM06 PM05 PM04 PM03 PM02 PM01 PM00 PM0 7 6 5 4 Symbol Address After Reset R W FF20H FFH R W 3 2 1 0 PM17 PM16 PM15 PM14 PM13...

Page 83: ...h of the pin that is set in the input mode and not subject to manipulation become undefined 4 4 2 Reading from I O port 1 In output mode The contents of an output latch can be read by using a transfer instruction The contents of the output latch are not changed 2 In input mode The status of a pin can be read by using a transfer instruction The contents of the output latch are not changed 4 4 3 Ari...

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Page 85: ...d by executing the STOP instruction 5 2 Configuration of Clock Generation Circuit The clock generation circuit consists of the following hardware Table 5 1 Configuration of Clock Generation Circuit Item Configuration Control register Processor clock control register PCC Oscillator System clock oscillator Figure 5 1 Block Diagram of Clock Generation Circuit X1 X2 fX Prescaler 22 fX Selector PCC1 In...

Page 86: ...et with a 1 bit or 8 bit memory manipulation instruction RESET input sets PCC to 02H Figure 5 2 Processor Clock Control Register Format CPU Clock fCPU Selection PCC1 0 1 fX 0 2 s fX 22 0 8 s µ µ 0 0 0 0 0 0 PCC1 0 PCC 7 6 5 4 Symbol Address After Reset R W FFFBH 02H R W 3 2 1 0 Caution Be sure to set bit 0 and bits 2 to 7 to 0 Remarks 1 fX System clock oscillation frequency 2 The parenthesized val...

Page 87: ... a Crystal or ceramic oscillation b External clock VSS0 VSS1 X1 X2 Crystal or Ceramic Resonator External Clock X1 X2 Caution When using the system clock oscillator circuit to avoid influence of wiring capacity etc wire the portion enclosed by the broken line in Figure 5 3 as follows Keep the wiring length as short as possible Do not cross the wiring with any other signal lines Do not route the wir...

Page 88: ...ER 5 CLOCK GENERATION CIRCUIT User s Manual U11919EJ3V0UM00 88 Figure 5 4 Incorrect Examples of Resonator Connection 1 2 a Too long wiring b Crossed signal line VSS0 VSS1 X1 X2 PORTn n 0 to 5 VSS0 VSS1 X1 X2 ...

Page 89: ...ing current d Current flowing through ground line of oscillation circuit potential at points A B and C fluctuates VSS0 VSS1 X1 X2 High Current VSS0 VSS1 X1 X2 Pmn VDD A B C High Current e Signal is extracted VSS0 VSS1 X1 X2 5 4 2 Divider circuit The divider circuit divides the output of the system clock oscillation circuit fX to generate various clocks ...

Page 90: ...gister PCC as follows a The slow mode 2 fCPU 1 6 µs at 5 0 MHz operation of the system clock is selected when the RESET signal is generated PCC 02H While a low level is input to the RESET pin oscillation of the system clock is stopped b Two types of CPU clocks fCPU 0 2 µs and 0 8 µs at 5 0 MHz operation can be selected by the PCC setting c Two standby modes STOP and HALT can be used d The clock to...

Page 91: ...ion time of the CPU clock before switching 5 6 2 Switching CPU clock The following figure illustrates how the CPU clock switches Figure 5 5 Switching CPU Clock VDD RESET CPU Clock Slow Operation High Speed Operation Wait 6 55 ms at 5 0 MHz operation Internal Reset Operation 1 The CPU is reset when the RESET pin is made low on power application The effect of resetting is released when the RESET pin...

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Page 93: ...er interrupt Timer output Count value capture 1 Timer interrupt An interrupt is generated when a count value and compare value matches 2 Timer output Timer output control is possible when a count value and compare value matches 3 Count value capture A TM20 count value is latched synchronizing with the capture trigger and retained ...

Page 94: ...TO20 Control register 16 bit timer mode control register 20 TMC20 Port mode register 5 PM5 Figure 6 1 Block Diagram of 16 Bit Timer 20 CPT2 P32 INTP2 Internal Bus Internal Bus 16 Bit Timer Mode Control Register 20 TMC20 16 Bit Timer Mode Control Register 20 TOF20 CPT201 CPT200 TOC20 TCL201 TCL200 TOE20 fX 22 fX 26 Edge Detection Circuit 16 Bit Capture Register 20 TCP20 16 Bit Counter Read Buffer 1...

Page 95: ...put RESET input clears this register to 0000H and after that to be in free running Cautions 1 The count value after releasing stop becomes undefined because the count operation is executed during the oscillation settling time 2 This register is manipulated with a 16 bit memory manipulation instruction however an 8 bit memory manipulation instruction can be used When manipulated with an 8 bit memor...

Page 96: ...ontrol 16 bit timer 20 16 bit timer mode control register 20 TMC20 Port mode register 5 PM5 1 16 bit timer mode control register 20 TMC20 16 bit timer mode control register 20 TMC20 controls the setting of a count clock capture edge etc TMC20 is set with a 1 bit or 8 bit memory manipulation instruction RESET input clears TMC20 to 00H ...

Page 97: ... TCL201 0 0 TCL200 0 1 fX 22 1 25 MHz fX 26 78 1 kHz 16 bit Timer 20 Output Control Output disabled port mode Output enabled 16 bit Timer Counter 20 Count Clock Selection Overflow Flag Set Clear by reset and software TOD20 0 1 Timer output data is 1 Timer Output Data Timer output data is 0 TOD20 TOF20 CPT201 CPT200 TOC20 TCL201 TCL200 TOE20 TMC20 R W FF5BH 00H R W 6 5 4 3 2 1 7 0 Symbol Address Af...

Page 98: ...mer output set the output latch of PM51 and P51 to 0 PM5 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets PM5 to FFH Figure 6 3 Port Mode Register 5 Format 1 1 1 1 PM53 PM52 PM51 PM50 PM5 R W FF25H FFH R W 6 5 4 3 2 1 PM51 0 1 7 0 Input mode output buffer off Symbol Address After Reset P51 Pin Input Output Selection Output mode output buffer on ...

Page 99: ... to CPT201 and CPT200 flags capture edge becomes setting prohibited When the count value of 16 bit timer counter 20 TM20 coincides with the value set to CR20 counting of TM20 continues and an interrupt request signal INTTM2 is generated Table 6 2 shows interval time and Figure 6 5 shows timing of timer interrupt operation Caution Perform the following processing when rewriting CR20 during count op...

Page 100: ...19EJ3V0UM00 100 Figure 6 5 Timer Interrupt Operation Timing Count Clock TM20 Count Value CR20 INTTM2 TO20 TOF20 0000H 0001H N FFFFH 0000H 0001H N FFFFH N N N N N Interrupt Accepted Interrupt Accepted Overflow Flag Set t Remark N 0000H to FFFFH ...

Page 101: ...CL200 TOE20 TMC20 TO20 Output Enable Setting of Count Clock see Table 6 2 Inverse Enable of Timer Output Data Caution If both CPT201 flag and CPT200 flag are set to 0 the capture edge becomes operation prohibited When the count value of 16 bit timer counter 20 TM20 matches the value set in CR20 the output status of the TO2 P51 pin is inverted This enables timer output At that time TM20 count is co...

Page 102: ...ches and retains the count value of 16 bit timer counter 20 TCP20 fetches count value within 2 clocks and retains the count value until the next capture edge detection Table 6 3 and Figure 6 9 show the setting contents of capture edge and capture operation timing respectively Table 6 3 Setting Contents of Capture Edge CPT201 CPT200 Capture Edge Selection 0 0 Capture operation prohibited 0 1 CPT2 p...

Page 103: ...M20 to 0000H and starts freerunning Figure 6 10 shows the timing of 16 bit timer counter 20 readout Cautions 1 The count value after releasing stop becomes undefined because the count operation is executed during oscillation settling time 2 Though TM20 is a dedicated register of a 16 bit transfer instruction an 8 bit transfer instruction can be used When using the 8 bit transfer instruction execut...

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Page 105: ...me Resolution 1 fX 200 ns 2 8 fX 51 2 µs 1 fX 200 ns 2 5 fX 6 4 µs 2 13 fX 1 64 ms 2 5 fX 6 4 µs Remarks 1 fX System clock oscillation frequency 2 The parenthesized values apply to operation at fX 5 0 MHz 2 External event counter The number of pulses of an externally input signal can be measured 3 Square wave output A square wave of arbitrary frequency can be output Table 7 2 Square Wave Output Ra...

Page 106: ... Bit Timer Counter 00 TM00 2 Internal Bus TCE00 TCL001 TCL000 TOE00 8 Bit Timer Mode Control Register 1 F F P50 Output Latch PM50 Selector 1 8 bit compare register 00 CR00 This is an 8 bit register to compare the value set to CR00 with the 8 bit timer register 00 TM00 count value and if they match generates an interrupt request INTTM0 CR00 is set with an 8 bit memory manipulation instruction The 0...

Page 107: ...uction RESET input clears TMC00 to 00H Figure 7 2 8 Bit Timer Mode Control Register 00 Format TCE00 0 0 0 0 TCL001 TCL000 TOE00 TMC00 Symbol Address After Reset R W FF53H 00H R W 6 7 5 4 3 2 1 0 TCL001 0 0 1 1 8 Bit Timer Counter 00 Count Clock Selection TCL000 0 1 0 1 fX fX 25 Rising edge of TI0Note Falling edge of TI0Note TCE00 0 1 8 Bit Timer Counter 00 Operation Control Operation disabled TM00...

Page 108: ...or timer output set PM50 and the output latch of P50 to 0 PM5 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets PM5 to FFH Figure 7 3 Port Mode Register 5 Format PM50 0 1 1 1 1 1 PM53 PM52 PM51 PM50 PM5 7 6 5 4 R W R W 3 2 1 0 Input mode output buffer OFF Symbol Address FF25H FFH After Reset P50 Pin Input Output Mode Selection Output mode output buffer ON ...

Page 109: ...d Table 7 4 shows interval time and Figure 7 4 shows the timing of interval timer operation Cautions 1 Before rewriting CR00 stop the timer operation If CR00 is rewritten while the timer operation is enabled the coincidence interrupt request signal may be generated immediately 2 If setting the count clock in TMC00 and enabling the operation of TM00 are performed at the same time with an 8 bit memo...

Page 110: ...ure 7 4 Interval Timer Operation Timing Clear Clear Interrupt Accepted Interrupt Accepted Count Start Interval Time Interval Time Interval Time Count Clock TM00 Count Value CR00 TCE00 INTTM0 TO0 N 01 00 N 01 00 N 00 01 N N N N t Remark Interval time N 1 t where N 00H to FFH ...

Page 111: ...alue of TM00 coincides with the value set to CR00 the value of TM00 is cleared to 0 and TM00 continues counting At the same time an interrupt request signal INTTM0 is generated Figure 7 5 shows the timing of external event counter operation with rising edge specified Cautions 1 Before rewriting CR00 stop the timer operation If CR00 is rewritten while the timer operation is enabled the coincidence ...

Page 112: ...As soon as a match occurred the TM00 value will be cleared to 0 then resume to count generating an interrupt request signal INTTM0 Setting 0 to the bit 7 in TMC00 that is TCE00 makes the square wave output clear to 0 Table 7 5 lists square wave output range and Figure 7 6 shows timing of square wave output Cautions 1 Before rewriting CR00 stop the timer operation If CR00 is rewritten while the tim...

Page 113: ...00 113 Figure 7 6 Square Wave Output Timing Clear Clear Interrupt Accepted Interrupt Accepted Count Start Count Clock TM00 Count Value CR00 TCE00 INTTM0 TO0Note N 01 00 N 01 00 N 00 01 N N N N Note The initial value of TO0 at output enable TOE00 1 becomes low level ...

Page 114: ...counter 00 TM00 started asynchronously with the count pulse Figure 7 7 8 Bit Timer Counter 00 Start Timing Count Pulse TM00 Count Value Timer starts 00H 01H 02H 03H 04H 2 Setting of 8 bit compare register 8 bit compare register 00 CR00 can be set to 00H Therefore one pulse can be counted when an 8 bit timer event counter operates as an event counter Figure 7 8 External Event Counter Operation Timi...

Page 115: ... an inadvertent loop is detected a non maskable interrupt or the RESET signal can be generated Table 8 1 Inadvertent Loop Detection Time of Watchdog Timer Inadvertent Loop Detection Time At fX 5 0 MHz 2 11 1 fX 410 µs 2 13 1 fX 1 64 ms 2 15 1 fX 6 55 ms 2 17 1 fX 26 2 ms fX System clock oscillation frequency 2 Interval timer The interval timer generates an interrupt at a given interval set in adva...

Page 116: ...gister Timer clock select register 2 TCL2 Watchdog timer mode register WDTM Figure 8 1 Block Diagram of Watchdog Timer Internal Bus Internal Bus Prescaler Selector Control Circuit fX 26 fX 28 fX 210 3 7 Bit Counter Clear TMIF4 TMMK4 TCL22 TCL21 TCL20 Timer Clock Select Register 2 TCL2 Watchdog Timer Mode Register WDTM WDTM4 RUN WDTM3 INTWDT Maskable Interrupt Request RESET INTWDT Non Maskable Inte...

Page 117: ...ry manipulation instruction RESET input clears TCL2 to 00H Figure 8 2 Timer Clock Select Register 2 Format TCL22 0 0 1 1 0 0 0 0 0 TCL22 TCL21 TCL20 TCL2 R W R W 7 6 5 4 3 2 1 0 TCL21 0 1 0 1 fX 24 fX 26 fX 28 fX 210 312 5 kHz 78 1 kHz 19 5 kHz 4 88 kHz TCL20 0 0 0 0 Setting prohibited Symbol Address FF42H 00H After Reset Other than above Watchdog Timer Count Clock Selection 211 fX 213 fX 215 fX 2...

Page 118: ...dog timer mode 1 overflow and non maskable interrupt occur Watchdog timer mode 2 overflow occurs and reset operation started 0 0 Notes 1 Once RUN has been set to 1 it cannot be cleared to 0 by software Therefore when counting is started it cannot be stopped by any means other than RESET input 2 Once WDTM3 and WDTM4 have been set to 1 they cannot be cleared to 0 by software 3 The watchdog timer sta...

Page 119: ...etting RUN to 1 the watchdog timer can be cleared and start counting If RUN is not set to 1 and the inadvertent loop detection time is exceeded the system is reset or a non maskable interrupt is generated by the value of bit 3 WDTM3 of WDTM The watchdog timer continues operation in the HALT mode but stops in the STOP mode Therefore set RUN to 1 before entering the STOP mode to clear the watchdog t...

Page 120: ...MK4 is valid and a maskable interrupt INTWDT can be generated The priority of INTWDT is set as the highest of all the maskable interrupts The interval timer continues operation in the HALT mode but stops in the STOP mode Therefore set RUN to 1 before entering the STOP mode to clear the interval timer and then execute the STOP instruction Cautions 1 Once bit 4 WDTM4 of WDTM is set to 1 when the wat...

Page 121: ... for serial clock SCK0 and two for serial data SI0 SO0 The 3 wire serial I O mode supports simultaneous transmit and receive operation reducing data transfer processing time It is possible to switch the start bit of 8 bit data to be transmitted between the MSB and the LSB thus allowing connection to devices with either start bit The 3 wire serial I O mode is effective for connecting display contro...

Page 122: ...IO00 Direction Control Circuit Receive Shift Register RXS00 Receive Control Circuit Asynchronous Serial Interface Status Register 00 ASIS00 Direction Control Circuit Asynchronous Serial Interface Mode Register 00 ASIM00 Transmit Control Circuit SCK Output Control Circuit Baud Rate Generator Note Baud Rate Generator Control Register 00 BRGC00 Serial Operation Mode Register 00 CSIM00 Transmit Shift ...

Page 123: ...SIE00 TXE00 RXE00 f X ASCK SCK0 P20 1 2 1 2 CSIE00 RXE00 CSIE00 Internal Bus BRGC00 Write TXE00 CSCK00 RXE00 Transmit Clock Receive Clock Selector Clear Clear 3 Bit Counter Clear 3 Bit Counter Clear Stop Prescaler Baud Rate Generator Control Register 00 BRGC00 Selector Selector Start Bit Detection BRGC00 Write Figure 9 2 Block Diagram of Baud Rate Generator ...

Page 124: ...RXB00 This register is used to hold received data Each time one byte of data is received a new byte of data is transferred from receive shift register 00 RXS00 If the data length is specified as 7 bits receive data is transferred to bits 0 to 6 of RXB00 and the MSB of RXB00 always becomes 0 RXB00 can be read with an 8 bit memory manipulation instruction It cannot be written to RESET input makes RX...

Page 125: ...sing serial interface 00 in the 3 wire serial I O mode CSIM00 is set with a 1 bit or 8 bit memory manipulation instruction RESET input clears CSIM00 to 00H Figure 9 3 Serial Operation Mode Register 00 Format CSIE00 0 1 Operation Control in 3 Wire Serial I O Mode CSIE00 0 0 0 0 DIR00 CSCK00 0 CSIM00 Symbol Address After Reset R W FF72H 00H R W 7 6 5 4 3 2 1 0 Operation stop Operation enable DIR00 0...

Page 126: ...er Reset R W FF70H 00H R W 7 6 5 4 3 2 1 0 Transmit operation stop Transmit operation enable Receive operation stop Receive operation enable RXE00 0 1 0 1 0 0 0 1 0 1 1 1 No parity Always add 0 parity at transmission Parity check is not performed at reception No parity error is generated Odd parity Even parity Receive Operation Control PS001 Parity Bit Specification PS000 CL00 0 1 SL00 Character L...

Page 127: ...nternal clock SCK0 output 0 1 External clock SCK0 input 0 0 1 1 1 1Note 2 Note 2 0 1 0 1 LSB Internal clock SI0 Note 2 SO0 CMOS output SCK0 output Other than above Setting prohibited 3 Asynchronous serial interface mode ASIM00 CSIM00 TXE00 RXE00 CSIE00 DIR00 CSCK00 PM22 P22 PM21 P21 PM20 P20 Start Bit Shift Clock P22 SI0 RxD Pin Function P21 SO0 TxD Pin Function P20 SCK0 ASCK Pin Function 1 Extern...

Page 128: ... 5 4 3 2 1 0 Parity error not generated Parity error generated when the parity of transmit data does not coincide Flaming error not generated Flaming error generated when stop bit is not detected Note 1 Overrun error not generated Overrun error generatedNote 2 when the next receive operation is completed before the data is read from the receive buffer register FE00 0 1 0 1 Flaming Error Flag Overr...

Page 129: ...1 0 1 0 1 0 1 0 n 1 2 3 4 5 6 7 8 Setting prohibited Symbol Address After Reset 3 Bit Counter Source Clock Selection Input clock from external to ASCK pinNote Other than above Note Only used in UART mode Cautions 1 When writing to BRGC00 is performed during a communication operation the baud rate generator output is disrupted and communications cannot be performed normally Be sure not to write to ...

Page 130: ...k The baud rate generated from the system clock is found from the following expression Baud rate Hz fX System clock oscillation frequency n Value determined by values of TPS000 through TPS003 as shown in Figure 9 6 2 n 8 Table 9 3 Example of Relationship between System Clock and Baud Rate Error Baud Rate bps n BRGC00 Set Value fX 5 0 MHz fX 4 9152 MHz 1 200 8 70H 2 400 7 60H 4 800 6 50H 9 600 5 40...

Page 131: ...SCK pin The baud rate generated from the clock input from the ASCK pin is found from the following expression Baud rate Hz fASCK Frequency of clock input to the ASCK pin Table 9 4 Relationship between ASCK Pin Input Frequency and Baud Rate When BRGC00 is Set to 80H Baud Rate bps ASCK Pin Input Frequency kHz 75 1 2 150 2 4 300 4 8 600 9 6 1 200 19 2 2 400 38 4 4 800 76 8 9 600 153 6 19 200 307 2 31...

Page 132: ...CK P21 SO0 TxD and P22 SI0 RxD pins can be used as normal I O ports 1 Register setting Operation stop mode is set by serial operation mode register 00 CSIM00 and asynchronous serial interface mode register 00 ASIM00 a Serial operation mode register 00 CSIM00 CSIM00 is set with a 1 bit or 8 bit memory manipulation instruction RESET input clears CSIM00 to 00H CSIE00 0 1 Operation Control in 3 Wire S...

Page 133: ...ulation instruction RESET input clears ASIM00 to 00H TXE00 0 1 Transmit Operation Control TXE00 RXE00 PS001 PS000 CL00 SL00 0 0 ASIM00 Symbol Address After Reset R W FF70H 00H R W 7 6 5 4 3 2 1 0 Transmit operation stop Transmit operation enable Receive operation stop Receive operation enable RXE00 0 1 Receive Operation Control Caution Be sure to set bits 0 and 1 to 0 ...

Page 134: ...ode is set by serial operation mode register 00 CSIM00 asynchronous serial interface mode register 00 ASIM00 asynchronous serial interface status register 00 ASIS00 and baud rate generator control register 00 BRGC00 a Serial operation mode register 00 CSIM00 CSIM00 is set with a 1 bit or 8 bit memory manipulation instruction RESET input clears CSIM00 to 00H Set 00H to CSIM00 when UART mode is sele...

Page 135: ...ration stop Transmit operation enable Receive operation stop Receive operation enable RXE00 0 1 0 1 0 0 0 1 0 1 1 1 No parity Always add 0 parity at transmission Parity check is not performed at reception No parity error is generated Odd parity Even parity Receive Operation Control PS001 Parity Bit Specification PS000 CL00 0 1 SL00 Character Length Specification 7 bits 8 bits 1 bit 2 bits Transmit...

Page 136: ...rror not generated Framing error generated when stop bit is not detected Note 1 Overrun error not generated Overrun error generatedNote 2 when the next receive operation is completed before the data is read from the receive buffer register FE00 0 1 0 1 Flaming Error Flag Overrun Error Flag OVE00 Notes 1 Even when the stop bit length is set to 2 bits by setting bit 2 SL00 of asynchronous serial int...

Page 137: ...annot be performed normally Be sure not to write to BRGC00 during communication operation 2 Be sure not to select n 1 during an operation at fX 5 0 MHz because n 1 exceeds the baud rate limit 3 When selecting an input clock from an external source set port mode register 2 PM2 to the input mode Remarks 1 fX System clock oscillation frequency 2 n Value determined by setting TPS000 through TPS003 1 n...

Page 138: ...eneration of baud rate transmit receive clock by means of external clock from ASCK pin The transmit receive clock is generated by scaling the clock input from the ASCK pin The baud rate generated from the clock input from the ASCK pin is estimated by using the following expression Baud rate Hz fASCK Frequency of clock input to the ASCK pin Table 9 6 Relationship between ASCK Pin Input Frequency an...

Page 139: ...Format D0 D1 D2 D3 D4 D5 D6 D7 Parity Bit Stop Bit Start Bit One Data Frame Start bit 1 bit Character bits 7 bits 8 bits Parity bit Even parity odd parity 0 parity no parity Stop bit s 1 bit 2 bits When 7 bits are selected as the number of character bits only the low order 7 bits bits 0 to 6 are valid in transmission the most significant bit bit 7 is ignored and in reception the most significant b...

Page 140: ...it is counted and if the number is odd a parity error is generated ii Odd parity At transmission Conversely to the even parity the parity bit is determined so that the number of bits with a value of 1 in the transmit data including parity bit may be odd The parity bit value should be as follows The number of bits with a value of 1 is an odd number in transmit data 0 The number of bits with a value...

Page 141: ...rface Transmission Completion Interrupt Timing a Stop bit length 1 STOP Parity D7 D6 D2 D1 D0 START TxD Output INTST b Stop bit length 2 STOP Parity D7 D6 D2 D1 D0 START TxD Output INTST Caution Do not rewrite to asynchronous serial interface mode register 00 ASIM00 during a transmit operation If the ASIM00 register is rewritten to during transmission subsequent transmission may not be performed t...

Page 142: ...ected after the start bit reception of one frame of data ends When one frame of data has been received the receive data in the shift register is transferred to receive buffer register 00 RXB00 and a reception completion interrupt INTSR is generated If an error is generated the receive data in which the error was generated is still transferred to RXB00 and INTSR is generated If the RXE00 bit is res...

Page 143: ...ble 9 7 Receive Error Causes Receive Error Cause Parity error Transmission time parity specification and reception data parity do not match Framing error Stop bit not detected Overrun error Reception of next data is completed before data is read from receive buffer register Figure 9 10 Receive Error Timing a Parity error generated STOP Parity D7 D6 D2 D1 D0 START RxD Input INTSR b Framing error or...

Page 144: ...b When bit 6 RXE00 of asynchronous serial interface mode register 00 ASIM00 is cleared during reception receive buffer register 00 RXB00 and receive completion interrupt INTSR are as follows Parity RxD Pin RXB00 INTSR 3 1 2 When RXE00 is set to 0 at a time indicated by 1 RXB00 holds the previous data and INTSR is not generated When RXE00 is set to 0 at a time indicated by 2 RXB00 renews the data a...

Page 145: ...l operation mode register 00 CSIM00 asynchronous serial interface mode register 00 ASIM00 and baud rate generator control register 00 BRGC00 a Serial operation mode register 00 CSIM00 CSIM00 is set with a 1 bit or 8 bit memory manipulation instruction RESET input clears CSIM00 to 00H CSIE00 0 1 Operation Control in 3 Wire Serial I O Mode CSIE00 0 0 0 0 DIR00 CSCK00 0 CSIM00 Symbol Address After Re...

Page 146: ...00H R W 7 6 5 4 3 2 1 0 Transmit operation stop Transmit operation enable Receive operation stop Receive operation enable RXE00 0 1 0 1 0 0 0 1 0 1 1 1 No parity Always add 0 parity at transmission Parity check is not performed at reception No parity error is generated Odd parity Even parity Receive Operation Control PS001 Parity Bit Specification PS000 CL00 0 1 SL00 Character Length Specification...

Page 147: ...ted and communications cannot be performed normally Be sure not to write to BRGC00 during communication operation 2 Be sure not to select n 1 during an operation at fX 5 0 MHz because n 1 exceeds the baud rate limit 3 When selecting an input clock from an external source set port mode register 2 PM2 to the input mode Remarks 1 fX System clock oscillation frequency 2 n Value determined by setting T...

Page 148: ...ansfer the operations of TXS00 SIO00 and RXS00 stop automatically and the interrupt request signal INTCSI0 is generated Figure 9 11 3 Wire Serial I O Mode Timing 1 2 3 4 5 6 7 8 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 End of Transfer Transfer start at the falling edge of SCK0 SCK0 SI0 SO0 INTCSI0 3 Transfer start Serial transfer is started by setting transfer data to transm...

Page 149: ...generated The non maskable interrupt has one source of interrupt from the watchdog timer 2 Maskable interrupt These interrupts undergo mask control If two or more interrupts are simultaneously generated each interrupt has a predetermined priority priority as shown in Table 10 1 A standby release signal is generated The maskable interrupt has four sources of external interrupts and five sources of ...

Page 150: ...dge detection External 000AH C INTSR End of serial interface 00 UART reception 4 INTCSI0 End of serial interface 00 3 wire transfer 000CH 5 INTST End of serial interface 00 UART transmission 000EH 6 INTTM0 Generation of 8 bit timer event counter 00 match signal 0010H 7 INTTM2 Generation of 16 bit timer 20 match signal Internal 0014H B Maskable 8 INTKR Key return signal detection External 002AH C N...

Page 151: ...e Signal B Internal maskable interrupt MK IF IE Internal Bus Interrupt Request Vector Table Address Generator Standby Release Signal C External maskable interrupt MK IF IE Internal Bus INTM0 KRM00 Interrupt Request Edge Detector Vector Table Address Generator Standby Release Signal INTM0 External interrupt mode register 0 KRM00 Key return mode register 00 IF Interrupt request flag IE Interrupt ena...

Page 152: ...r 0 INTM0 Program status word PSW Key return mode register 00 KRM00 Table 10 2 gives a listing of interrupt request flag and interrupt mask flag names corresponding to interrupt requests Table 10 2 Flags Corresponding to Interrupt Request Signal Name Interrupt Request Signal Name Interrupt Request Flag Interrupt Mask Flag INTWDT INTP0 INTP1 INTP2 INTSR INTCSI0 INTST INTTM0 INTTM2 INTKR TMIF4 PIF0 ...

Page 153: ...IF0 and bits 1 to 6 of IF1 to 0 2 TMIF4 flag is R W enabled only when a watchdog timer is used as an interval timer If the watchdog timer mode 1 or 2 is used set TMIF4 flag to 0 3 Because port 3 has an alternate function as the external interrupt input when the output level is changed by specifying the output mode of the port function an interrupt request flag is set Therefore 1 should be set in t...

Page 154: ... Address After Reset Interrupt Servicing Control Interrupt servicing enabled Interrupt servicing disabled MK 6 5 4 3 2 1 7 0 TMMK20 1 1 1 1 1 1 KRMK00 MK1 FFE5H FFH R W 6 5 4 3 2 1 7 0 Cautions 1 Be sure to set bit 7 of MK0 and bits 1 to 6 of MK1 to 1 2 IF the TMMK4 flag is read when a watchdog timer is used in watchdog timer mode 1 or 2 its value becomes undefined 3 Because port 3 has an alternat...

Page 155: ...mbol Address After Reset INTP0 Valid Edge Selection Falling edge Rising edge Setting prohibited Both rising and falling edges INTP1 Valid Edge Selection Falling edge Rising edge Setting prohibited Both rising and falling edges INTP2 Valid Edge Selection Falling edge Rising edge Setting prohibited Both rising and falling edges ES00 ES01 ES11 ES10 ES20 ES21 Cautions 1 Be sure to set bits 0 and 1 to ...

Page 156: ...ster can carry out operations with a bit manipulation instruction and dedicated instructions EI and DI When a vectored interrupt request is acknowledged PSW is automatically saved into a stack and the IE flag is reset to 0 It is restored from the stack with the RETI and POP PSW instructions RESET input sets PSW to 02H Figure 10 5 Program Status Word Configuration IE Z 0 AC 0 0 1 CY PSW 7 6 5 4 3 2...

Page 157: ...M007 KRM006 KRM005 KRM004 0 0 0 KRM000 KRM00 Symbol Address After Reset R W FFF5H 00H R W 7 6 5 4 3 2 1 0 Cautions 1 Be sure to set bits 1 to 3 to 0 2 When KRM00 is set to 1 the corresponding pin is connected to a pull up resistor unless it is in output mode In output mode the pull up resistor is not connected 3 Before setting KRM00 set bit 0 of MK1 KRMK00 1 to disable interrupts To enable interru...

Page 158: ...d to the stack in that order the IE flag is reset to 0 the contents of the vector table are loaded to the PC and then program execution branches Figure 10 8 shows the flowchart from non maskable interrupt request generation to acceptance Figure 10 9 shows the timing of non maskable interrupt request acceptance Figure 10 10 shows the acceptance operation if multiple non maskable interrupts are gene...

Page 159: ... Timer No WDT overflows No Yes Reset Processing No Yes Yes Interrupt request is generated Interrupt processing is started WDTM3 0 non maskable interrupt is selected WDTM Watchdog timer mode register WDT Watchdog timer Figure 10 9 Non Maskable Interrupt Request Acceptance Timing Instruction Instruction Saving PSW and PC and jump to interrupt processing Interrupt Processing Program CPU Processing TM...

Page 160: ...INTERRUPT FUNCTIONS User s Manual U11919EJ3V0UM00 160 Figure 10 10 Accepting Non Maskable Interrupt Request Second Interrupt Processing First Interrupt Processing NMI Request second NMI Request first Main Routine ...

Page 161: ...est to Processing Minimum Time Maximum Time Note 9 clocks 19 clocks Note The wait time is maximum when an interrupt request is generated immediately before BT and BF instruction Remark 1 clock fCPU CPU clock When two or more maskable interrupt requests are generated at the same time they are accepted starting from the interrupt request assigned the highest priority A pended interrupt is accepted w...

Page 162: ...ptance Program Algorithm Start IF 1 MK 0 IE 1 Vectored Interrupt Processing Yes Interrupt request generated Yes Yes No No No Interrupt Request Pending Interrupt Request Pending IF Interrupt request flag MK Interrupt mask flag IE Flag to control maskable interrupt request acceptance 1 enable 0 disable ...

Page 163: ...ng Instruction Execution Saving PSW and PC jump to interrupt processing 8 Clocks Interrupt Processing Program Clock CPU Interrupt NOP MOV A r If an interrupt request flag IF is set at the last clock of the instruction the interrupt acceptance processing starts after the next instruction is executed Figure 10 13 shows an example of the interrupt acceptance timing for an interrupt request flag that ...

Page 164: ...terrupt request acceptance and the interrupt request acceptance enable state is set Example 2 A nesting is not generated because interrupts are not enabled INTyy EI Main Processing RETI INTyy Processing INTxx Processing IE 0 INTxx RETI INTyy is kept pending IE 0 Because interrupts are not enabled in interrupt INTxx servicing an EI instruction is not issued interrupt request INTyy is not accepted a...

Page 165: ...tion of the next instruction even if the interrupt request maskable interrupt non maskable interrupt and external interrupt is generated during the execution The following shows such instructions interrupt request reserve instruction Manipulation instruction for the interrupt request flag registers 0 and 1 IF0 and IF1 Manipulation instruction for the interrupt mask flag registers 0 and 1 MK0 and M...

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Page 167: ... and stops the entire system The current drain of the CPU can be substantially reduced in this mode Data memory can be retained at low voltages VDD 1 8 V min Therefore this mode is useful for retaining the contents of the data memory at an extremely low current The STOP mode can be released by an interrupt request so that this mode can be used for intermittent operation However some time is requir...

Page 168: ...lation Settling Time Select Register Format OSTS2 0 0 1 0 0 0 0 0 OSTS2 OSTS1 OSTS0 OSTS R W FFFAH 04H R W 7 6 5 4 3 2 1 0 OSTS1 0 1 0 212 fX 215 fX 217 fX 819 s µ 6 55 ms 26 2 ms OSTS0 0 0 0 Setting prohibited Symbol Address After Reset Oscillation Settling Time Selection Other than above Caution The wait time after the STOP mode is released does not include the time from STOP mode release to clo...

Page 169: ...Mode Operating Status Item HALT Mode Operating Status Clock generation circuit System clock oscillation enabled Clock supply to CPU stopped CPU Operation stopped Port Output latch Retains the status before setting the HALT mode 16 bit timer Operation enabled 8 bit timer event counter Operation enabled Watchdog timer Operation enabled Serial interface Operation enabled External interrupt Operation ...

Page 170: ...ess is executed Figure 11 2 Releasing HALT Mode by Interrupt HALT Instruction Standby Release Signal Wait Wait HALT Mode Operation Mode Operation Mode Clock Oscillation Remarks 1 The broken line indicates the case where the interrupt request that has released the standby mode is accepted 2 The wait time is as follows When vectored interrupt processing is performed 9 to 10 clocks When vectored inte...

Page 171: ...15 fX 6 55 ms Reset Period HALT Mode Operation Mode Oscillation Settling Wait Status Clock Operation Mode Oscillation Stop Oscillation Oscillation Remarks 1 fX System clock oscillation frequency 2 The parenthesized values apply to operation at fX 5 0 MHz Table 11 2 Operation after Release of HALT Mode Releasing Source MK IE Operation 0 0 Executes next address instruction 0 1 Executes interrupt pro...

Page 172: ...t time set by the oscillation settling time select register OSTS elapses and then operation mode is set The operation status in the STOP mode is shown in the following table Table 11 3 STOP Mode Operating Status Item STOP Mode Operation Status Clock generation circuit Stops system clock oscillation CPU Stops operation Port Output latch Retains the status before setting the STOP mode 16 bit timer S...

Page 173: ...ored interrupt processing is performed after the oscillation settling time has elapsed If the interrupt acceptance is disabled the instruction at the next address is executed Figure 11 4 Releasing STOP Mode by Interrupt STOP Instruction Standby Release Signal Wait Set Time by OSTS STOP Mode Operation Mode Oscillation Settling Wait Status Clock Operation Mode Oscillation Stop Oscillation Oscillatio...

Page 174: ...Wait 215 fX 6 55 ms STOP Mode Operation Mode Oscillation Settling Wait Status Clock Operation Mode Oscillation Stop Oscillation Oscillation Reset Period Remarks 1 fX System clock oscillation frequency 2 The parenthesized values apply to operation at fX 5 0 MHz Table 11 4 Operation after Release of STOP Mode Releasing Source MK IE Operation 0 0 Executes next address instruction 0 1 Executes interru...

Page 175: ...ut or during oscillation settling time just after reset clear When a high level is input to the RESET pin the reset is cleared and program execution is started after the oscillation settling time 215 fX has elapsed The reset applied by the watchdog timer overflow is automatically cleared after reset and program execution is started after the oscillation settling time 215 fX has elapsed see Figures...

Page 176: ...g by Overflow in Watchdog Timer X1 Internal Reset Signal Port Pin Overflow in Watchdog Timer Normal Operation Reset Period oscillation continues Oscillation Settling Time Wait Normal Operation reset processing Hi Z Figure 12 4 Reset Timing by RESET Input in STOP Mode X1 RESET Internal Reset Signal Port Pin Hi Z Delay Delay STOP Instruction Execution Normal Operation Stop Status oscillation stops R...

Page 177: ...CP20 Undefined Timer counter TM00 00H Compare register CR00 00H 8 bit timer event counter Mode control register TMC00 00H Timer clock select register TCL2 00H Watchdog timer Mode register WDTM 00H Mode register CSIM00 00H Asynchronous serial interface mode register ASIM00 00H Asynchronous serial interface status register ASIS00 00H Baud rate generator control register BRGC00 00H Transmit shift reg...

Page 178: ...User s Manual U11919EJ3V0UM00 178 MEMO ...

Page 179: ...25 µPD789026 ROM 16 Kbytes flash memory 4 Kbytes 8 Kbytes 12 Kbytes 16 Kbytes Internal memory Internal high speed RAM 512 bytes 256 bytes 512 bytes IC pin Not provided Provided VPP pin Provided Not provided Electric characteristics Refer to Data Sheet Caution The flash memory and masked ROM products have different noise immunity and noise radiation characteristics Do not use ES products for evalua...

Page 180: ...hose listed in Table 13 2 To select a communication mode the format shown in Figure 13 1 is used Each communication mode is selected depending on the number of VPP pulses shown in Table 13 2 Table 13 2 Communication Modes Communication Mode Pins Used Number of VPP Pulses 3 wire serial I O SCK0 ASCK P20 SO0 TxD P21 SI0 RxD P22 0 UART TxD SO0 P21 RxD SI0 P22 8 P00 Serial clock input P01 Serial data ...

Page 181: ...check Checks erased status of entire memory Data write Writes data to flash memory starting from write start address and based on number of data bytes to be written Batch verify Compares all contents of memory with input data 13 1 3 Connection Example of Flashpro III Connection with Flashpro III differs depending on the communication mode 3 wire serial I O UART or pseudo 3 wire mode Figures 13 2 t...

Page 182: ...o III PD78F9026A µ VPPnNote VDD RESET SO SI GND VPP VDD0 VDD1 RESET RxD TxD VSS0 VSS1 Note n 1 2 Figure 13 4 Connection Example of Flashpro III in Pseudo 3 Wire Mode When using P0 VPPnNote VDD RESET SCK SO SI GND VPP VDD0 VDD1 RESET P00 serial clock P02 serial input P01 serial output VSS0 VSS1 PD78F9026A µ Flashpro III Note n 1 2 ...

Page 183: ... O SIO CLK 1 0 MHz 0 COMM PORT UART ch0 CPU CLK On Target Board On Target Board 4 1943 MHz UART UART BPS 9 600 bps Note 2 8 COMM PORT Port A On Target Board CPU CLK In Flashpro On Target Board 4 1943 MHz SIO CLK 1 0 MHz In Flashpro 4 0 MHz SIO CLK 1 0 MHz 12 COMM PORT Port B On Target Board CPU CLK In Flashpro On Target Board 4 1943 MHz SIO CLK 1 kHz In Flashpro 4 0 MHz Pseudo 3 wire mode SIO CLK ...

Page 184: ...User s Manual U11919EJ3V0UM00 184 MEMO ...

Page 185: ... address specification Indirect address specification In the case of immediate data write an appropriate numeric value or a label When using a label be sure to write the and symbols For operand register identifiers r and rp either functional names X A C etc or absolute names names in parentheses in the table below R0 R1 R2 etc can be used Table 14 1 Operand Identifiers and Writing Methods Identifi...

Page 186: ... flag AC Auxiliary carry flag Z Zero flag IE Interrupt request enable flag NMIS Flag indicating non maskable interrupt servicing in progress Memory contents indicated by address or register contents in parentheses H L High order 8 bits and low order 8 bits of 16 bit register Logical product AND Logical sum OR Exclusive logical sum exclusive OR Inverted data addr16 16 bit immediate data or label jd...

Page 187: ...r sfr A 2 4 sfr A A addr16 3 8 A addr16 addr16 A 3 8 addr16 A PSW byte 3 6 PSW byte A PSW 2 4 A PSW PSW A 2 4 PSW A A DE 1 6 A DE DE A 1 6 DE A A HL 1 6 A HL HL A 1 6 HL A A HL byte 2 6 A HL byte MOV HL byte A 2 6 HL byte A A X 1 4 A X A r Note 2 2 6 A r A saddr 2 6 A saddr A sfr 2 6 A sfr A DE 1 8 A DE A HL 1 8 A HL XCH A HL byte 2 8 A HL byte Notes 1 Except r A 2 Except r A X Remark One instruct...

Page 188: ...dr16 A HL 1 6 A CY A HL ADD A HL byte 2 6 A CY A HL byte A byte 2 4 A CY A byte CY saddr byte 3 6 saddr CY saddr byte CY A r 2 4 A CY A r CY A saddr 2 4 A CY A saddr CY A addr16 3 8 A CY A addr16 CY A HL 1 6 A CY A HL CY ADDC A HL byte 2 6 A CY A HL byte CY A byte 2 4 A CY A byte saddr byte 3 6 saddr CY saddr byte A r 2 4 A CY A r A saddr 2 4 A CY A saddr A addr16 3 8 A CY A addr16 A HL 1 6 A CY A...

Page 189: ... saddr saddr byte A r 2 4 A A r A saddr 2 4 A A saddr A addr16 3 8 A A addr16 A HL 1 6 A A HL AND A HL byte 2 6 A A HL byte A byte 2 4 A A byte saddr byte 3 6 saddr saddr byte A r 2 4 A A r A saddr 2 4 A A saddr A addr16 3 8 A A addr16 A HL 1 6 A A HL OR A HL byte 2 6 A A HL byte A byte 2 4 A A byte saddr byte 3 6 saddr saddr byte A r 2 4 A A r A saddr 2 4 A A saddr A addr16 3 8 A A addr16 A HL 1 ...

Page 190: ...EC saddr 2 4 saddr saddr 1 INCW rp 1 4 rp rp 1 DECW rp 1 4 rp rp 1 ROR A 1 1 2 CY A7 A0 Am 1 Am 1 ROL A 1 1 2 CY A0 A7 Am 1 Am 1 RORC A 1 1 2 CY A0 A7 CY Am 1 Am 1 ROLC A 1 1 2 CY A7 A0 CY Am 1 Am 1 saddr bit 3 6 saddr bit 1 sfr bit 3 6 sfr bit 1 A bit 2 4 A bit 1 PSW bit 3 6 PSW bit 1 SET1 HL bit 2 10 HL bit 1 saddr bit 3 6 saddr bit 0 sfr bit 3 6 sfr bit 0 A bit 2 4 A bit 0 PSW bit 3 6 PSW bit 0...

Page 191: ...Z saddr16 2 6 PC PC 2 jdisp8 if Z 1 BNZ saddr16 2 6 PC PC 2 jdisp8 if Z 0 saddr bit addr16 4 10 PC PC 4 jdisp8 if saddr bit 1 sfr bit addr16 4 10 PC PC 4 jdisp8 if sfr bit 1 A bit addr16 3 8 PC PC 3 jdisp8 if A bit 1 BT PSW bit addr16 4 10 PC PC 4 jdisp8 if PSW bit 1 saddr bit addr16 4 10 PC PC 4 jdisp8 if saddr bit 0 sfr bit addr16 4 10 PC PC 4 jdisp8 if sfr bit 0 A bit addr16 3 8 PC PC 3 jdisp8 ...

Page 192: ...yte addr16 1 None A ADD ADDC SUB SUBC AND OR XOR CMP MOVNote XCH Note ADD ADDC SUB SUBC AND OR XOR CMP MOV XCH MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MOV ADD ADDC SUB SUBC AND OR XOR CMP MOV MOV XCH MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP ROR ROL RORC ROLC r MOV MOV INC DEC B C DBNZ sfr MOV MOV saddr MOV ADD ADDC SUB SUBC AND OR XOR CMP MOV DBNZ INC DEC ...

Page 193: ...Note saddrp SP None AX ADDW SUBW CMPW MOVW XCHW MOVW MOVW rp MOVW MOVW Note INCW DECW PUSH POP saddrp MOVW SP MOVW Note Only when rp BC DE or HL 3 Bit manipulation instructions SET1 CLR1 NOT1 BT BF 2nd Operand 1st Operand addr16 None A bit BT BF SET1 CLR1 sfr bit BT BF SET1 CLR1 saddr bit BT BF SET1 CLR1 PSW bit BT BF SET1 CLR1 HL bit SET1 CLR1 CY SET1 CLR1 NOT1 ...

Page 194: ...00 194 4 Call instructions branch instructions CALL CALLT BR BC BNC BZ BNZ DBNZ 2nd Operand 1st Operand AX addr16 addr5 addr16 Basic instructions BR CALL BR CALLT BR BC BNC BZ BNZ Compound instructions DBNZ 5 Other instructions RET RETI NOP EI DI HALT STOP ...

Page 195: ...ment tools Compatibility with PC98 NX series Unless stated otherwise products which are supported for the IBM PC ATTM compatibles can also be used with the PC98 NX series When using the PC98 NX series therefore refer to the explanations for the IBM PC AT compatibles Windows Unless stated otherwise Windows refers to the following operating systems Windows 3 1 Windows 95 Windows NTTM Ver 4 0 ...

Page 196: ...e Assembler package C compiler package System simulator Device file C compiler source file Integrated debugger Flash Memory Writing Environment In Circuit Emulator Emulation Probe Emulation board Flash writer Flash memory writing adapter Flash memory Target System Interface adapter Host Machine PC or EWS Conversion socket Power Supply Unit ...

Page 197: ...he assembler package CC78K0S C compiler package Part number µS CC78K0S File containing the information inherent to the device Used in combination with other optional tools RA78K0S CC78K0S SM78K0S DF789026 Note Device file Part number µS DF789026 Source file of functions constituting object library included in C compiler package Necessary for changing object library included in C compiler package a...

Page 198: ...44GB FA 44GB 8ES Flash memory writing adapter Flash memory writing adapter Used in connection with Flashpro III FA 42CU For 42 pin plastic shrink DIP CU type FA 44GB For 44 pin plastic QFP GB 3BS type FA 44GB 8ES For 44 pin plastic LQFP GB 8ES type Remark FL PR3 FA 42CU FA 44GB and FA 44GB 8ES are products of Naito Densei Machida Mfg Co Ltd For further information contact Naito Densei Machida Mfg ...

Page 199: ...K0S NS IE 789026 NS EM1 Emulation board Emulation board for emulating the peripheral hardware inherent to the device Used in combination with in circuit emulator NP 44GB Note Emulation probe Emulation probe for connecting the in circuit emulator and target system This is for the 44 pin plastic QFP GB 3BS type and the 44 pin plastic LQFP GB 8ES type EV 9200G 44 Conversion adapter This conversion ad...

Page 200: ...rating system to be used µS ID78K0S NS Host Machine OS Supply Media AA13 PC 9800 series Japanese Windows Note 3 5 2HD FD AB13 IBM PC AT compatibles Japanese Windows Note 3 5 2HC FD Note Also operates under the DOS environment Debugs program at C source level or assembler level while simulating operation of target system on host machine SM78K0S runs on Windows By using SM78K0S the logic and perform...

Page 201: ...EV 9200G 44 B C M N O L K R Q I H P J G EV 9200G 44 G0 ITEM MILLIMETERS INCHES A B C D E F G H I J K L M O N P Q R 15 0 10 3 10 3 15 0 4 C 3 0 0 8 5 0 12 0 14 7 5 0 12 0 14 7 8 0 7 8 2 0 1 35 0 35 0 1 1 5 0 591 0 406 0 406 0 591 4 C 0 118 0 031 0 197 0 472 0 579 0 197 0 472 0 579 0 315 0 307 0 079 0 053 0 014 0 059 0 004 0 005 φ φ No 1 pin index Based on EV 9200G 44 1 Package drawing in mm ...

Page 202: ...0 1 1 57 0 03 0 618 0 433 0 433 0 618 0 197 0 197 0 02 0 062 0 087 0 062 0 8 0 02 10 8 0 0 05 0 8 0 02 10 8 0 0 05 φ φ φ 0 002 0 001 0 002 0 002 0 002 0 001 0 002 0 002 0 003 0 004 0 003 0 004 0 001 0 002 φ φ φ 0 001 0 002 0 004 0 005 0 001 0 002 Dimensions of mount pad for EV 9200 and that for target device QFP may be different in some parts For the recommended mount pad dimensions for QFP refer ...

Page 203: ...0 398 D H C 2 0 C 0 079 I 9 35 0 368 J 1 325 0 052 E 8 4 0 331 F 10 8 0 425 K 1 325 0 052 L 12 0 0 472 M Q 1 8 0 071 R S N 8 5 0 335 O 13 15 P 5 0 0 197 0 518 W X 6 0 0 236 Y T U 16 95 V 7 35 0 289 0 667 Z 3 5 0 138 16 65 16 65 0 656 0 656 G 13 2 0 520 Reference diagram TGB 044SAP TQPACK044SA TQSOCKET044SAP Package dimension unit mm S C H a f g T note Product by TOKYO ELETECH CORPORATION TGB 044SA...

Page 204: ...User s Manual U11919EJ3V0UM00 204 MEMO ...

Page 205: ...the MX78K0S OS controls task execution order and performs the switching process to a task to be executed Caution when used under the PC environment The MX78K0S is a DOS based application Use this software in the DOS pane when running it on Windows Remark in the part number differs depending on the host machines and operating system to be used µS MX78K0S Host Machine OS Supply Media AA13 PC 9800 se...

Page 206: ...User s Manual U11919EJ3V0UM00 206 MEMO ...

Page 207: ...26 133 135 146 Asynchronous serial interface status register 00 ASIS00 128 136 B Baud rate generator control register 00 BRGC00 129 137 147 E External interrupt mode register 0 INTM0 155 I Interrupt mask flag register 0 MK0 154 Interrupt mask flag register 1 MK1 154 Interrupt request flag register 0 IF0 153 Interrupt request flag register 1 IF1 153 K Key return mode register 00 KRM00 157 O Oscilla...

Page 208: ... 81 98 108 Processor clock control register PCC 86 Pull up resistor option register PUO 82 R Receive buffer register 00 RXB00 124 Receive shift register 00 RXS00 124 S Serial operation mode register 00 CSIM00 125 132 134 145 T Timer clock select register 2 TCL2 117 Transmit shift register 00 TXS00 124 W Watchdog timer mode register WDTM 118 ...

Page 209: ...terrupt request flag register 1 153 INTM0 External interrupt mode register 0 155 K KRM00 Key return mode register 00 157 M MK0 Interrupt mask flag register 0 154 MK1 Interrupt mask flag register 1 154 O OSTS Oscillation settling time select register 168 P P0 Port 0 71 P1 Port 1 72 P2 Port 2 73 P3 Port 3 76 P4 Port 4 77 P5 Port 5 78 PCC Processor clock control register 86 PM0 Port mode register 0 8...

Page 210: ... register 2 117 TCP20 16 bit capture register 20 95 TM00 8 bit timer counter 00 106 TM20 16 bit timer counter 20 95 TMC00 8 bit timer mode control register 00 107 TMC20 16 bit timer mode control register 20 96 TXS00 Transmit shift register 00 124 W WDTM Watchdog timer mode register 118 ...

Page 211: ...ister 00 Chapter 9 Serial Interface 00 Change of flag names of interrupt request flag register Change of flag names of interrupt mask flag register Change of symbols and flag names of key return mode register 00 Addition of description on timing of maskable interrupt request acceptance Chapter 10 Interrupt Functions Second edition Addition of setting with Flashpro II Chapter 13 µPD78F9026 Completi...

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Page 213: ... 02 2719 5951 Address North America NEC Electronics Inc Corporate Communications Dept Fax 1 800 729 9288 1 408 588 6130 Europe NEC Electronics Europe GmbH Technical Documentation Dept Fax 49 211 6503 274 South America NEC do Brasil S A Fax 55 11 6462 6829 Asian Nations except Philippines NEC Electronics Singapore Pte Ltd Fax 65 250 3583 Japan NEC Semiconductor Technical Hotline Fax 044 435 9608 I ...

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