7-7
7.8 List of CPU Pin Assignments
Port
Pin No.
Signal Name
Initial Setting
Function
Remark
~ 1
NC
~
~
P1.0
2
HDATA0
~
gm5020 4bit interface data
P1.1
3
HDATA1
~
gm5020 4bit interface data
P1.2
4
HDATA2
~
gm5020 4bit interface data
P1.3
5
HDATA3
~
gm5020 4bit interface data
P1.4
6
HCLK
~
gm5020 4bit interface clock
P1.5 7
HFS
~ gm5020
data
enable
P1.6 8
Bank
~
~
P1.9
9
PWM
~
Pulse width modulation
~
10
RST
L
Reset CPU
Active H
P3.0 11
RXD
H
Receive
data
~ 12
NC
~
~
P3.1 13
TXD
H
Transmit
data
P3.2
14
IRQ
~
gm5020 interrupt signal
P3.3
15
PWR_SW
~
ON/OFF monitor power
P3.4
16
SDA
H
IIC Bus data
P3.5
17
SCL
~
IIC Bus data
Active L
P3.6
18
P3.6
H
External Memrv Write Enable
P3.7
19
DDC_GND
L
Detect Dsub cable plug-in
~
20
XTAL2
~
Crystal signal out
~
21
XTAL
~
Crystal signal in
~ 22
GND
~
~
~ 23
NC
~
~
P2.0
24
A8
~
High-order address byte
P2.1
25
A9
~
High-order address byte
P2.2
26
A10
~
High-order address byte
P2.3
27
A11
~
High-order address byte
P2.4
28
A12
~
High-order address byte
P2.5
29
A13
~
High-order address byte
P2.6
30
A14
~
High-order address byte
P2.7
31
A15
~
High-order address byte
~
32
PSEN#
H
Program store enable
~
33
ALE
~
Address latch enable
~ 34
NC
~
~
~
35
EA#
H
External Access Enable
P0.7
36
D7(USB_ON)
H
USB HUB power Enable(option)
P0.6
37
D6(MUTE)
H
Audio MUTE Enable
P0.5
38
D5(LVCC)
L
Audio suspend Enable
P0.4
39
D4(LEDGRN)
H
LED Green ON
P0.3
40
D3(LEDANBER) L LED
AMBER
ON
P0.2
41
D2(BKLT_EN)
~
Inverter back light Enable
P0.1
42
D1(LVDS ON)
H
LVDS IC Enable
P0.0
43
D0(PANEL EN)
H
Panel power Enable
~ 44
VCC
~ VCC