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CHAPTER 4 DIFFERENCES BETWEEN TARGET DEVICES AND TARGET INTERFACE CIRCUITS
User’s Manual U14013EJ2V0UM00
37
(2) Signals input from the target system via a gate
Since the following signals are input via a gate, their timing shows a delay compared to that of the
µ
PD178078,
178098 Subseries, and
µ
PD178F098. Their AC characteristics and DC characteristics are therefore different
from the
µ
PD178078, 178098 Subseries, and
µ
PD178F098, making it necessary to observe a stricter timing
design than in the case of the the
µ
PD178078, 178098 Subseries, and
µ
PD178F098.
•
RESET signal
•
Signals related to clock input
In all the signals input from the target system, the RESET signal, and signals related to clock input are input to
the evaluation chip via a logic IC. The DC characteristics are therefore different from the
µ
PD178078, 178098
Subseries, and
µ
PD178F098. The AC characteristics are also different because of the delayed signal timing
caused by the gate.
Figure 4-2. Equivalent Circuit 2 of Emulator
Probe side
IE-178098-NS-EM1 side
(3) Signals related to PLL
•
AMIFC
•
FMIFC
•
VCOH
•
VCOL
•
REGOSC
•
REGCPU
•
V
DD
PLL
•
GNDPLL
LV
CC
LV
CC
1 M
Ω
4.7 k
Ω
HSK120
HD151015
X1
X1
HD151015
HC4066
RESET
RESET
Summary of Contents for IE-178098-NS-EM1
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