NBS Technologies NBS5500, User Manual

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NBS Payment Solutions 19/60 User Manual
1.8 DETAILED HARDWARE CHARACTERISTICS
1.8.1 Processors - the power of Telium
®
technology
"A CIRCUIT BOARD BUILT INTO A CHIP".
Main characteristics
Main CPU ARM 32-bit RISC processor
Clock frequency 180 MHz
Capacity 200 MIPS
CRYPTO CPU ARM 32-bit RISC processor
Clock frequency 60 MHz
Capacity 50 MIPS
Calendar Leap-year management
Time and date stamping Without seasonal hour changes
The power of the NBS5XXX's processors gives the following performance:
Algorithm
Algorithm Keys
RSA
SDA DDA
1024 exp 3 2.5 ms 5.1 ms 7.7 ms
1024 exp 2
16
+ 1 22 ms 44.1 ms 66.2 ms
2048 exp 3 8 ms 16.1 ms 24.2 ms
2048 exp 2
16
+ 1
72 ms 144 ms 218 ms
1.8.2 Data security
1.8.2.1 Equipment design
The terminal was designed with the goal of resisting tampering, in order to keep the confidential character of
sensitive data (keys or confidential code), and to delete this data as soon as a tamper attempt is detected.
Tamper resistance
•
All the data are inside the crypto processor and are thus physically protected by the chip. This prevents
the reading of secret bank keys and confidential codes.
•
The display, keypad and smart card readers are controlled by the crypto processor.
1.8.2.2 Tamper detection
Protection against tampering
•
By micro switches
•
By temperature surveillance
•
By voltage surveillance