National Semiconductor SERDES05-40USB, User Manual

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SERDES Evaluation Kit DS99R105/106 USB Version 0.1 Users Manual

National Semiconductor Corporation

Date: 5/14/2008
Page 32 of 37

SECONDARY COMP SIDE – SOLDER PASTE (LAYER 4)

PRIMARY COMP SIDE – SOLDER PASTE (LAYER 1)

PRIMARY COMP SIDE – SILKSCREEN (LAYER 1)

SILKSCREEN COMP SIDE – SILKSCREEN (LAYER 4)

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Summary of Contents for SERDES05-40USB

Page 1: ...RDES Evaluation Kit DS99R105 106 USB Version 0 1 Users Manual National Semiconductor Corporation Date 5 14 2008 Page 1 of 37 SERDES Demonstration Kit User Manual NSID SERDES05 40USB DS99R105 106 Rev 0...

Page 2: ...SETTINGS FOR THE TX BOARD 8 TX LVCMOS AND FPD LINKII PINOUT BY IDC CONNECTOR 11 BOM BILL OF MATERIALS SERIALIZER PCB 12 RX SERDES DE SERIALIZER BOARD 13 CONFIGURATION SETTINGS FOR THE RX BOARD 14 RX...

Page 3: ...FPD LinkII Serializer converts the LVCMOS parallel lines into a single serialized FPD LINKII data pair with an embedded FPD LINKII clock The serial data stream toggles at 28 times the base clock rate...

Page 4: ...ion Kit 1 One Serializer board with the DS99R105 2 One De serializer board with the DS99R106 3 One 2 meter high speed USB 2 0 cable 4 pin USB A to 5 pin mini USB 4 Evaluation Kit Documentation this ma...

Page 5: ...on Date 5 14 2008 Page 5 of 37 Figures 1a and 1b illustrate the use of the Chipset Tx Rx in a Host to Flat Panel Interface The chipsets support up to 18 bit color depth TFT LCD Panels Refer to the pro...

Page 6: ...a USB device be plugged into the demo boards 2 Jumpers and switches have been configured at the factory they should not require any changes for immediate operation of the chipset See text on Configur...

Page 7: ...I outputs in AC coupled mode S1 RESVRDA RESVRDB and VODSEL must be set LOW Rising or falling edge reference clock is also selected on S1 TRFB HIGH rising or LOW falling The USB connector P2 USB A side...

Page 8: ...AOFF MUST be tied low for normal operation Default RESVRDB DCBOFF MUST be tied low for normal operation Default TPWDNB PoWerDowN Bar Powers Down Operational Default TRFB Latch input data on Rising or...

Page 9: ...JP1 JP2 USB Red and Black wire Reference Description VDD VSS OPEN JP1 Power wire in USB cable thru P2 and P1 not mounted connector Jumper RED to VSS recommended Note Normally VDD in USB application R...

Page 10: ...D Link II serial stream This snapshot was taken with a differential probe across the 100 ohm termination resistor R1 on the DS99R106 Rx evaluation board R1 is the termination resistor to the RxIN Note...

Page 11: ...the lvcmos input and FPD LINKII outputs J1 P2 P1 LVCMOS INPUT bottom side topside pin no name name pin no FPD LINKII OUTPUT not mounted 1 GND DIN0 2 pin no name FPD LINKII OUTPUT 3 GND DIN1 4 1 JP1 p...

Page 12: ...11 C15 C16 C19 0 01uF CAP HDC 0603 7 5 C8 C12 C14 C17 C18 0 1uF CAP HDC 0603 8 2 JP2 JP1 3 Pin Header Header 3P 9 1 JP3 2 Pin Header Header 2P 10 1 J1 IDC2X25_Unshrouded IDC 50 11 2 J5 J4 BANANA CON B...

Page 13: ...erializer board is powered externally from the J4 VDD and J5 VSS connectors shown below For the De serializer to be operational the Power Down RPWDNB and Receiver Enable REN switches on S1 must be set...

Page 14: ...e Description Input L Input H S1 RFB Latch output data on Rising or Falling Data Strobe of RCLK Falling Default Rising REN Receiver Output ENabled Disabled Enabled Default RPWDNB PoWerDowN Bar Power D...

Page 15: ...SS recommended Note Normally VDD in USB application Red wire tied to VDD Red wire tied to VSS Default Red wire floating not recommended JP2 Power wire in USB cable thru J2 and J1 not mounted connector...

Page 16: ...INKII inputs and LVCMOS outputs J3 J2 J1 LVCMOS INPUT topside bottom side pin no name name pin no FPD LINKII OUTPUT not mounted 1 ROUT0 GND 2 pin no name FPD LINKII OUTPUT 3 ROUT1 GND 4 1 JP1 pin no n...

Page 17: ...CAP HDC 0402 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C39 6 8 C31 C32 C33 C38 C43 C49 22uF CAP EIA B 3528 21 C54 C55 7 8 C34 C37 C40 C44 C45 C48 0 1uF CAP HDC 0603 C52...

Page 18: ...ces for 6 bit Digital LVCMOS RGB 3 Any other signal video generator that generates the correct input levels as specified in the datasheet 4 Optional Logic Analyzer or Oscilloscope The following is a l...

Page 19: ...n Date 5 14 2008 Page 19 of 37 The picture below shows a typical test set up using a Graphics Controller and LCD Panel Figure 2 Typical SERDES Setup of LCD Panel Application The picture below shows a...

Page 20: ...rify that data is strobed on the selected rising falling RFB pin edge of the clock 4 Check that the Jumpers and Switches are set correctly 5 Check that the cable is properly connected TROUBLESHOOTING...

Page 21: ...437 9585 Fax 408 437 9591 www component tdk com Optional EMI Filters TDK Chip Beads or equivalent Cable References The FPD LINKII interface cable included in the kit is a standard off the shelf high...

Page 22: ...SERDES Evaluation Kit DS99R105 106 USB Version 0 1 Users Manual National Semiconductor Corporation Date 5 14 2008 Page 22 of 37 Appendix Serializer Tx PCB Schematic...

Page 23: ...SERDES Evaluation Kit DS99R105 106 USB Version 0 1 Users Manual National Semiconductor Corporation Date 5 14 2008 Page 23 of 37 DS99R105...

Page 24: ...SERDES Evaluation Kit DS99R105 106 USB Version 0 1 Users Manual National Semiconductor Corporation Date 5 14 2008 Page 24 of 37...

Page 25: ...SERDES Evaluation Kit DS99R105 106 USB Version 0 1 Users Manual National Semiconductor Corporation Date 5 14 2008 Page 25 of 37...

Page 26: ...SERDES Evaluation Kit DS99R105 106 USB Version 0 1 Users Manual National Semiconductor Corporation Date 5 14 2008 Page 26 of 37 De serializer Rx PCB Schematic...

Page 27: ...SERDES Evaluation Kit DS99R105 106 USB Version 0 1 Users Manual National Semiconductor Corporation Date 5 14 2008 Page 27 of 37 DS99R106...

Page 28: ...SERDES Evaluation Kit DS99R105 106 USB Version 0 1 Users Manual National Semiconductor Corporation Date 5 14 2008 Page 28 of 37...

Page 29: ...SERDES Evaluation Kit DS99R105 106 USB Version 0 1 Users Manual National Semiconductor Corporation Date 5 14 2008 Page 29 of 37...

Page 30: ...SERDES Evaluation Kit DS99R105 106 USB Version 0 1 Users Manual National Semiconductor Corporation Date 5 14 2008 Page 30 of 37 Serializer Tx PCB Layout TOP VIEW BOTTOMSIDE VIEW...

Page 31: ...Manual National Semiconductor Corporation Date 5 14 2008 Page 31 of 37 PRIMARY COMPONENT SIDE LAYER 1 GROUND PLANE VSS LAYER 2 POWER PLANE VDD LAYER 3 SECONDARY COMP SIDE LAYER 4 PRIMARY COMP SIDE SOL...

Page 32: ...sion 0 1 Users Manual National Semiconductor Corporation Date 5 14 2008 Page 32 of 37 SECONDARY COMP SIDE SOLDER PASTE LAYER 4 PRIMARY COMP SIDE SOLDER PASTE LAYER 1 PRIMARY COMP SIDE SILKSCREEN LAYER...

Page 33: ...SERDES Evaluation Kit DS99R105 106 USB Version 0 1 Users Manual National Semiconductor Corporation Date 5 14 2008 Page 33 of 37 Serializer Tx PCB Stackup...

Page 34: ...SERDES Evaluation Kit DS99R105 106 USB Version 0 1 Users Manual National Semiconductor Corporation Date 5 14 2008 Page 34 of 37 Deserializer Rx PCB Layout TOP VIEW BOTTOMSIDE VIEW...

Page 35: ...Manual National Semiconductor Corporation Date 5 14 2008 Page 35 of 37 PRIMARY COMPONENT SIDE LAYER 1 GROUND PLANE VSS LAYER 2 POWER PLANE VDD LAYER 3 SECONDARY COMP SIDE LAYER 4 PRIMARY COMP SIDE SOL...

Page 36: ...sion 0 1 Users Manual National Semiconductor Corporation Date 5 14 2008 Page 36 of 37 SECONDARY COMP SIDE SOLDER PASTE LAYER 4 PRIMARY COMP SIDE SOLDER PASTE LAYER 1 PRIMARY COMP SIDE SILKSCREEN LAYER...

Page 37: ...SERDES Evaluation Kit DS99R105 106 USB Version 0 1 Users Manual National Semiconductor Corporation Date 5 14 2008 Page 37 of 37 Deserializer Rx PCB Stackup...

Page 38: ...or use in safety critical applications such as life support where a failure of the TI product would reasonably be expected to cause severe personal injury or death unless officers of the parties have...

Page 39: ...Mouser Electronics Authorized Distributor Click to View Pricing Inventory Delivery Lifecycle Information Texas Instruments SERDES05 40USB NOPB...

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