SERDES Evaluation Kit DS99R105/106 USB Version 0.1 Users Manual
National Semiconductor Corporation
Date: 5/14/2008
Page 16 of 37
Rx FPD-LINK
II
Pinout and LVCMOS by IDC Connector
The following three tables illustrate how the Rx outputs are mapped to the IDC
connector J3, the mini USB FPD-LINKII connector J2, and the mini USB FPD-LINKII
connector J1 (not installed) pinouts. Note
–
labels are also printed on the demo boards
for both the FPD-LINKII inputs and LVCMOS outputs.
J3
J2
J1
LVCMOS INPUT
(topside)
(bottom side)
pin no.
name
name
pin no.
FPD-LINK
II
OUTPUT
(not mounted)
1
ROUT0
GND
2
pin no.
name
FPD-LINK
II
OUTPUT
3
ROUT1
GND
4
1
JP1
pin no.
name
5
ROUT2
GND
6
2
DOUT+
5 JP2
7
ROUT3
GND
8
3
DOUT-
4 NC
9
ROUT4
GND
10
4
NC
3
DOUT-
11
ROUT5
GND
12
5
JP2
2
DOUT+
13
ROUT6
GND
14
1
JP1
15
ROUT7
GND
16
17
ROUT8
GND
18
19
ROUT9
GND
20
21
ROUT10
GND
22
23
ROUT11
GND
24
25
RCLK
GND
26
27
ROUT12
GND
28
29
ROUT13
GND
30
31
ROUT14
GND
32
33
ROUT15
GND
34
35
ROUT16
GND
36
37
ROUT17
GND
38
39
ROUT18
GND
40
41
ROUT19
GND
42
43
ROUT20
GND
44
45
ROUT21
GND
46
47
ROUT22
GND
48
49
ROUT23
GND
50