National Semiconductor NS32081-10, Manual, Page: 9 / 18

2.0 Architectural Description
(Continued)
2.2.3 Floating-Point Instruction Set
The NS32081 FPU instructions occupy formats 9 and 11 of
the Series 32000 Family instruction set (
Figure 2-6 ). A list
of all Series 32000 family instruction formats is found in the
applicable CPU data sheet.
Certain notations in the following instruction description ta-
bles serve to relate the assembly language form of each
instruction to its binary format in
Figure 2-6 .
Format 9
TL/EE/5234 – 11
Format 11
TL/EE/5234 – 12
FIGURE 2-6. Floating-Point Instruction Formats
The Format column indicates which of the two formats in
Figure 2-6 represents each instruction.
The Op column indicates the binary pattern for the field
called ‘‘op’’ in the applicable format.
The Instruction column gives the form of each instruction as
it appears in assembly language. The form consists of an
instruction mnemonic in upper case, with one or more suffix-
es (i or f) indicating data types, followed by a list of oper-
ands (gen1, gen2).
An i suffix on an instruction mnemonic indicates a choice of
integer data types. This choice affects the binary pattern in
the i field of the corresponding instruction format (
Figure 2-6 )
as follows:
Suffix i Data Type i Field
B Byte 00
W Word 01
D Double Word 11
An f suffix on an instruction mnemonic indicates a choice of
floating-point data types. This choice affects the setting of
the f bit of the corresponding instruction format (
Figure 2-6 )
as follows:
Suffix f Data Type f Bit
F Single Precision 1
L Double Precision (Long) 0
An operand designation (gen1, gen2) indicates a choice of
addressing mode expressions. This choice affects the bina-
ry pattern in the corresponding gen1 or gen2 field of the
instruction format (
Figure 2-6 ). Refer to Table 2-1 for the
options available and their patterns.
Further details of the exact operations performed by each
instruction are found in the Series 32000 Instruction Set
Reference Manual.
Movement and Conversion
The following instructions move the gen1 operand to the
gen2 operand, leaving the gen1 operand intact.
Format Op Instruction Description
11 0001 MOVf gen1, gen2 Move without
conversion
9 010 MOVLF gen1, gen2 Move, converting
from double
precision to
single precision.
9 011 MOVFL gen1, gen2 Move, converting
from single
precision to
double
precision.
9 000 MOVif gen1, gen2 Move, converting
from any integer
type to any
floating-point
type.
9 100 ROUNDfi gen1, gen2 Move, converting
from floating-
point to the
nearest integer.
9 101 TRUNCfi gen1, gen2 Move, converting
from floating-
point to the
nearest integer
closer to zero.
9 111 FLOORfi gen1, gen2 Move, converting
from floating-
point to the
largest integer
less than or
equal to its
value.
Note: The MOVLF instruction f bit must be 1 and the i field must be 10.
The MOVFL instruction f bit must be 0 and the i field must be 11.
Arithmetic Operations
The following instructions perform floating-point arithmetic
operations on the gen1 and gen2 operands, leaving the re-
sult in the gen2 operand.
Format Op Instruction Description
11 0000 ADDf gen1, gen2 Add gen1 to gen2.
11 0100 SUBf gen1, gen2 Subtract gen1
from gen2.
11 1100 MULf gen1, gen2 Multiply gen2 by
gen1.
11 1000 DIVf gen1, gen2 Divide gen2 by
gen1.
11 0101 NEGf gen1, gen2 Move negative of
gen1 to gen2.
11 1101 ABSf gen1, gen2 Move absolute
value of gen1 to
gen2.
9