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3.0 Functional Description

(Continued)

Using the Addressing Mode fields within the Operation
Word, the CPU starts fetching operands and issuing them to
the FPU. To do so, it references any Addressing Mode ex-
tensions appended to the FPU instruction. Since the CPU is
solely responsible for memory accesses, these extensions
are not sent to the Slave Processor. The Status Code ap-
plied is 01 (Transfer Slave Processor Operand, Table 3-1).

After the CPU has issued the last operand, the FPU starts
the actual execution of the instruction. Upon completion, it
will signal the CPU by pulsing SPC low. To allow for this, the
CPU releases the SPC signal, causing it to float. SPC must
be held high by an external pull-up resistor.

Upon receiving the pulse on SPC, the CPU uses SPC to
read a Status Word from the FPU, applying Status Code 10.
This word has the format shown in

Figure 3-7 . If the Q bit

(‘‘Quit’’, Bit 0) is set, this indicates that an error has been
detected by the FPU. The CPU will not continue the proto-
col, but will immediately trap through the Slave vector in the
Interrupt Table. If the instruction being performed is CMPf
(Section 2.2.3) and the Q bit is not set, the CPU loads Proc-
essor Status Register (PSR) bits N, Z and L from the corre-
sponding bits in the Status Word. The NS32081 FPU always
sets the L bit to zero.

TL/EE/5234 – 18

FIGURE 3-7. FPU Protocol Status Word Format

The last step in the protocol is for the CPU to read a result,
if any, and transfer it to the destination. The Read cycles
from the FPU are performed by the CPU while applying
Status Code 01 (Section 4.1.2).

TABLE 3-1. General Instruction Protocol

Step

Status

Action

1

11

CPU sends ID Byte.

2

01

CPU sends Operation Word.

3

01

CPU sends required operands.

4

XX

FPU starts execution.

5

XX

FPU pulses SPC low.

6

10

CPU reads Status Word.

7

01

CPU reads result (if any).

3.5.2 Floating-Point Protocols

Table 3-2 gives the protocols followed for each floating-
point instruction. The instructions are referenced by their
mnemonics. For the bit encodings of each instruction, see
Section 2.2.3.

The Operand Class columns give the Access Classes for
each general operand, defining how the addressing modes
are interpreted by the CPU (see Series 32000 Instruction
Set Reference Manual).

The Operand Issued columns show the sizes of the oper-
ands issued to the Floating-Point Unit by the CPU. ‘‘D’’ indi-
cates a 32-bit Double Word. ‘‘i’’ indicates that the instruction
specifies an integer size for the operand (B

e

Byte, W

e

Word, D

e

Double Word). ‘‘f’’ indicates that the instruction

specifies a floating-point size for the operand (F

e

32-bit

Standard Floating, L

e

64-bit Long Floating).

The Returned Value Type and Destination column gives the
size of any returned value and where the CPU places it. The
PSR Bits Affected column indicates which PSR bits, if any,
are updated from the Slave Processor Status Word (

Figure

3-7 ).

Any operand indicated as being of type ‘‘f’’ will not cause a
transfer if the Register addressing mode is specified, be-
cause the Floating-Point Registers are physically on the
Floating-Point Unit and are therefore available without CPU
assistance.

TABLE 3-2. Floating Point Instruction Protocols

Mnemonic

Operand 1

Operand 2

Operand 1

Operand 2

Returned Value

PSR Bits

Class

Class

Issued

Issued

Type and Dest.

Affected

ADDf

read.f

rmw.f

f

f

f to Op. 2

none

SUBf

read.f

rmw.f

f

f

f to Op. 2

none

MULf

read.f

rmw.f

f

f

f to Op. 2

none

DIVf

read.f

rmw.f

f

f

f to Op. 2

none

MOVf

read.f

write.f

f

N/A

f to Op. 2

none

ABSf

read.f

write.f

f

N/A

f to Op. 2

none

NEGf

read.f

write.f

f

N/A

f to Op. 2

none

CMPf

read.f

read.f

f

f

N/A

N,Z,L

FLOORfi

read.f

write.i

f

N/A

i to Op. 2

none

TRUNCfi

read.f

write.i

f

N/A

i to Op. 2

none

ROUNDfi

read.f

write.i

f

N/A

i to Op. 2

none

MOVFL

read.F

write.L

F

N/A

L to Op. 2

none

MOVLF

read.L

write.F

L

N/A

F to Op. 2

none

MOVif

read.i

write.f

i

N/A

f to Op. 2

none

LFSR

read.D

N/A

D

N/A

N/A

none

SFSR

N/A

write.D

N/A

N/A

D to Op. 2

none

D

e

Double Word

i

e

Integer size (B, W, D) specified in mnemonic.

f

e

Floating-Point type (F, L) specified in mnemonic.

N/A

e

Not Applicable to this instruction.

12

Summary of Contents for NS32081-10

Page 1: ... archi tecture and powerful addressing modes of the Series 32000 micro processor family Features Y Eight on chip data registers Y 32 bit and 64 bit operations Y Supports proposed IEEE standard for binary floating point arithmetic Task P754 Y Directly compatible with NS32016 NS32008 and NS32032 CPUs Y High speed XMOSTM technology Y Single 5V supply Y 24 pin dual in line package Block Diagram TL EE ...

Page 2: ...t Instruction Set 2 3 Traps 3 0 FUNCTIONAL DESCRIPTION 3 1 Power and Grounding 3 2 Clocking 3 3 Resetting 3 0 FUNCTIONAL DESCRIPTION Continued 3 4 Bus Operation 3 4 1 Bus Cycles 3 4 2 Operand Transfer Sequences 3 5 Instruction Protocols 3 5 1 General Protocol Sequence 3 5 2 Floating Point Protocols 4 0 DEVICE SPECIFICATIONS 4 1 Pin Descriptions 4 1 1 Supplies 4 1 2 Input Signals 4 1 3 Input Output...

Page 3: ...PackageÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ4 1 Timing Specification Standard Signal Valid After Clock Edge ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ4 2 Timing Specification Standard Signal Valid Before Clock Edge ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ4 3 Clock Timing ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ...

Page 4: ...r positive or negative as shown in Table 1 2 TABLE 1 2 Sample E Fields E Field F Field Represented Value 011 110 100 0 1 5c2b1 e 0 75 011 111 100 0 1 5c20 e 1 50 100 000 100 0 1 5c21 e 3 00 Two values of the E field are not exponents 11 11 sig nals a reserved operand Section 2 1 3 00 00 repre sents the number zero if the F field is also all zeroes other wise it signals a reserved operand The S bit...

Page 5: ... Point Unit FPU TL EE 5234 4 FIGURE 2 1 Register Set 2 1 1 Floating Point Registers There are eight registers F0 F7 on the NS32081 FPU for providing high speed access to floating point operands Each is 32 bits long A floating point register is referenced whenever a floating point instruction uses the Register ad dressing mode Section 2 2 2 for a floating point operand All other Register mode usage...

Page 6: ...e this condi tion 011 Divide by zero An attempt has been made to divide a non zero floating point number by zero Dividing zero by zero is considered an Invalid Operation instead below 100 Illegal Instruction Two undefined floating point instruc tion forms are detected by the FPU as being illegal The binary formats causing this trap are xxxxxxxxxx0011xx10111110 xxxxxxxxxx1001xx10111110 101 Invalid ...

Page 7: ...n the instruction which acts upon that variable Extraneous data movement is therefore mini mized Series 32000 Addressing Modes fall into nine basic types Register In floating point instructions these addressing modes refer to a Floating Point Register F0 F7 if the op erand is of a floating point type Otherwise a CPU General Purpose Register R0 R7 is referenced See Section 2 1 1 Register Relative A...

Page 8: ...k memory disp SP SP0 or SP1 as selected in PSR 11010 Static memory disp SB 11011 Program memory adisp MEMORY RELATIVE 10000 Frame memory relative disp2 disp1 FP Disp2aPointer Pointer found at 10001 Stack memory relative disp2 disp1 SP address Disp1aRegister SP is 10010 Static memory relative disp2 disp1 SB either SP0 or SP1 as selected in PSR IMMEDIATE 10100 Immediate value None Operand is issued ...

Page 9: ... indicates a choice of addressing mode expressions This choice affects the bina ry pattern in the corresponding gen1 or gen2 field of the instruction format Figure 2 6 Refer to Table 2 1 for the options available and their patterns Further details of the exact operations performed by each instruction are found in the Series 32000 Instruction Set Reference Manual Movement and Conversion The followi...

Page 10: ...wer supply applied on pin 24 VCC See DC Electrical Characteristics table Grounding connections are made on two pins Logic Ground GNDL pin 12 is the common pin for on chip logic and Buffer Ground GNDB pin 13 is the common pin for the output drivers For optimal noise immunity it is recommend ed that GNDL be attached through a single conductor di rectly to GNDB and that all other grounding connection...

Page 11: ...CTION PROTOCOLS 3 5 1 General Protocol Sequence Slave Processor instructions have a three byte Basic In struction field consisting of an ID byte followed by an Oper ation Word See Section 2 2 3 for FPU instruction encod ings The ID Byte has three functions 1 It identifies the instruction to the CPU as being a Slave Processor instruction 2 It specifies which Slave Processor will execute it 3 It det...

Page 12: ...n The instructions are referenced by their mnemonics For the bit encodings of each instruction see Section 2 2 3 The Operand Class columns give the Access Classes for each general operand defining how the addressing modes are interpreted by the CPU see Series 32000 Instruction Set Reference Manual The Operand Issued columns show the sizes of the oper ands issued to the Floating Point Unit by the C...

Page 13: ... the FPU to signal completion of an operation Section 3 5 1 Must be held high with an external pull up resistor while floating Data Bus D0 D15 16 bit bus for data transfer D0 is the least significant bit Section 3 4 4 2 ABSOLUTE MAXIMUM RATINGS Temperature Under Bias 0 C to a70 C Storage Temperature b65 C to a150 C All Input or Output Voltages with Respect to GND b0 5V to a7 0V Power Dissipation 1...

Page 14: ...the input and output signals as illustrated in Figures 4 2 and 4 3 unless specifically stated otherwise ABBREVIATIONS L E Ð Leading Edge T E Ð Trailing Edge R E Ð Rising Edge F E Ð Falling Edge TL EE 5234 26 FIGURE 4 2 Timing Specification Standard Signal Valid After Clock Edge TL EE 5234 27 FIGURE 4 3 Timing Specification Standard Signal Valid Before Clock Edge 14 ...

Page 15: ...ts Conditions tPWR 4 5 Power Stable to After VCC 50 50 ms RST R E Reaches 4 5V tRSTw 4 6 RST Pulse Width At 0 8V 64 64 tCLKp Both Edges tSs 4 7 Status ST0 ST1 Before SPC L E 50 33 ns Setup tSh 4 7 Status ST0 ST1 After SPC L E 40 35 ns Hold tDs 4 8 D0 D15 Setup Time Before SPC T E 40 30 ns tDh 4 8 D0 D15 Hold Time After SPC T E 50 35 ns tSPCw 4 7 SPC Pulse Width At 0 8V 70 50 ns from CPU Both Edges...

Page 16: ...n Reset TL EE 5234 21 FIGURE 4 6 Non Power On Reset TL EE 5234 22 FIGURE 4 7 Read Cycle from FPU Note SPC pulse must be nominally 1 clock wide when writing into FPU TL EE 5234 23 FIGURE 4 8 Write Cycle to FPU Note SPC pulse may also be 2 clocks wide but its edges must meet the tSPCs and tSPCh requirements with respect to CLK 16 ...

Page 17: ...PC Pulse from FPU TL EE 5234 25 FIGURE 4 10 RST Release Timing Note The rising edge of RST must occur while CLK is high as shown Physical Dimensions inches millimeters Ceramic Dual In Line Package D Order Number NS32081D 10 or NS32081D 15 NS Package Number D24C 17 ...

Page 18: ...d in accordance support device or system or to affect its safety or with instructions for use provided in the labeling can effectiveness be reasonably expected to result in a significant injury to the user National Semiconductor National Semiconductor National Semiconductor National Semiconductor Corporation Europe Hong Kong Ltd Japan Ltd 1111 West Bardin Road Fax a49 0 180 530 85 86 13th Floor St...

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