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Symbol
Parameter
Conditions
Min
Typ
Max
Units
THERMAL SHUTDOWN
T
SD
Thermal Shutdown
Threshold
165
°C
T
HYS
Thermal Shutdown
Hysteresis
25
THERMAL RESISTANCE
θ
JA
Junction to Ambient
20L TSSOP EP
34
°C/W
Note 1:
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability
and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in
the Operating Ratings is not implied. The recommended Operating Ratings indicate conditions at which the device is functional and the device should not be
operated beyond such conditions.
Note 2:
All voltages are with respect to the potential at the GND pin, unless otherwise specified.
Note 3:
Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at T
J
=165°C (typical) and disengages at
T
J
=140°C (typical).
Note 4:
Junction-to-ambient thermal resistance is highly board-layout dependent. The numbers listed in the table are given for a reference layout wherein the
20L TSSOP EP package has its DAP pad populated with 9 vias. In applications where high maximum power dissipation exists, namely driving a large MosFET
at high switching frequency from a high input voltage, special care must be paid to thermal dissipation issues during board design. In high-power dissipation
applications, the maximum ambient temperature may have to be derated. Maximum ambient temperature (T
A-MAX
) is dependent on the maximum operating
junction temperature (T
J-MAX-OP
= 125°C), the maximum power dissipation of the device in the application (P
D-MAX
), and the junction-to ambient thermal resistance
of the package in the application (
θ
JA
), as given by the following equation: T
A-MAX
= T
J-MAX-OP
– (θ
JA
× P
D-MAX
). In most applications there is little need for the full
power dissipation capability of this advanced package. Under these circumstances, no vias would be required and the thermal resistances would be 104 °C/W
for the 20L TSSOP EP. It is possible to conservatively interpolate between the full via count thermal resistance and the no via count thermal resistance with a
straight line to get a thermal resistance for any number of vias in between these two limits.
Note 5:
Refer to National’s packaging website for more detailed information and mounting techniques. http://www.national.com/analog/packaging/
Note 6:
Human Body Model, applicable std. JESD22-A114-C.
Note 7:
All limits guaranteed at room temperature (standard typeface) and at temperature extremes (bold typeface). All room temperature limits are 100%
production tested. All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods. All limits are used
to calculate Average Outgoing Quality Level (AOQL).
Note 8:
Typical numbers are at 25°C and represent the most likely norm.
Note 9:
These electrical parameters are guaranteed by design, and are not verified by test.
Note 10:
The measurements were made using the standard buck-boost evaluation board from AN-1967.
Note 11:
The measurements were made using the standard boost evaluation board from AN-1969.
5
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