To mitigate this problem, a compensator should be designed
to give adequate phase margin (above 45°) at the crossover
frequency. A simple compensator using a single capacitor at
the COMP pin (C
CMP
) will add a dominant pole to the system,
which will ensure adequate phase margin if placed low
enough. At high duty cycles (as shown in
zero places extreme limits on the achievable bandwidth with
this type of compensation. However, because an LED driver
is essentially free of output transients (except catastrophic
failures open or short), the dominant pole approach, even with
reduced bandwidth, is usually the best approach. The domi-
nant compensation pole (
ω
P2
) is determined by C
CMP
and the
output resistance (R
O
) of the error amplifier (typically 5 M
Ω):
It may also be necessary to add one final pole at least one
decade above the crossover frequency to attenuate switching
noise and, in some cases, provide better gain margin. This
pole can be placed across R
SNS
to filter the ESL of the sense
resistor at the same time.
sation is physically implemented in the system.
The high frequency pole (
ω
P3
) can be calculated:
The total system transfer function becomes:
The resulting compensated loop gain frequency response
shown in
indicates that the system has adequate
phase margin (above 45°) if the dominant compensation pole
is placed low enough, ensuring stability:
300857a4
FIGURE 11. Compensated Loop Gain Frequency
Response
30085761
FIGURE 12. Start-up Waveforms
START-UP REGULATOR and SOFT-START
The LM3424 includes a high voltage, low dropout bias regu-
lator. When power is applied, the regulator is enabled and
sources current into an external capacitor (C
BYP
) connected
to the V
CC
pin. The recommended bypass capacitance for the
V
CC
regulator is 2.2 µF to 3.3 µF. The output of the V
CC
reg-
ulator is monitored by an internal UVLO circuit that protects
the device from attempting to operate with insufficient supply
voltage and the supply is also internally current limited.
The LM3424 also has programmable soft-start, set by an ex-
ternal capacitor (C
SS
), connected from SS to GND. For C
SS
to affect start-up, C
REF
> C
NTC
must be maintained so that the
converter does not start in foldback mode.
the typical start-up waveforms for the LM3424 assuming
C
REF
> C
NTC
.
First, C
BYP
is charged to be above V
CC
UVLO threshold
(~4.2V). The C
VCC
charging time (t
VCC
) can be estimated as:
Assuming there is no C
SS
or if C
SS
is less than 40% of
C
CMP
, C
CMP
is then charged to 0.9V over the charging time
(t
CMP
) which can be estimated as:
Once C
CMP
= 0.9V, the part starts switching to charge C
O
until
the LED current is in regulation. The C
O
charging time (t
CO
)
can be roughly estimated as:
If C
SS
is greater than 40% of C
CMP
, the compensation capac-
itor will only charge to 0.7V over a smaller C
CMP
charging time
(t
CMP-SS
) which can be estimated as:
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16
LM3424