National Semiconductor HPC167064, Specification Sheet

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Functional Modes of Operation
There are two primary functional modes of operation for the
HPC167064.
# EPROM Mode
#
Normal Running Mode
EPROM MODE
In the EPROM mode, the HPC167064 is configured to ‘‘ap-
proximately emulate’’ a standard NMC27C256 EPROM.
Some dissimilarities do exist. The most significant one is
that HPC167064 contains only 16 kbytes of programmable
memory, rather than the 32 kbytes in 27C256. An
HPC167064 in the EPROM mode can be programmed with
a Data I/O machine.
Given below is the list of functions that can be performed by
the user in the EPROM mode.
# Programming
CAUTION: Exceeding 14V on pin 1 (V
PP
) will damage the
HPC167064.
Initially, and after each erasure, all bits of the HPC
EPROM are in the ‘‘1’’ state. Data is introduced by selec-
tively programming ‘‘0s’’ into the desired bit locations.
Although only ‘‘0s’’ will be programmed, both ‘‘1s’’ and
‘‘0s’’ can be presented in the data word. The only way to
change a ‘‘0’’ to a ‘‘1’’ is by ultraviolet light erasure.
#
Program/verify EPROM registers
To read data (verify) during the programming process,
V
PP
must be at 13V. When reading data after the pro-
gramming process, V
PP
can be either 13V or at V
CC
.
# Program/verify ECON registers
There are two configuration registers ECON6 and
ECON7 to emulate different family members and also to
enable/disable different features in the chip. These reg-
isters are not mapped in the EPROM user space. These
bytes must be programmed through a pointer register
ECONA.
To prevent unintentional programming, the ECON6, 7
registers must be programmed with the assistance of this
pointer register. ECONA, and externally presented ad-
dress, both identify the same ECON register may be pro-
grammed.
NORMAL RUNNING MODE
In this mode, the HPC167064 executes user software in the
normal manner. By default, its arcitecture imitates that of
the HPC16064. It may be configured to emulate the
HPC16083. The addressable memory map will be exactly as
for the HPC16083. The WATCHDOG function monitors ad-
dresses accordingly. Thus, the HPC167064 can be used as
a stand-alone emulator for both HPC16064 and HPC16083.
Within this mode, the on-chip EPROM cell acts as read only
memory.
Each memory fetch is 16-bits wide. The
HPC167064 operates to 20 MHz with 1 wait state for the on-
chip memory.
The HPC167064 emulates the HPC16064 and HPC16083,
except as described here.
# The value of EXM is latched on the rising edge of
RESET. Thus, the user may not switch from ROMed to
ROMless operation or vice-versa, without another
RESET pulse.
#
The security logic can be used to control access to the
on-chip
EPROM. This feature is unique to the
HPC167064. There is no corresponding mode of opera-
tion on the HPC16064 or the HPC16083.
#
Specific inputs are allowed to be driven at high voltage
(13V) to configure the device for programming. These
high voltage inputs are unique to the HPC167064. The
same inputs cannot be driven to high voltage on the
HPC16064 and HPC16083 without damage to the part.
# The Port D input structure on this device is slightly differ-
ent from the masked ROM HPC16083 and HPC16064.
V
IH2
min and V
IL2
max are the same as for the masked
ROM HPC16083 and HPC16064. There is a V
IH2
max
requirement for this device equal to V
CC
a
0.05V. There
is also a V
IL2
min requirement for this device equal to
GND-0.05V. The V
IH2
max and V
IL2
min requirement for
the masked ROM devices is the Absolute Maximum Rat-
ings of V
CC
a
0.5V and GND-0.5V respectively.
#
The D.C. Electrical Characteristics and A.C. Electrical
Characteristics for the HPC167064, where T
A
e b
55 § C
to
a
125 § C, are guaranteed over a reduced operating
voltage range of V
CC g
5%. This is different from the
masked ROM devices that it simulates which is V
CC
g
10%. These characteristics for the HPC467064, where
T
A
e b
0 § C to
a
70 § C, are guaranteed over the masked
ROM operating voltage range which is V
CC
g
10%.
# In addition to the reduced operating voltage range for the
HPC167064, the A.C. timing parameter t
UDH
is required
to be a mimimum value of 25 ns. The masked ROM de-
vices require a mimimum t
UDH
0f 20 ns. This A.C. timing
parameter for the HPC467064 is required to be the same
as the masked ROM devices.
HPC167064 EPROM SECURITY
The HPC167064 includes security logic to provide READ
and WRITE protection of the on-chip EPROM. These de-
fined privileges are intended to deter theft, alteration, or un-
intentional destruction of user code. Two bits are used to
define four levels of security on the HPC167064 to control
access to on-chip EPROM.
Security Level 3
This is the default configuration of an erased HPC167064.
READ and WRITE accesses to the on-chip EPROM or
ECON registers may be accomplished without constraint in
EPROM mode. READ accesses to the on-chip EPROM may
be accomplished without constraint in NORMAL RUNNING
mode.
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