Receiver Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Condition/
Reference
Min
Typ
Max
Units
CLHT
LVCMOS/LVTTL Low-to-High Transition
Time, C
L
= 8pF, (
Figure 5
) (Note 8)
Register addr 28d/1ch,
bit [2] (RCLK)=0b (Default),
bit [1] (RXE) =0b (Default),
bit [0] (RXO) =0b (Default)
Rx clock out
1.45
2.10
ns
Rx data out
2.40
3.50
ns
CHLT
LVCMOS/LVTTL High-to-Low Transition
Time, C
L
= 8pF, (
Figure 5
) (Note 8)
Register addr 28d/1ch,
bit [2] (RCLK)=0b (Default),
bit [1] (RXE) =0b (Default),
bit [0] (RXO) =0b (Default)
Rx clock out
1.35
2.20
ns
Rx data out
2.40
3.60
ns
CLHT
Programmable
adjustment
LVCMOS/LVTTL Low-to-High Transition
Time, C
L
= 8pF, (
Figure 5
) (Note 8)
Register addr 28d/1ch,
bit [2] (RCLK)=1b (Default),
bit [1] (RXE) =1b (Default),
bit [0] (RXO) =1b (Default)
Rx clock out
2.45
ns
Rx data out
3.40
ns
CHLT
Programmable
adjustment
LVCMOS/LVTTL High-to-Low Transition
Time, C
L
= 8pF, (
Figure 5
) (Note 8)
Register addr 28d/1ch,
bit [2] (RCLK)=0b (Default),
bit [1] (RXE) =0b (Default),
bit [0] (RXO) =0b (Default)
Rx clock out
2.35
ns
Rx data out
3.40
ns
RCOP
RCLK OUT Period (
Figures 11, 12
) (Note 8)
8–135 MHz
7.4
T
125
ns
RCOH
RCLK OUT High Time (
Figures 11, 12
)
Rx clock out
0.4T
0.5T
0.6T
ns
RCOL
RCLK OUT Low Time (
Figures 11, 12
)
Rx clock out
0.4T
0.5T
0.6T
ns
RSRC
RxOUT Setup to RCLK OUT (
Figures 11, 12
) (Notes 8, 9)
Register addr 29d/1dh [2:1]= 00b (Default)
2.60
0.5T
ns
RHRC
RxOUT Hold to RCLK OUT (
Figures 11, 12
) (Notes 8, 9)
Register addr 29d/1dh [2:1]= 00b (Default)
3.60
0.5T
ns
RSRC/RHRC
Programmable
Adjustment
Register addr 29d/1dh [2:1] = 01b, (
Figures 13, 14
)
(Notes 2, 10)
RSRC increased from default by 1UI
RHRC decreased from default by 1UI
+1UI /
-1UI
ns
Register addr 29d/1dh [2:1] = 10b, (
Figures 13, 14
)
(Notes 2, 10)
RSRC decreased from default by 1UI
RHRC increased from default by 1UI
-1UI /
+1UI
ns
Register addr 29d/1dh [2:1] = 11b, (
Figures 13, 14
)
(Notes 2, 10)
RSRC increased from default by 2UI
RHRC decreased from default by 2UI
+2UI /
-2UI
ns
RPLLS
Receiver Phase Lock Loop Set (
Figure 6
)
10
ms
RPDD
Receiver Powerdown Delay (
Figure 7
)
100
ns
RPDL
Receiver Propagation Delay — Latency (
Figure 8
)
4*RCLK
ns
RITOL
Receiver Input Tolerance
(
Figures 10, 16
) (Notes 8, 10)
V
CM
= 1.25V,
V
ID
= 350mV
0.25
UI
Note 8:
Specification is guaranteed by characterization.
Note 9:
A Clock Unit Symbol (T) is defined as 1/ (Line rate of RCLK). E.g. For Line rate of RCLK at 85MHz, 1 T = 11.76ns
Note 10:
A Unit Interval (UI) is defined as 1/7th of an ideal clock period (RCLK/7). E.g. For an 11.76ns clock period (85MHz), 1 UI = 1.68ns
DS90C3202
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